CN111384977B - Method and device for generating parity check bits of Polar code and readable storage medium - Google Patents
Method and device for generating parity check bits of Polar code and readable storage medium Download PDFInfo
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- CN111384977B CN111384977B CN201811612326.4A CN201811612326A CN111384977B CN 111384977 B CN111384977 B CN 111384977B CN 201811612326 A CN201811612326 A CN 201811612326A CN 111384977 B CN111384977 B CN 111384977B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
Abstract
A parity check bit generation method and device of Polar code and readable storage medium, the method comprises: detecting whether N target PC bits with the same checked information bits exist in the generated PC-CA-Polar codes or not; when detecting that there are N target PC bits, sequentially determining target information bits associated with the N-1 target PC bits, including: adjusting information bits related to the ith target PC bit, wherein the information bits related to the ith target PC bit after adjustment do not coincide with the information bits related to the PC bits before the ith target PC bit; and selecting X information bits meeting preset conditions from the information bits associated with the ith target PC bit after adjustment as target information bits associated with the ith target PC bit. The scheme can effectively avoid the situation that different PC bits in the PC-CA-Polar code check the same information bit.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a parity bit generation method and apparatus for Polar codes, and a readable storage medium.
Background
Parity Check and CRC assisted Polar codes (PC-CA-Polar) have been widely used in wireless communications. The generation process of the existing PC-CA-Polar code can be briefly described as follows: performing CRC coding on an information bit sequence, and then generating PC bits; the information bit sequence and the generated CRC check bits are then fed into the Polar encoder together with the PC check bits.
When the PC-CA-Polar code is generated by adopting the existing method, the problem that different PC bits check the same information bit exists, namely, two or more than two PC bits check the same information bit.
Disclosure of Invention
The embodiment of the invention solves the technical problem that different PC bits exist in the PC-CA-Polar code and check the same information bit.
To solve the above technical problem, an embodiment of the present invention provides a method for generating parity bits of Polar codes, including: detecting whether N target PC bits with completely same checked information bits exist in the generated PC-CA-Polar code; n is more than or equal to 2; when detecting that there are N target PC bits, sequentially determining target information bits associated with the N-1 target PC bits, including: determining the target information bit associated with the ith target PC bit by adopting the following steps: adjusting the information bit associated with the ith target PC bit, wherein the information bit associated with the ith target PC bit after adjustment is not overlapped with the information bit associated with the PC bit before the ith target PC bit; selecting X information bits meeting preset conditions from the adjusted information bits associated with the ith target PC bit as target information bits associated with the ith target PC bit; the preset conditions are as follows: the Hamming weight is less than the Hamming weight of the ith target PC bit, and i is more than or equal to 2 and less than or equal to N.
Optionally, the sequentially determining target information bits associated with the N-1 target PC bits includes: and sequentially determining target information bits related to the N-1 target PC bits positioned behind according to the positions of the N target PC bits in the PC-CA-Polar code.
Optionally, the adjusting the information bits associated with the ith target PC bit includes: determining a candidate set according to the length M of the generated mother code of the PC-CA-Polar code; elements in the candidate set do not include values that have been used by a target PC bit preceding the ith target PC bit; selecting an element Pi from the candidate set, and selecting an information bit at a position with a distance from the ith target PC bit being an integral multiple of Pi as the adjusted information bit associated with the ith target PC bit in the first set; wherein the first set is: removing all elements in the third set which are the same as the elements in the second set to obtain a set; the second set is: a set of information bits associated with other PC bits except the ith target PC bit; the third set is: a set of all information bits preceding the ith target PC bit.
Optionally, the determining a candidate set according to the mother code length M of the generated PC-CA-Polar code includes: acquiring all prime numbers not greater than M; and removing the prime numbers used by the target PC bit before the ith target PC bit from all the obtained prime numbers to obtain the candidate set.
Optionally, the determining a candidate set according to the mother code length M of the generated PC-CA-Polar code includes: acquiring all positive integers not greater than M; and removing the used positive integer of the target PC bit before the ith target PC bit from all the obtained positive integers to obtain the candidate set.
Optionally, the method for generating parity bits of Polar codes further includes: and when the information bit meeting the preset condition is not selected from the information bits associated with the adjusted ith target PC bit, selecting an unused element Pj from the candidate set, and selecting the information bit at the position of which the distance from the ith target PC bit is integral multiple of Pj from the first set as the information bit associated with the adjusted ith target PC bit.
Optionally, the method for generating parity bits of Polar codes further includes: when the information bits associated with the ith target PC bit determined by any element in the candidate set do not meet the preset condition, determining that the target information bits associated with the ith target PC bit are: information bits associated with the initial i-th target PC bit in the PC-CA-Polar code.
Optionally, the selecting X information bits that meet the preset condition includes: and selecting X information bits according to the sequence of the reliability of the information bits from low to high.
Optionally, the value of X is 1 or 2.
Optionally, after determining the target information bits associated with the N-1 target PC bits, the method further includes: and updating information bits related to corresponding target PC bits in the PC-CA-Polar codes into corresponding target information bits according to the determined target information bits.
The embodiment of the present invention further provides a parity bit generation apparatus for Polar codes, including: the detection unit is used for detecting whether N target PC bits with the same checked information bits exist in the generated PC-CA-Polar codes or not; the determining unit is used for sequentially determining target information bits related to the N-1 target PC bits when the detecting unit detects that the N target PC bits exist; the determination unit includes: the adjusting subunit is used for adjusting information bits associated with an ith target PC bit, and the information bits associated with the ith target PC after adjustment are not overlapped with information bits associated with PC bits before the ith target PC bit; a selecting subunit, configured to select, from information bits associated with an ith target PC bit after adjustment, X information bits that meet a preset condition as target information bits associated with the ith target PC bit; the preset conditions are as follows: the Hamming weight is less than the Hamming weight of the ith target PC bit, and i is more than or equal to 2 and less than or equal to N.
Optionally, the determining unit is configured to sequentially determine, according to the positions of the N target PC bits in the PC-CA-Polar code, target information bits associated with N-1 target PC bits located behind the target PC bits.
Optionally, the adjusting subunit is configured to determine a candidate set according to the mother code length M of the generated PC-CA-Polar code; elements in the candidate set do not include values that have been used by a target PC bit preceding the ith target PC bit; selecting an element Pi from the candidate set, and selecting an information bit at a position with a distance from the ith target PC bit being an integral multiple of Pi as the adjusted information bit associated with the ith target PC bit in the first set; wherein the first set is: removing all elements in the third set which are the same as the elements in the second set to obtain a set; the second set is: a set of information bits associated with other PC bits than the ith target PC bit; the third set is: a set of all information bits preceding the ith target PC bit.
Optionally, the adjusting subunit is configured to obtain all prime numbers not greater than M; and removing the prime numbers used by the target PC bit before the ith target PC bit from all the obtained prime numbers to obtain the candidate set.
Optionally, the adjusting subunit is configured to obtain all positive integers not greater than M; and removing the used positive integer of the target PC bit before the ith target PC bit from all the obtained positive integers to obtain the candidate set.
Optionally, the adjusting subunit is further configured to: and when the information bit meeting the preset condition is not selected from the information bits associated with the adjusted ith target PC bit, selecting an unused element Pj from the candidate set, and selecting the information bit at the position of which the distance from the ith target PC bit is integral multiple of Pj from the first set as the information bit associated with the adjusted ith target PC bit.
Optionally, the determining unit is further configured to determine that, when none of the information bits associated with the ith target PC bit determined by any element in the candidate set satisfies a preset condition, the target information bit associated with the ith target PC bit is: information bits associated with the initial ith target PC bit in the PC-CA-Polar code.
Optionally, the selecting subunit is configured to select X information bits according to a sequence of the information bit reliabilities from low to high.
Optionally, the value of X is 1 or 2.
Optionally, the parity bit generation apparatus of Polar code further includes: and the updating unit is used for updating the information bits related to the corresponding target PC bits in the PC-CA-Polar codes into the corresponding target information bits according to the determined target information bits.
The embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium is a non-volatile storage medium or a non-transitory storage medium, and computer instructions are stored on the computer-readable storage medium, and when the computer instructions are executed, the steps of any one of the above methods for generating parity check bits of Polar codes are executed.
The embodiment of the invention also provides another parity bit generation device for Polar codes, which comprises a memory and a processor, wherein the memory stores computer instructions capable of being run on the processor, and the processor executes any one of the steps of the parity bit generation method for Polar codes when running the computer instructions.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the generated PC-CA-Polar code is checked. When two or more than two target PC bits with the same checked information bits exist in the generated PC-CA-Polar code, adjusting the information bits associated with the N-1 target PC bits positioned later, and sequentially determining the target information bits associated with the N-1 target PC bits. For N-1 target PC bits behind the target PC bit, when the associated information bits are adjusted, the information bits associated with the ith target PC bit are not overlapped with the information bits associated with the PC bits before the ith target PC bit, so that the finally determined target information bits associated with the ith target PC bit are not overlapped with the information bits associated with any PC bits before the ith target PC bit, and the condition that different PC bits exist in the PC-CA-Polar code and the same information bits are checked can be effectively avoided.
Drawings
FIG. 1 is a diagram illustrating a relationship between PC bits and information bits in a PC-CA-Polar code according to the prior art;
FIG. 2 is a flowchart of a parity bit generation method for Polar codes according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating the relationship between PC bits and information bits in the updated PC-CA-Polar code according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a parity bit generation apparatus for Polar codes in the embodiment of the present invention.
Detailed Description
As described above, in the prior art, when the PC-CA-Polar code is generated by using the existing method, there is a problem that different PC bits check the same information bit, that is, two or more PC bits check the same information bit.
For example, referring to FIG. 1, a schematic diagram of the relationship between PC bits and information bits in a PC-CA-Polar code is shown. In fig. 1, I1 to I7 are information bits, PC1, PC2, and PC3 are PC bits, the information bits verified by PC1 are I1 and I4, the information bits verified by PC2 are also I1 and I4, and the information bits verified by PC3 are I5 and I7. Thus, the presence of two PC bits in the PC-CA-Polar code checks the same information bit.
In the embodiment of the invention, for N-1 target PC bits behind the position, when the associated information bits are adjusted, the information bits associated with the ith target PC bit are not overlapped with the information bits associated with the PC bits before the ith target PC bit, so that the finally determined target information bits associated with the ith target PC bit are not overlapped with the information bits associated with any PC bit before the ith target PC bit, and the condition that different PC bits exist in the PC-CA-Polar code and check the same information bits can be effectively avoided.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a parity bit generation method for Polar codes, and the method is described in detail by referring to fig. 2 through specific steps.
Step S201, detecting whether N target PC bits with the same checked information bits exist in the generated PC-CA-Polar codes.
In a specific implementation, existing schemes may be employed to generate the PC-CA-Polar codes. The generation process of the existing PC-CA-Polar code can be briefly described as follows: performing CRC coding on an information bit sequence, and then generating PC bits; the information bit sequence and the generated CRC check bits are then fed into the Polar encoder together with the PC check bits. The specific generation process of the PC-CA-Polar code can refer to the prior art, and the invention is not described in detail.
When the prior art is adopted to generate the PC-CA-Polar code, the information bits checked by different PC bits may be identical. In the embodiment of the invention, when the information bits verified by different PC bits are completely the same, the PC bit with the completely same verified information bit is taken as the target PC bit.
For example, referring to fig. 1, the information bits verified by PC1 and PC2 are I1 and I4, and therefore PC1 and PC2 are the target PC bits.
Step S202, when detecting that N target PC bits exist, sequentially determining target information bits related to the N-1 target PC bits.
In specific implementation, when detecting that there are N target PC bits in the generated PC-CA-Polar code, the information bits associated with one of the target PC bits may be kept unchanged, and the target information bits associated with the remaining N-1 target PC bits are sequentially determined.
In the embodiment of the present invention, information bits associated with the first target PC bit in the PC-CA-Polar code may be kept unchanged according to the positions of all target PC bits in the PC-CA-Polar code, and information bits associated with the later N-1 target PC bits may be adjusted once to obtain target information bits associated with the later N-1 target PC bits.
For example, if there are 3 target PC bits in the PC-CA-Polar code, the information bit associated with the first target PC bit appearing in the PC-CA-Polar code is kept unchanged, and the information bit associated with the second target PC bit and the information bit associated with the third target PC bit appearing in the PC-CA-Polar code are adjusted in sequence to obtain the target information bit associated with the second target PC bit and the information bit associated with the third target PC bit.
In the embodiment of the invention, when the target information bits associated with the N-1 target PC bits are determined in sequence, the target information bit associated with the next target PC bit can be determined after the target information bit associated with one target PC bit is determined.
For example, in the generated PC-CA-Polar code, the information bit corresponding to the 1 st target PC bit is kept unchanged, and the target information bit corresponding to the 2 nd target PC bit is determined. After the determination of the target information bit corresponding to the 2 nd target PC bit is completed, the target information bit corresponding to the 3 rd target PC bit is determined, and so on.
In a specific implementation, when determining a target information bit associated with an ith target PC bit, information bits associated with the ith target PC bit in the generated PC-CA-Polar code may be adjusted, and information bits associated with the adjusted ith target PC bit do not overlap with information bits associated with PC bits before the ith target PC bit.
After the information bits associated with the adjusted ith target PC bit are obtained, X information bits meeting the preset condition are selected from the information bits associated with the adjusted ith target PC bit to serve as target information bits associated with the ith target PC bit. In the embodiment of the present invention, the preset condition may be: the hamming weight is less than the hamming weight of the ith target PC bit.
In practical applications, the hamming weight is the hamming distance of a character string relative to a zero character string of the same length. That is, the hamming weight is the number of non-zero elements in the string. For a binary string, the hamming weight is the number of 1's in the string. For example, 1101 has a Hamming weight of 3.
When selecting the X information bits meeting the preset condition, the X information bits can be selected according to the sequence of the reliability of the information bits from low to high.
For the ith target PC bit, the number of the corresponding target information bits is X. Usually, the number of information bits checked by one PC bit is 1 or 2. Therefore, in the embodiment of the present invention, the value of X may be 1 or 2. It should be noted that the value of X may also be other positive integers. In practical application, the value of X can be determined according to specific application scenarios and application requirements.
The following describes the process of adjusting the information bits associated with the ith target PC bit in detail.
In the embodiment of the present invention, adjusting the information bits associated with the ith target PC bit means: and adjusting information bits related to the ith target PC bit in the generated PC-CA-Polar code.
When the information bit associated with the ith target PC bit is adjusted, a candidate set may be determined according to the mother code length M of the generated PC-CA-Polar code.
In the embodiment of the present invention, the elements in the candidate set may be prime numbers not greater than M, and prime numbers used by PC bits positioned before the i-th target PC bit are not included in the candidate set.
For example, the length of the mother code M =8, the prime number used by the 1 st target PC bit is 2, and the elements in the candidate set corresponding to the 2 nd target PC bit include 3, 5, and 7. In other words, the candidate sets corresponding to different target PC bits may be different.
In the embodiment of the present invention, the elements in the candidate set may also be positive integers not greater than M, and the prime numbers used by the PC bits positioned before the ith target PC bit are not included in the candidate set.
For example, the length of the mother code M =8, and the integer used by the 1 st target PC bit is 1, then the element in the candidate set corresponding to the 2 nd target PC bit includes 2, 3, 4, 5, 6, 7, and 8.
After determining the candidate set corresponding to the ith target PC bit, an element Pi may be selected from the candidate set. In the first set, information bits at positions spaced apart from the ith target PC by an integer multiple of Pi are selected as information bits associated with the ith target PC bit after adjustment.
In the embodiment of the present invention, a set of information bits associated with other PC bits except the ith target PC bit may be obtained first as a second set; thereafter, all information bits preceding the ith target PC bit are obtained as a third set. And removing all elements in the second set, which are the same as the elements in the third set, and taking the obtained set as the first set.
Continuing with the illustration of fig. 1.
The element Pi =3 selected from the candidate set, and the i-th target PC bit is PC2. The second set is a set of information bits associated with other PC bits than PC2, i.e. a set of information bits associated with PC1 and PC3, wherein the elements include I1, I4, I5, I7. The third set is a set of all information bits before PC2, the elements of which include I1 to I7.
And removing the elements in the third set, which are the same as the elements in the second set, to obtain a first set, wherein the elements in the first set comprise I2, I3 and I6.
In the first set, information bits at positions at integral multiples of Pi =3 from PC2 are selected. As is clear from fig. 1, since the information bits at an integer multiple of 3 away from PC2 are I3, I3 is set as the information bits associated with PC2 after adjustment.
After the hamming weight corresponding to I3 is judged to be less than the hamming weight of PC2, the target information bit corresponding to PC2 can be determined to be I3.
In specific implementation, after the target information bits associated with the N-1 target PC bits are determined, the generated PC-CA-Polar codes can be updated.
In the embodiment of the present invention, when updating the generated PC-CA-Polar code, the information bits associated with the target PC bits for which the target information bits are determined are updated to the corresponding target information bits in the PC-CA-Polar code.
In a specific implementation, after the target information bit associated with the ith target PC bit is determined, the generated PC-CA-Polar code may be updated. And when the generated PC-CA-Polar code is updated, updating the information bit associated with the ith target PC bit in the generated PC-CA-Polar code to the determined target information bit.
Referring to FIG. 3, a schematic diagram of the relationship between PC bits and information bits in the updated PC-CA-Polar code is shown.
In the initially generated PC-CA-Polar code, the information bits associated with PC2 are I1 and I4. By adopting the method provided by the embodiment of the invention, the target information bit associated with the PC2 is I3. Therefore, in the updated PC-CA-Polar code, the information bit associated with PC2 is I3.
In a specific implementation, the following scenarios may exist: and failing to select information bits meeting the preset condition from the information bits associated with the adjusted ith target PC bit determined according to the element Pi. For example, the information bit associated with the adjusted PC2 determined according to the element Pi is I3, but I3 does not meet the preset condition.
At this time, an element Pj that has not been used may be selected from the candidate set, and information bits at positions that are integer multiples of Pj apart from the i-th target PC bit may be selected again in the first set as information bits associated with the adjusted i-th target PC bit.
That is, when an information bit satisfying a preset condition cannot be selected from information bits associated with an i-th target PC bit determined according to the element Pi, another unused element may be selected from the candidate set to re-determine an information bit associated with the i-th target PC bit, and X information bits satisfying the preset condition may be selected from the re-determined information bits associated with the i-th target PC bit as target information bits corresponding to the i-th target PC bit.
If the information bits associated with the adjusted ith target PC bit corresponding to the element Pj do not satisfy the preset condition, other unused elements may be continuously selected from the candidate set to readjust the information bits associated with the ith target PC bit.
In a specific application, if the information bits associated with the ith target PC bit after adjustment corresponding to all elements in the candidate set do not satisfy a preset condition, the target information bits associated with the ith target PC bit are: and information bits related to ith target PC bits in the generated PC-CA-Polar codes. That is, the information bits associated with the ith target PC bit are kept unchanged.
For example, in the generated PC-CA-Polar code, the information bits associated with PC2 are I1 and I4. The elements in the candidate set include 3 and 5. The information bits associated with the adjusted PC2 corresponding to Pi =3 do not satisfy the preset condition, and the information bits associated with the adjusted PC2 corresponding to Pi =5 do not satisfy the preset condition, at this time, the target information bits associated with the PC2 are I1 and I4.
The obtained adjusted information bit associated with the ith target PC bit and the target information bit associated with the ith target PC bit have two different concepts. The target information bit associated with the ith target PC bit is determined from the adjusted information bit associated with the ith target PC bit.
Therefore, for N-1 target PC bits behind the position, when the associated information bits are adjusted, the information bits associated with the ith target PC bit are not overlapped with the information bits associated with the PC bits before the ith target PC bit, so that the finally determined target information bits associated with the ith target PC bit are not overlapped with the information bits associated with any PC bits before the ith target PC bit, and the condition that different PC bits exist in the PC-CA-Polar code and the same information bits are checked can be effectively avoided.
The method for generating parity bits of Polar codes provided in the above embodiments of the present invention is described below with an embodiment.
And generating the PC-CA-Polar code according to the design scheme of the existing PC-CA-Polar code. And acquiring the mapping relation between all PC bits and information bits in the generated PC-CA-Polar code, and judging whether two or more than two PC bits check completely same information bits.
And detecting that two PC bits check completely the same information bit, wherein the two PC bits are PC1 and PC2 respectively, and the information bits checked by the PC1 and the PC2 are I1 and I4 respectively. And keeping the information bits verified by the PC1 as I1 and I4 unchanged, and adjusting the information bits verified by the PC2.
When the information bits checked by the PC2 are adjusted, the set of the information bits checked by other PC bits except for the PC2 is set as A, and the set of the information bits positioned before the PC2 in the PC-CA-Polar code is set as B. And removing the same information bits in the set B as the set A to obtain a set C.
And according to the length N of the mother code of the PC-CA-Polar code, taking the prime numbers from 1 to N to form a set P, and deleting the prime numbers used by the PC1 from the set P to obtain a set P'. And selecting one element Pi from the set P', and selecting information bits at positions with integral multiple Pi distances from the PC2 from the set C to form an adjusted information bit set Di corresponding to the PC2.
And calculating the Hamming weight d (PC) of the PC2, and calculating the Hamming weight d (Di) of each information bit in the set Di, wherein the size of the set Di is | Di |. According to the sequence of the reliability of the information bits from low to high, X information bits meeting the requirement that d (Di) < d (PC) are selected as the information bits corresponding to the PC2, and the value of X is 1 or 2. If no information bit satisfying d (Di) < d (PC) is found in the set Di, selecting an unused prime number Pj from the set P again, and readjusting the information bit related to the PC2 according to the Pj.
And if the information bits meeting the condition that d (Di) < d (PC) cannot be found by using any element in the set P after the traversal of the set P is completed, keeping the information bits for PC bit check to be I1 and I4 unchanged.
The parity bit generation method of Polar code provided in the above embodiment of the present invention is described below by another embodiment.
And generating the PC-CA-Polar code according to the design scheme of the existing PC-CA-Polar code. And acquiring the mapping relation between all PC bits and information bits in the generated PC-CA-Polar code, and judging whether two or more than two PC bits check the completely same information bits.
And detecting that two PC bits check completely the same information bit, wherein the two PC bits are PC1 and PC2 respectively, and the information bits checked by the PC1 and the PC2 are I1 and I4 respectively. And keeping the information bits verified by the PC1 as I1 and I4 unchanged, and adjusting the information bits verified by the PC2.
When the information bits checked by the PC2 are adjusted, the set of information bits checked by other PC bits except for the PC2 is set as A, and the set of information bits positioned before the PC2 in the PC-CA-Polar code is set as B. And removing the same information bits in the set B as the set A to obtain a set C.
And according to the length N of the mother code of the PC-CA-Polar code, taking an integer set P consisting of 1 to N, and deleting the integer used by the PC1 from the set P to obtain a set P'. And selecting one element Pi from the set P', and selecting information bits at positions with integral multiple of Pi away from the PC2 from the set C to form an adjusted information bit set Di corresponding to the PC2.
And calculating the Hamming weight d (PC) of the PC2, and calculating the Hamming weight d (Di) of each information bit in the set Di, wherein the size of the set Di is | Di |. According to the sequence of the reliability of the information bits from low to high, X information bits meeting the requirement that d (Di) < d (PC) are selected as the information bits corresponding to the PC2, and the value of X is 1 or 2. If no information bit satisfying d (Di) < d (PC) is found in the set Di, selecting an unused prime number Pj from the set P again, and readjusting the information bit related to the PC2 according to the Pj.
And if the information bits meeting the condition that d (Di) < d (PC) cannot be found by using any element in the set P after the traversal of the set P is completed, keeping the information bits for PC bit check to be I1 and I4 unchanged.
The difference between the two examples is that the elements in the set P used in the first embodiment are prime numbers, while the elements in the set P used in the second embodiment are integers.
Referring to fig. 4, a parity bit generating apparatus 40 of Polar code in the embodiment of the present invention is shown, including:
a detecting unit 41, configured to detect whether N target PC bits with identical verified information bits exist in the generated PC-CA-Polar code;
a determining unit 42, configured to sequentially determine target information bits associated with N-1 target PC bits when the detecting unit 41 detects that N target PC bits exist; the determination unit 42 includes: an adjusting subunit 421, configured to adjust an information bit associated with an ith target PC bit, where the adjusted information bit associated with the ith target PC does not coincide with an information bit associated with a PC bit before the ith target PC bit; a selecting subunit 422, configured to select, from information bits associated with the adjusted ith target PC bit, X information bits that meet a preset condition as target information bits associated with the ith target PC bit; the preset conditions are as follows: the Hamming weight is less than the Hamming weight of the ith target PC bit, and i is more than or equal to 2 and less than or equal to N.
In a specific implementation, the determining unit 42 is configured to sequentially determine, according to the positions of the N target PC bits in the PC-CA-Polar code, target information bits associated with N-1 target PC bits located behind.
In a specific implementation, the adjusting subunit 421 is configured to determine a candidate set according to the length M of the mother code of the generated PC-CA-Polar code; elements in the candidate set do not include values for which a target PC bit preceding the ith target PC bit has been used; selecting an element Pi from the candidate set, and selecting an information bit at a position with a distance from the ith target PC bit being an integral multiple of Pi as the adjusted information bit associated with the ith target PC bit in the first set; wherein the first set is: removing all elements in the third set which are the same as the elements in the second set to obtain a set; the second set is: a set of information bits associated with other PC bits than the ith target PC bit; the third set is: a set of all information bits preceding the ith target PC bit.
In a specific implementation, the adjusting subunit 421 is configured to obtain all prime numbers not greater than M; and removing prime numbers used by the target PC bit before the ith target PC bit from all the obtained prime numbers to obtain the candidate set.
In a specific implementation, the adjusting subunit 421 is configured to obtain all positive integers not greater than M; and removing the used positive integer of the target PC bit before the ith target PC bit from all the obtained positive integers to obtain the candidate set.
In a specific implementation, the adjusting subunit 421 is further configured to: and when the information bit meeting the preset condition is not selected from the information bits associated with the adjusted ith target PC bit, selecting an unused element Pj from the candidate set, and selecting the information bit at the position of which the distance from the ith target PC bit is integral multiple of Pj from the first set as the information bit associated with the adjusted ith target PC bit.
In a specific implementation, the determining unit 42 is further configured to determine that, when none of the information bits associated with the ith target PC bit determined by any element in the candidate set satisfies a preset condition, the target information bit associated with the ith target PC bit is: information bits associated with the initial i-th target PC bit in the PC-CA-Polar code.
In a specific implementation, the selecting subunit 422 is configured to select X information bits in an order from a low reliability to a high reliability of the information bits.
In specific implementation, the value of X is 1 or 2.
In a specific implementation, the parity bit generating device of Polar code further includes: and the updating unit is used for updating the information bits related to the corresponding target PC bits in the PC-CA-Polar codes into the corresponding target information bits according to the determined target information bits.
The embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium is a non-volatile storage medium or a non-transitory storage medium, and has computer instructions stored thereon, and when the computer instructions are executed, the steps of the parity bit generation method for Polar codes according to any of the above embodiments of the present invention are executed.
The embodiment of the invention also provides another parity bit generation device for Polar codes, which comprises a memory and a processor, wherein the memory stores computer instructions, and the processor executes the steps of the parity bit generation method for Polar codes in any embodiment of the invention when running the computer instructions stored in the memory.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by instructing the relevant hardware through a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
Claims (22)
1. A method for generating parity bits of Polar codes is characterized by comprising the following steps:
detecting whether N target PC bits with completely same checked information bits exist in the generated PC-CA-Polar codes or not; n is more than or equal to 2;
when detecting that there are N target PC bits, sequentially determining target information bits associated with the N-1 target PC bits, including: determining the target information bit associated with the ith target PC bit by adopting the following steps: adjusting the information bit associated with the ith target PC bit, wherein the information bit associated with the ith target PC bit after adjustment is not overlapped with the information bit associated with the PC bit before the ith target PC bit; selecting X information bits meeting preset conditions from the adjusted information bits associated with the ith target PC bit as target information bits associated with the ith target PC bit; the preset conditions are as follows: the Hamming weight is less than the Hamming weight of the ith target PC bit, and i is more than or equal to 2 and less than or equal to N.
2. The method for generating parity bits for Polar codes according to claim 1, wherein said sequentially determining target information bits associated with N-1 target PC bits comprises:
and sequentially determining target information bits related to the N-1 target PC bits positioned behind according to the positions of the N target PC bits in the PC-CA-Polar code.
3. The method for generating parity bits for Polar code according to claim 1, wherein said adjusting information bits associated with said ith target PC bit comprises:
determining a candidate set according to the length M of the generated mother code of the PC-CA-Polar code; elements in the candidate set do not include values for which a target PC bit preceding the ith target PC bit has been used;
selecting an element Pi from the candidate set, and selecting an information bit at a position with a distance from the ith target PC bit being an integral multiple of Pi as the adjusted information bit associated with the ith target PC bit in the first set;
wherein the first set is: removing all elements in the third set which are the same as the elements in the second set to obtain a set; the second set is: a set of information bits associated with other PC bits than the ith target PC bit; the third set is: a set of all information bits preceding the ith target PC bit.
4. The method for generating parity bits for Polar codes according to claim 3, wherein said determining a candidate set according to the mother code length M of said generated PC-CA-Polar codes comprises:
acquiring all prime numbers not greater than M;
and removing the prime numbers used by the target PC bit before the ith target PC bit from all the obtained prime numbers to obtain the candidate set.
5. The method for generating parity bits for Polar codes according to claim 3, wherein said determining a candidate set according to the mother code length M of the generated PC-CA-Polar codes comprises:
acquiring all positive integers not greater than M;
and removing the used positive integer of the target PC bit before the ith target PC bit from all the obtained positive integers to obtain the candidate set.
6. The method for generating parity bits for Polar codes according to claim 3, further comprising:
and when the information bit meeting the preset condition is not selected from the information bits associated with the adjusted ith target PC bit, selecting an unused element Pj from the candidate set, and selecting the information bit at the position of which the distance from the ith target PC bit is integral multiple of Pj from the first set as the information bit associated with the adjusted ith target PC bit.
7. The method for generating parity bits for Polar codes according to claim 6, further comprising: when the information bits associated with the ith target PC bit determined by any element in the candidate set after adjustment do not meet a preset condition, determining that the target information bits associated with the ith target PC bit are: information bits associated with the initial ith target PC bit in the PC-CA-Polar code.
8. The method for generating parity bits of Polar codes according to claim 1, wherein said selecting X information bits satisfying a predetermined condition comprises:
and selecting X information bits according to the sequence of the reliability of the information bits from low to high.
9. The method for generating parity bits for Polar codes according to claim 8, wherein the value of X is 1 or 2.
10. The method for generating parity bits for Polar codes according to claim 1, wherein after determining the target information bits associated with N-1 target PC bits, further comprising:
and updating information bits related to corresponding target PC bits in the PC-CA-Polar codes into corresponding target information bits according to the determined target information bits.
11. An apparatus for generating parity bits for Polar codes, comprising:
the detection unit is used for detecting whether N target PC bits with the same checked information bits exist in the generated PC-CA-Polar codes or not;
the determining unit is used for sequentially determining target information bits related to N-1 target PC bits when the detecting unit detects that N target PC bits exist; the determination unit includes: the adjusting subunit is used for adjusting the information bit associated with the ith target PC bit, and the information bit associated with the ith target PC after adjustment is not overlapped with the information bit associated with the PC bit before the ith target PC bit; a selecting subunit, configured to select, from information bits associated with an ith target PC bit after adjustment, X information bits that meet a preset condition as target information bits associated with the ith target PC bit; the preset conditions are as follows: the Hamming weight is less than the Hamming weight of the ith target PC bit, and i is more than or equal to 2 and less than or equal to N.
12. The apparatus for generating parity bits for Polar codes according to claim 11, wherein said determining unit is configured to sequentially determine target information bits associated with N-1 target PC bits located behind according to the positions of the N target PC bits in the PC-CA-Polar codes.
13. The apparatus for generating parity bits for Polar codes according to claim 11, wherein said adjusting subunit is configured to determine a candidate set according to a mother code length M of said generated PC-CA-Polar codes; elements in the candidate set do not include values that have been used by a target PC bit preceding the ith target PC bit; selecting an element Pi from the candidate set, and selecting information bits at positions with integral multiple of Pi of the distance between the information bits and the ith target PC bit from the first set as the adjusted information bits related to the ith target PC bit; wherein the first set is: removing all elements in the third set which are the same as the elements in the second set to obtain a set; the second set is: a set of information bits associated with other PC bits than the ith target PC bit; the third set is: a set of all information bits preceding the ith target PC bit.
14. The apparatus for generating parity bits for Polar codes according to claim 13, wherein said adjusting subunit is configured to obtain all prime numbers not greater than M; and removing the prime numbers used by the target PC bit before the ith target PC bit from all the obtained prime numbers to obtain the candidate set.
15. The apparatus for generating parity bits for Polar codes according to claim 13, wherein said adjusting subunit is configured to obtain all positive integers not greater than M; and removing the used positive integer of the target PC bit before the ith target PC bit from all the obtained positive integers to obtain the candidate set.
16. The parity bit generating apparatus of Polar code according to claim 13, wherein said adjusting subunit is further configured to: and when the information bits meeting the preset condition are not selected from the information bits associated with the adjusted ith target PC bit, selecting an unused element Pj from the candidate set, and selecting the information bits at the position of integral multiple of Pj, which is the distance between the information bits and the ith target PC bit, from the first set as the information bits associated with the adjusted ith target PC bit.
17. The apparatus for generating parity bits for Polar codes according to claim 16, wherein the determining unit is further configured to determine, when none of the information bits associated with the ith adjusted target PC bit determined by any element in the candidate set satisfies a preset condition, that the target information bit associated with the ith target PC bit is: information bits associated with the initial i-th target PC bit in the PC-CA-Polar code.
18. The apparatus for generating parity bits for Polar codes according to claim 11, wherein said selecting subunit is configured to select X information bits in order from low reliability to high reliability.
19. The apparatus for generating parity bits for Polar codes according to claim 18, wherein X takes a value of 1 or 2.
20. The parity bit generating apparatus of Polar code according to claim 11, further comprising: and the updating unit is used for updating the information bits related to the corresponding target PC bits in the PC-CA-Polar codes into the corresponding target information bits according to the determined target information bits.
21. A computer readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, having computer instructions stored thereon, wherein the computer instructions, when executed by a processor, perform the steps of the parity bit generation method of Polar code according to any one of claims 1 to 10.
22. An apparatus for generating parity bits for Polar codes, comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, and the processor executes the computer instructions to perform the steps of the method for generating parity bits for Polar codes according to any one of claims 1 to 10.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018030927A1 (en) * | 2016-08-11 | 2018-02-15 | Telefonaktiebolaget Lm Ericsson (Publ) | Selection of an error correcting code based on a target information length and a target parity length |
| CN108365914A (en) * | 2017-01-26 | 2018-08-03 | 华为技术有限公司 | Polar code coding/decoding methods and device |
| CN108540141A (en) * | 2017-03-02 | 2018-09-14 | 华为技术有限公司 | Polar code coding/decoding methods and device |
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| CN108574494B (en) * | 2017-03-13 | 2020-08-25 | 华为技术有限公司 | Coding and decoding method and device |
| CN107425857A (en) * | 2017-06-19 | 2017-12-01 | 华为技术有限公司 | One kind polarization code coding/decoding method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018030927A1 (en) * | 2016-08-11 | 2018-02-15 | Telefonaktiebolaget Lm Ericsson (Publ) | Selection of an error correcting code based on a target information length and a target parity length |
| CN108365914A (en) * | 2017-01-26 | 2018-08-03 | 华为技术有限公司 | Polar code coding/decoding methods and device |
| CN108540141A (en) * | 2017-03-02 | 2018-09-14 | 华为技术有限公司 | Polar code coding/decoding methods and device |
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