CN111384958B - Data compression device and related product - Google Patents
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- CN111384958B CN111384958B CN201811607224.3A CN201811607224A CN111384958B CN 111384958 B CN111384958 B CN 111384958B CN 201811607224 A CN201811607224 A CN 201811607224A CN 111384958 B CN111384958 B CN 111384958B
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- 238000012545 processing Methods 0.000 claims abstract description 100
- 238000007906 compression Methods 0.000 claims abstract description 90
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/60—General implementation details not specific to a particular type of compression
- H03M7/6017—Methods or arrangements to increase the throughput
- H03M7/6029—Pipelining
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
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Abstract
The application relates to a data compression device and related products, including: at least one compression pipeline, and each compression pipeline includes at least two stages of pipelined compressed data units, the pipelined compressed data units comprising: an encoding circuit, a selection circuit, and a bypass channel; the compression pipeline is used for realizing multistage compression processing on input data; the selection circuit is used for determining input data output to the coding circuit in the next stage of pipeline compressed data unit according to the input control signal. The data compression device can realize the compression processing of the data by flexibly configuring the coding mode, greatly reduce the data volume and improve the compression efficiency of the data.
Description
Technical Field
The present invention relates to the field of information processing technologies, and in particular, to a data compression device and a related product.
Background
With the continuous development of information technology, especially with the continuous development of various machine learning algorithms, the data volume is increasing, and in the process of transmitting data and processing data, the requirements of people on the data access and data processing speed are increasing.
Currently, in order to meet the above requirements, in the process of data transmission and processing, a common data encoding method, such as Huffman encoding, run-length encoding, LZW encoding, arithmetic encoding, etc., is generally adopted, and an encoding hardware circuit corresponding to the data encoding method is designed to implement compression encoding of data, and the compressed data is transmitted or processed. In practical applications, the compression processing of data is generally implemented by using one of the above-mentioned encoding circuits.
However, the compression coding method is often inflexible, has a small amount of reduced data, and has a low efficiency.
Disclosure of Invention
The application provides a data compression device and related products, which can realize flexible configuration of coding modes, compress data, greatly reduce data volume and improve data compression efficiency.
In a first aspect, an embodiment of the present application provides a data compression apparatus, including: at least one compression pipeline, each compression pipeline comprising at least two stages of pipelined compressed data units, the pipelined compressed data units comprising: an encoding circuit, a selection circuit, and a bypass channel; wherein the encoding modes of the encoding circuits in the pipeline compressed data units of each stage are different; the output end of the coding circuit is connected with the input end of a selection circuit in the same-level pipeline compressed data unit on the current compression pipeline; the output end of the selection circuit is respectively connected with one end of the bypass channel in the next-stage pipeline compressed data unit on the current compression pipeline and the input end of the coding circuit in the next-stage pipeline compressed data unit on the current compression pipeline, and the other end of the bypass channel is connected with the input end of the selection circuit in the next-stage pipeline compressed data unit on the current compression pipeline; the compression pipeline is used for realizing multistage compression processing of input data; the selection circuit is used for determining input data output to the coding circuit in the next stage of pipeline compressed data unit according to the input control signal.
In a second aspect, embodiments of the present application provide a computing device for performing machine learning computations, the computing device including an arithmetic unit and a control unit; the arithmetic unit includes: a master processing circuit and a plurality of slave processing circuits; the main processing circuit includes: the data compression device according to the first aspect, and a main operation circuit; the slave processing circuit includes: the data compression device according to the first aspect, and a slave operation circuit;
the control unit is used for acquiring original data, an operation instruction and a control instruction and sending the original data, the operation instruction and the control instruction to the main processing circuit;
the main processing circuit is used for executing compression processing on the original data and transmitting data and operation instructions with the plurality of auxiliary processing circuits;
the slave processing circuits are used for executing intermediate operation in parallel according to the data and operation instructions transmitted from the master processing circuit to obtain a plurality of intermediate results, compressing the intermediate results and transmitting the compressed intermediate results to the master processing circuit;
the main processing circuit is also used for executing subsequent processing on the intermediate result after the compression processing to obtain a calculation result.
In a third aspect, embodiments of the present application provide a machine learning chip including the computing device of the second aspect.
In a fourth aspect, embodiments of the present application provide a chip package structure, where the chip package structure includes the machine learning chip described in the third aspect.
In a fifth aspect, an embodiment of the present application provides a board, where the board includes the chip package structure described in the fourth aspect.
In a sixth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the board card in the fifth aspect.
According to the data compression device and the related products, each compression pipeline in the data compression device comprises at least two stages of pipeline compression data units, and the coding modes of the coding circuits in each stage of pipeline compression data units are different, so that the data compression device can realize multiple compression processing on input data, the data quantity is greatly reduced, meanwhile, the selection circuits in each stage of pipeline compression data units can select whether to output data output by each coding circuit or not through setting different control signals, the combination of the coding circuits is realized, and the combined coding circuits are adopted to compress the input data, so that the data compression device provided by the application can flexibly configure the corresponding coding modes to compress the input data according to the actual application requirements, and the data compression efficiency is improved.
In addition, the data compression device comprises at least one compression pipeline, so that simultaneous compression processing can be realized on a plurality of input parallel data, and the data compression device provided by the application can further improve the speed of parallel processing data.
Drawings
FIG. 1 is a schematic diagram of a data compression device according to one embodiment;
FIG. 2 is a schematic diagram of a data compression device according to one embodiment;
FIG. 2A is a schematic diagram of a data compression device according to one embodiment;
FIG. 3 is a schematic diagram of a data compression device according to one embodiment;
FIG. 4 is a schematic diagram of a data compression device according to one embodiment;
FIG. 5 is a schematic diagram of a computing device provided by one embodiment;
FIG. 6 is a schematic diagram of a computing device provided by one embodiment;
fig. 7 is a schematic diagram of a board according to an embodiment.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims of this application and in the drawings, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Fig. 1 is a schematic diagram of a data compression device according to an embodiment. The data compression device is used for realizing compression processing operation on the received data. As shown in fig. 1, the data compression apparatus includes: at least one compression pipeline (01, 02, 03 in the figure), each compression pipeline comprising at least two stages of pipelined compressed data units (10, 11, 12 in the figure); the pipelined compressed data units of each stage include: the encoding circuit (100, 110 and 120 in the figure), the selection circuit (101, 111 and 121 in the figure) and the bypass channel (102, 112 and 122 in the figure), wherein the encoding modes of the encoding circuits in the pipeline compressed data units of each stage are different; the output end of the coding circuit is connected with the input end of a selection circuit in the same-level pipeline compressed data unit on the current compression pipeline; the output end of the selection circuit is respectively connected with one end of a bypass channel in a next-stage pipeline compressed data unit on the current compression pipeline and the input end of an encoding circuit in the next-stage pipeline compressed data unit on the current compression pipeline, and the other end of the bypass channel is connected with the input end of the selection circuit in the next-stage pipeline compressed data unit on the current compression pipeline; the compression pipeline is used for realizing multistage compression processing of input data;
the selection circuit is used for determining input data output to the coding circuit in the next stage of pipeline compressed data unit according to the input control signal.
It should be noted that, the structure of the data compression device shown in fig. 1 is an alternative scheme, and the application environment is: when the data compression device receives a plurality of data at the same time and needs to compress the data at the same time, the data compression device can comprise a plurality of parallel compression pipelines to realize the simultaneous compression processing of the input data, each compression pipeline can comprise a plurality of stages of pipeline compression data units, and each stage of pipeline compression data units on each compression pipeline can be arranged in a cascade connection relationship, so that the multistage compression processing of the data is realized. In this embodiment, the multi-stage pipeline compressed data units on the multiple parallel compressed pipelines may be used to perform simultaneous compression processing operation on different input data, and output the compressed result at the output end of each compressed pipeline.
Optionally, the data compression device shown in fig. 1 may further include only one compression pipeline, so as to implement multi-stage compression processing on the input single data, and the data compression device may be suitable for an application scenario of serial data transmission. The following embodiments will be described with the structure of such a data compression device.
In the above-mentioned data compression device, the coding circuit is configured to compress input data by using a preset coding scheme, and output the compressed data. The coding modes can comprise a plurality of coding modes, and a user can select a corresponding coding mode, namely a corresponding coding circuit, according to actual application requirements so as to realize compression processing of data. In this embodiment, the encoding modes of the encoding circuits in the pipeline compressed data units of each stage are different, so that the data compression device provided by the application can select different encoding circuits to compress input data according to application requirements. For example, the coding modes adopted by the coding circuits 100, 110, 120, etc. in the figures are different, and the user may select only the coding circuit 100, or only the coding circuit 110, or may select both the coding circuit 100 and the coding circuit 110 according to actual needs.
Alternatively, the bypass channel is a hardware line that implements a physical direct connection, which may be a bypass, or alternatively, a pass-through circuit. The bypass path 112 in the present embodiment directly connects the selection circuit 101 of the previous stage and the selection circuit 111 of the present stage, and transmits the output data of the selection circuit 101 of the previous stage to the selection circuit 111 of the present stage.
Alternatively, the selection circuit may be a 2-out-of-1 selector, which may include two data input ports, a control signal input port, and a data output port, where the selector may be specifically configured to gate one of the two data input ports according to the control signal received by the control signal input port, so that the data output port of the selector may output the data received on one of the data input ports. The control signal may be a strobe signal for gating the two data input ports of the selection circuit. It may be a high-low level signal, for example, a high level signal 1 and a low level signal 0, and assuming that the selection circuit has two data input ports, namely, a 1# port and a 0# port, and the 1# port corresponds to the high level signal 1 and the 0# port corresponds to the low level signal 0, the high level signal 1 may control the selection circuit to gate the data on the 1# port to output, and the low level signal 0 may control the selection circuit to gate the data on the 0# port to output.
In practical application, each stage of the pipeline compressed data unit can select whether to use the coding circuit in the stage of pipeline compressed data unit to compress the data output by the coding circuit in the previous stage by controlling the selection circuit, if the stage of the pipeline compressed data unit is used, the control signal controls the selection circuit in the stage of pipeline compressed data unit to output the data compressed by the coding circuit, and if the stage of the pipeline compressed data unit is not used, the control signal controls the selection circuit in the stage of pipeline compressed data unit to output the data transmitted on the bypass channel.
For example, the structure of one compression pipeline 01 in the data compression apparatus shown in fig. 1 is illustrated, where the encoding circuit 100 in the pipeline compressed data unit 10 of the first stage in the drawing applies a corresponding encoding method to compress the obtained original data, and sends the result after the compression to the 1# port of the selection circuit 101 of the present stage. Meanwhile, the 0# port of the selection circuit 101 of the present stage can receive the original data. When the selection circuit 101 of the present stage receives a control signal for gating the 1# port, the selection circuit 101 outputs data on the 1# port, i.e., compressed data output by the encoding circuit 100 of the present stage; accordingly, when the selection circuit 101 receives a control signal for gating the 0# port, the selection circuit 101 outputs data on the 0# port, i.e., raw data; when the first stage of the pipeline compressed data unit 10 completes the corresponding operation, the data output from the present stage is sent to the encoding circuit 110 and the bypass channel 112 in the second stage of the pipeline compressed data unit 11, respectively. Similarly, when which encoding circuit is required to compress the data, the control signal controls the selection circuit of the stage to output the output data of the encoding circuit. As can be seen from the above process, the compressed data finally output by the data compression device may be compressed data output after being compressed by all stages of encoding circuits (for example, 100, 110, 120 in the figure), compressed data output after being compressed by part of the stages of encoding circuits (for example, 100 and 110 in the figure), or original data output without any stage of encoding circuits.
The data compression device provided in the above embodiment includes: at least one compression pipeline, each compression pipeline comprising at least two stages of pipelined compressed data units; and the pipelined compressed data unit comprises: the device comprises a coding circuit, a selection circuit and a bypass channel, wherein the coding modes of the coding circuits in the pipeline compressed data units of each stage are different; the output end of the coding circuit is connected with the input end of a selection circuit in the same-level pipeline compressed data unit on the current compression pipeline; the output end of the selection circuit is respectively connected with one end of a bypass channel in a next-stage pipeline compressed data unit on the current compression pipeline and the input end of an encoding circuit in the next-stage pipeline compressed data unit on the current compression pipeline, and the other end of the bypass channel is connected with the input end of the selection circuit in the next-stage pipeline compressed data unit on the current compression pipeline; the compression pipeline is used for realizing multistage compression processing of input data; the selection circuit is used for determining input data output to the coding circuit in the next stage of pipeline compressed data unit according to the input control signal. In the data compression process, each compression pipeline in the data compression device comprises at least two stages of pipeline compression data units, and the coding modes of the coding circuits in each stage of pipeline compression data units are different, so that the data compression device can realize multiple compression processing on input data, the data volume is greatly reduced, meanwhile, the selection circuits in each stage of pipeline compression data units can select whether to output data output by each coding circuit or not through setting different control signals, the combination of a plurality of coding circuits is realized, and the combined coding circuits are adopted to compress the input data, so that the data compression device provided by the application can flexibly configure the corresponding coding modes to compress the input data according to the actual application requirements, and the data compression efficiency is improved.
In addition, the data compression device comprises at least one compression pipeline, so that simultaneous compression processing can be performed on a plurality of input parallel data, and the data compression device provided by the application can further improve the speed of parallel processing data.
Fig. 2 is a schematic diagram of a data compression device according to an embodiment. As shown in fig. 2, the data compression device further comprises a control unit 13, and the control unit 13 is connected to the input terminal of the selection circuit (101, 111, 121 in the figure). Wherein the control unit 13 is arranged to output a control signal.
Alternatively, the control unit 13 may be a controller that outputs a high-low level signal, specifically, the control unit 13 may generate a corresponding high-low level signal according to an instruction input by a user, and then send the high-low level signal to a selection circuit connected to the high-low level signal; alternatively, the control unit 13 may also receive control signals sent by other circuits, perform decoding processing on the received control signals, generate corresponding high-low level signals, and send the high-low level signals to a selection circuit connected thereto.
In this embodiment, the data compression device may flexibly configure different encoding circuits (100, 110, 120 in the figure) through the control unit 13 and the selection circuits (101, 111, 121 in the figure) in each pipeline compressed data unit (10, 11, 12 in the figure), so that the data compression device may select an appropriate encoding circuit to compress the input original data according to the actual application requirement, and obtain compressed data.
The above configuration process is exemplified, as shown in fig. 2A, the data compression device in the figure includes three pipeline compressed data units, namely pipeline compressed data unit a, pipeline compressed data unit b and pipeline compressed data unit c, and the control unit D is connected to the selection circuit a, the selection circuit b and the selection circuit c, respectively. Wherein the control unit D transmits a control signal of a high-low level. When the control unit D sends a high-level signal (1) to the selection circuit a, the control unit D sends a low-level signal (0) to the selection circuit b, and the control unit D sends a high-level signal (1) to the selection circuit c, the data output by the coding circuit a in the figure is selected to be output by the selection circuit a, and the data output by the coding circuit c is selected to be output by the selection circuit c, so that the data compression device in the figure sequentially compresses the input data by adopting the combination of the coding circuit a and the coding circuit c. Therefore, different control signals correspond to different coding modes, and a user can flexibly configure the coding circuit by inputting different control signals according to actual application requirements to compress input data.
Fig. 3 is a schematic diagram of a data compression device according to an embodiment. As shown in fig. 3, the data compression device further includes a storage unit 14, where the storage unit 14 is connected to input ends of the encoding circuit 100 and the selection circuit 101 in the first stage of pipeline compressed data unit, respectively; and the storage unit 14 is used for storing the raw data.
The original data is data to be subjected to compression processing, and may be stored in the storage unit 14 in advance. The hardware circuit corresponding to the storage unit 14 may be a register, a cache, or a memory RAM, which is not limited in this embodiment.
In this embodiment, the encoding circuit 100 in the first stage pipeline compressed data unit 10 may obtain the original data from the storage unit 14, and simultaneously perform compression processing on the original data by adopting a corresponding encoding mode to obtain compressed data, and then send the compressed data to a 1# data input port of the selection circuit 101, where in addition, the data received on the 0# data input port of the selection circuit 101 may be the original data in the storage unit 14. In this application scenario, the data output from the output port of the selection circuit 101 in the first stage pipeline compressed data unit 10 may be the original data or the compressed data output from the encoding circuit 100 of the present stage according to the control signal. For example, when the control signal is a high-low level signal, one option may be to: the high level signal controls the selection circuit 101 to output the compressed data, and the low level signal controls the selection circuit 101 to output the original data.
Optionally, the encoding mode of the encoding circuit in each pipeline compressed data unit may be at least one of run-length encoding, huffman encoding, LZ77 encoding and JPEG encoding. Alternatively, the encoding mode of the encoding circuit may be other modes capable of performing compression encoding on the data.
Optionally, if the encoding mode of the encoding circuit in the pipelined compressed data unit is huffman encoding, the encoding circuit in the pipelined compressed data unit may include: an address table look-up circuit and a compressed data table look-up circuit; the input end of the address table look-up circuit is connected with the output end of the selection circuit in the previous stage of the pipeline compressed data unit, and the output end of the address table look-up circuit is connected with the input end of the compressed data table look-up circuit; the output end of the compressed data table look-up circuit is connected with the input end of the selection circuit in the same-level pipeline compressed data unit.
The address table look-up circuit is used for outputting addresses corresponding to data output by the selection circuit in the previous stage of the stream compression data unit. Specifically, the address table look-up circuit stores an address list, and a plurality of addresses are recorded in the address list. The compressed data table look-up circuit is used for outputting compressed data corresponding to the address output by the address table look-up circuit. Specifically, the compressed data table look-up circuit stores a compressed data list, and a plurality of compressed data and a plurality of corresponding addresses are recorded in the compressed data list.
In this embodiment, when the address lookup circuit receives the data output by the selection circuit in the previous stage of the compressed data unit, optionally, the address lookup circuit may sequentially find the corresponding addresses from the address list according to the order of receiving the data, and output the found addresses to the compressed data lookup circuit. When the compressed data table look-up circuit receives the address, the compressed data table can be searched, the compressed data corresponding to the address in the compressed data table can be searched according to the address, and the searched compressed data is output to the selection circuit connected with the compressed data table.
In one embodiment, the application further provides a data compression device based on the run-length coding and Huffman coding circuit. The data compression device combines a run-length coding mode and a Huffman coding mode to realize the compression processing of the original data. For this compression processing, the following embodiment will give a specific explanation in connection with the schematic configuration of the data compression apparatus shown in fig. 4.
An exemplary illustration is shown in fig. 4. The data compression device comprises a pipeline compressed data unit A and a pipeline compressed data unit B, wherein an encoding circuit in the pipeline compressed data unit A is a run-length encoding circuit, an encoding circuit in the pipeline compressed data unit B is a Huffman encoding circuit, and the Huffman encoding circuit further comprises an address table look-up circuit and a compressed data table look-up circuit. In this embodiment, when the data compression device needs to compress original data, the run-length encoding circuit compresses the received original data and outputs the compressed data a to the selection circuit a, and when the control signal a is 0, the selection circuit a outputs the original data, and when the control signal a is 1, the selection circuit a outputs the data a; then, the selection circuit a sends the output data (original data or data a) to the address lookup circuit connected with the selection circuit a, the address lookup circuit looks up the address on the address list according to the data a, and outputs the address a corresponding to the data a to the compressed data lookup circuit, the compressed data lookup circuit looks up the compressed data corresponding to the address a in the compressed data list according to the address a, and sends the compressed data B to the selection circuit B connected with the compressed data lookup circuit B, at this time, when the control signal a is 0 or 1 and the control signal B is 1, the selection circuit B outputs the compressed data B, when the control signal a is 1 and the control signal B is 0, the selection circuit B outputs the data a, and when the control signal a is 0 and the control signal B is 0, the selection circuit B outputs the original data. In summary, the above data compression apparatus may implement four processing operations on the original data by setting the control signal a and the control signal B, one is to perform the compression processing operation on the original data only by using the huffman coding mode, one is to perform the compression processing operation on the original data only by using the run-length coding mode, one is to perform the compression processing operation on the original data by using the cascade mode of the run-length coding and the huffman coding, and one is to directly output the original data without performing the compression processing operation on the original data.
The data compression device described in all the embodiments above can be applied in different scenarios, for example, it can be applied in all systems requiring data transmission, and also in all systems requiring data processing. A computing device comprising a data compression device according to any of the embodiments described above is described next.
FIG. 5 is a schematic diagram of a computing device for performing machine learning computation according to one embodiment, as shown in FIG. 5, the computing device includes an arithmetic unit 20 and a control unit 21; the operation unit 20 includes: a master processing circuit 201 and a plurality of slave processing circuits 202; the main processing circuit 201 includes: a data compression device 2011 and a main operation circuit 2012; the slave processing circuit 202 includes: a data compression device 2021, and a slave computing circuit 2022;
the control unit 21 is configured to obtain the raw data, the operation instruction, and the control instruction, and send the raw data, the operation instruction, and the control instruction to the main processing circuit 201;
the master processing circuit 201 is configured to perform compression processing on the original data, and to transmit data and operation instructions to the plurality of slave processing circuits 202; a plurality of slave processing circuits 202, configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit 201 to obtain a plurality of intermediate results, and compress the plurality of intermediate results and transmit the compressed results to the master processing circuit 201;
based on the above application, the main processing circuit 201 is further configured to perform subsequent processing on the intermediate result after the compression processing, to obtain a calculation result.
In this embodiment, the data compression device is applied to the arithmetic unit 20, and realizes data interaction between the master processing circuit 201 and the slave processing circuit 202 in the arithmetic unit 20. The specific data interaction process is as follows: when the main processing circuit 201 acquires the original data from the control unit 21, the data compression device 2011 performs compression processing on the original data to obtain compressed data, and then sends the compressed data to the sub-processing circuit 202; the slave computing circuit 2022 in the slave processing circuit 202 performs a computation (e.g., a product operation) on the received data to obtain an intermediate result, then sends the intermediate result to the data compression device 2021 to perform compression processing to obtain a compressed intermediate result, and sends the compressed intermediate result to the main processing circuit 201, and the main computing circuit 2012 in the main processing circuit 201 performs a computation (e.g., an accumulation and operation or an activation operation) on the received intermediate result to obtain a computation result, and sends the computation result to the data compression device 2011 to cause the data compression device 2011 to compress the target computation result to obtain a compressed computation result.
Optionally, as shown in the schematic structure of the computing device shown in fig. 6, the computing device may further include a storage unit 22, where the storage unit 22 is connected to the main processing circuit 201, and based on this application, the main processing circuit 201 is further configured to send the result of the calculation to the storage unit 22.
In this embodiment, the main processing circuit 201 may directly obtain the original data from the storage unit 22, and then perform corresponding processing on the original data. After the main processing circuit 201 performs the corresponding operation to obtain the final calculation result, the calculation result may be sent to the storage unit 22 for storage for use by other circuits. Note that, the calculation result may be a calculation result after the compression processing by the data compression device 2011, or alternatively, may be a calculation result after the compression processing by the data compression device 2011.
In the process of executing the machine learning operation, the computing device according to the embodiment of the invention includes the data compression device, and the data compression device can greatly reduce the data volume and has higher compression efficiency, so that the computing device improves the data transmission efficiency when executing the machine learning operation and transmitting and processing the data, thereby improving the operation rate of the computing device.
In one embodiment, the present application also provides a machine learning chip that includes the computing device described above.
In one embodiment, the present application further provides a chip package structure, which includes the chip.
In one embodiment, the present application further provides a board card, which includes the above chip package structure. Referring to fig. 7, the board card may further include other mating components in addition to the chip package structure 81, including but not limited to: a memory device 82, an interface device 83, and a control device 84; the memory device 82 is connected to the machine learning chip 811 in the chip package 81 through a bus for storing data, and the memory device 82 may include a plurality of sets of memory cells 821. Each set of the memory units 821 is connected to the machine learning chip 811 via a bus. It is understood that each set of the memory cells 821 may be a DDR SDRAM (Double Data Rate SDRAM, double Rate synchronous dynamic random Access memory).
DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include 4 sets of the memory cells. Each set of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip may include 4 72-bit DDR4 controllers therein, where 64 bits of the 72-bit DDR4 controllers are used to transfer data and 8 bits are used for ECC verification. In one embodiment, each set of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each storage unit.
The interface device 83 is electrically connected to a machine learning chip 811 within the chip package structure 81. The interface device 83 is used to implement data transmission between the machine learning chip 811 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 83 may be a standard PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface. For example, the data to be processed is transferred to the machine learning chip by the server through a standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X10 interface transmission is adopted, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 83 may be another interface, which is not limited to the specific form of the other interface, and the interface device may be capable of implementing a switching function. In addition, the calculation result of the machine learning chip 811 is still transmitted back to an external device (e.g., a server) by the interface device 83.
The control device 84 is electrically connected to the machine learning chip 811. The control device 84 is used to monitor the status of the chip. Specifically, the machine learning chip 811 and the control device 84 may be electrically connected through an SPI (Serial Peripheral Interface ) interface. The control device may comprise a single chip microcomputer (Micro Controller Unit, MCU). The machine learning chip may comprise a plurality of data processing devices and/or a combination processing device, and may drive a plurality of loads. Therefore, the machine learning chip can be in different working states such as multi-load and light-load. The control device 84 can regulate the operating states of a plurality of data processing devices and/or combined processing devices in the machine learning chip.
In some embodiments, an electronic device is provided that includes the above board card. The electronic device includes a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, an intelligent terminal, a cell phone, a vehicle recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an aircraft, a ship and/or a vehicle; the household appliances comprise televisions, air conditioners, microwave ovens, refrigerators, electric cookers, humidifiers, washing machines, electric lamps, gas cookers and range hoods; the medical device includes a nuclear magnetic resonance apparatus, a B-mode ultrasonic apparatus, and/or an electrocardiograph apparatus.
Those skilled in the art will also appreciate that the embodiments described in the specification are all alternative embodiments and that the acts and modules referred to are not necessarily required in the present application. In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units described above may be implemented either in hardware or in software program modules.
The integrated units, if implemented in the form of software program modules, may be stored in a computer-readable memory for sale or use as a stand-alone product. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the processes of the above embodiments may be performed by hardware associated with a program, which may be stored in a computer readable memory, and the memory may include: flash disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A data compression apparatus comprising at least one compression pipeline, each compression pipeline comprising at least two stages of pipelined compressed data units, the pipelined compressed data units comprising: an encoding circuit, a selection circuit, and a bypass channel; wherein the encoding modes of the encoding circuits in the pipeline compressed data units of each stage are different; the output end of the coding circuit is connected with the input end of a selection circuit in the same-level pipeline compressed data unit on the current compression pipeline; the output end of the selection circuit is respectively connected with one end of a bypass channel in a next-stage pipeline compressed data unit on the current compression pipeline and the input end of an encoding circuit in the next-stage pipeline compressed data unit on the current compression pipeline, and the other end of the bypass channel is connected with the input end of the selection circuit in the next-stage pipeline compressed data unit on the current compression pipeline;
the compression pipeline is used for realizing multistage compression processing of input data;
the selection circuit is used for determining input data output to the coding circuit in the next stage of pipeline compressed data unit according to the input control signal;
the data compression device further comprises a control unit, wherein the control unit is connected with the input end of the selection circuit and is used for outputting the control signal;
the data compression device also comprises a storage unit which is respectively connected with the input ends of the coding circuit and the selection circuit in the first-stage pipeline compressed data unit; the storage unit is used for storing the original data.
2. The apparatus of claim 1, wherein the encoding circuit encodes at least one of run-length encoding, huffman encoding, LZ77 encoding, and JPEG encoding.
3. The apparatus of claim 2, wherein if the coding scheme of the coding circuit is huffman coding, the coding circuit comprises: an address table look-up circuit and a compressed data table look-up circuit; the input end of the address table look-up circuit is connected with the output end of the selection circuit in the previous stage of pipeline compressed data unit, and the output end of the address table look-up circuit is connected with the input end of the compressed data table look-up circuit; the output end of the compressed data table look-up circuit is connected with the input end of the selection circuit in the same-level pipeline compressed data unit.
4. The apparatus of claim 1, wherein the selection circuit is a one-out-of-two selector.
5. A computing device for performing machine learning calculations, the computing device comprising an arithmetic unit and a control unit; the arithmetic unit includes: a master processing circuit and a plurality of slave processing circuits; the main processing circuit includes: the data compression apparatus according to any one of claims 1 to 4, and a main operation circuit; the slave processing circuit includes: the data compression apparatus according to any one of claims 1 to 4, and a slave operation circuit;
the control unit is used for acquiring original data, an operation instruction and a control instruction and sending the original data, the operation instruction and the control instruction to the main processing circuit;
the main processing circuit is used for executing compression processing on the original data and transmitting data and operation instructions with the plurality of auxiliary processing circuits;
the slave processing circuits are used for executing intermediate operation in parallel according to the data and operation instructions transmitted from the master processing circuit to obtain a plurality of intermediate results, compressing the intermediate results and transmitting the compressed intermediate results to the master processing circuit;
the main processing circuit is also used for executing subsequent processing on the intermediate result after the compression processing to obtain a calculation result.
6. The apparatus of claim 5, further comprising a memory unit coupled to the main processing circuit, the main processing circuit further configured to send the calculation result to the memory unit.
7. A machine learning chip comprising the computing device of claim 5 or 6.
8. A chip package structure comprising the machine learning chip of claim 7.
9. A board comprising the chip package structure of claim 8.
10. An electronic device comprising the board card of claim 9.
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| CN201811607224.3A CN111384958B (en) | 2018-12-27 | 2018-12-27 | Data compression device and related product |
| PCT/CN2019/121056 WO2020114283A1 (en) | 2018-12-07 | 2019-11-26 | Data processing method and device |
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| CN201811607224.3A CN111384958B (en) | 2018-12-27 | 2018-12-27 | Data compression device and related product |
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