CN111384869A - Frequency-division staggered power supply control circuit and high-power supply - Google Patents
Frequency-division staggered power supply control circuit and high-power supply Download PDFInfo
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- CN111384869A CN111384869A CN202010148242.0A CN202010148242A CN111384869A CN 111384869 A CN111384869 A CN 111384869A CN 202010148242 A CN202010148242 A CN 202010148242A CN 111384869 A CN111384869 A CN 111384869A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
- H02M7/53803—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration with automatic control of output voltage or current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a frequency-division staggered power supply control circuit and a high-power supply, which comprise a sampling circuit, a signal modulation circuit and a phase staggered processing circuit; the sampling circuit is directly connected with the signal modulation circuit or is in isolated feedback connection with the signal modulation circuit, and the signal modulation circuit is connected with the phase interleaving processing circuit; the sampling circuit is used for sampling the output electric signal of the power supply and outputting the sampling signal to the signal modulation circuit; the signal modulation circuit is used for processing the sampling signal and outputting a pulse width signal to the phase interleaving processing circuit; the phase interleaving processing circuit is used for receiving the pulse width signals output by the signal modulation circuit, taking the frequency of the pulse width signals as the main control frequency of the pulse width signals when the frequency of the pulse width signals meets a first preset condition, and processing the pulse width signals into two paths of signals which are interleaved in a frequency division manner. The scheme can solve the problems of large power loss and low efficiency during standby and light load of a high-power supply using an old integrated control chip, so that the high-power supply meets the requirements of energy conservation and emission reduction.
Description
Technical Field
The invention relates to the field of high-power supplies, in particular to a frequency-division staggered power supply control circuit and a high-power supply.
Background
The flyback topology can be selected for the power supply topology below 100W, and chip manufacturers and power supply manufacturers in China do not worry about supply interruption, but the power supply with the power supply above 100W needs to use control topologies such as forward, half-bridge and staggered, and needs to use a foreign power supply integrated control chip, so that once the power supply is not supplied, the power supply enterprise lives worry.
Under the condition that no foreign high-end high-power integrated control chip can be used, domestic manufacturers can only use control chips before half a century, such as UC3846 and SG3525, the standby loss of the high-power supply using the chips is large, the requirements of energy conservation and environmental protection cannot be met, the protection function of the control chips is not strong, a large number of peripheral circuits need to be lapped to increase the protection capability of the chips, and the reliability of the power supply is reduced.
Therefore, how to use the control chip technology which is mature at present in China to make the effect of the control chip of foreign manufacturers is the problem to be solved by the invention.
Disclosure of Invention
The invention provides a frequency-division staggered power supply control circuit and a high-power supply.
The technical scheme adopted by the invention for solving the technical problems is as follows: a frequency division interleaved power supply control circuit is constructed, and comprises a sampling circuit, a signal modulation circuit and a phase interleaving processing circuit;
the sampling circuit is directly connected with the signal modulation circuit or is in isolation feedback connection with the signal modulation circuit, and the signal modulation circuit is connected with the phase interleaving processing circuit;
the sampling circuit is used for sampling the output electric signal of the power supply and outputting the sampling signal to the signal modulation circuit;
the signal modulation circuit is used for processing the sampling signal and outputting a pulse width signal to the phase interleaving processing circuit;
the phase interleaving processing circuit is used for receiving the pulse width signals output by the signal modulation circuit, taking the frequency of the pulse width signals as the main control frequency of the pulse width signals when the frequency of the pulse width signals meets a first preset condition, and processing the pulse width signals into two paths of signals which are interleaved in a frequency division manner.
Further, in the frequency-division interleaved power supply control circuit of the present invention, the first preset condition is: the frequency of the pulse width signal output by the signal modulation circuit is 50-100 times of the preset frequency of the phase interleaving processing circuit.
Furthermore, the frequency division interleaved power supply control circuit comprises a phase interleaved pulse width output circuit connected with the phase interleaved processing circuit;
the phase-interleaved pulse width output circuit is used for driving a load to work.
Furthermore, in the frequency-division-interleaved power supply control circuit of the present invention, the phase-interleaved pulse width output circuit is a push-pull driving circuit.
Furthermore, the frequency division interleaved power supply control circuit of the invention also comprises a pulse width driving output circuit connected between the signal modulation circuit and the phase interleaving circuit,
the pulse width driving output circuit is used for transmitting the single-path pulse width signal output by the signal modulation circuit to the phase interleaving processing circuit.
Further, the frequency-division interleaved power control circuit of the present invention, the pulse width driving output circuit includes: a first resistor R1 and a first capacitor C1;
one end of the first resistor R1 is connected to the signal modulation circuit, and the other end of the first resistor R1 is connected to the phase interleaving processing circuit via the first capacitor C1.
Further, the frequency-division interleaved power supply control circuit according to the present invention includes: a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a phase-interleaved integrated control chip U1,
the fifth pin CT of the phase-interleaved integrated control chip U1 is grounded in series through the second capacitor C2 and the second resistor R2, the fourth resistor R4 is directly connected between the fifth pin CT and the seventh pin DISCHRG of the phase-interleaved integrated control chip U1, the sixth pin RT of the phase-interleaved integrated control chip U1 is grounded through the third resistor R3, the eighth pin S-S of the phase-interleaved integrated control chip U1 is grounded, and the twelfth pin GND of the phase-interleaved integrated control chip U1 is grounded;
when the frequency of the pulse width signal output by the signal modulation circuit is 50-100 times of the frequency of the sawtooth wave on the fifth pin CT of the phase-interleaved integrated control chip U1, the phase-interleaved integrated control chip U1 takes the frequency of the pulse width signal output by the signal modulation circuit as the main control frequency and processes the pulse width signal output by the signal modulation circuit into a pulse width signal with two frequency divisions, and the pulse width signal is output through the eleventh pin OUT-a and the fourteenth pin OUT-B of the phase-interleaved integrated control chip U1.
Furthermore, in the frequency division interleaved power supply control circuit of the invention, the sampling circuit is a current sampling circuit and/or a voltage sampling circuit;
the current sampling circuit is used for sampling an output current signal of the switching power supply, filtering the current signal and then providing the filtered current signal to the signal modulation circuit;
the voltage sampling circuit is used for sampling an output voltage signal of the switching power supply and filtering the voltage signal and then providing the filtered voltage signal to the signal modulation circuit.
Furthermore, in the frequency division interleaved power control circuit of the present invention, the signal modulation circuit is a pulse width modulation circuit or a frequency modulation circuit;
when the signal modulation circuit is a pulse width modulation circuit, a pulse width signal with fixed frequency is output;
and when the signal modulation circuit is a frequency modulation circuit, the signal modulation circuit outputs a variable-frequency pulse width signal.
The invention also provides a high-power supply which comprises the frequency division interleaved power supply control circuit.
The implementation of the invention has the following beneficial effects: the problems that the power consumption of a high-power supply using an old integrated control chip is large during standby and the efficiency is low during light load can be solved, so that the high-power supply meets the requirements of energy conservation and emission reduction.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram of a frequency-division interleaved power control circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of a frequency-division interleaved power control circuit according to the present invention;
fig. 3 is a schematic block diagram of a second embodiment of a frequency-division interleaved power control circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a frequency-division interleaved power control circuit according to a first embodiment of the present invention. The frequency division staggered power supply control circuit can be arranged in a power supply, the power loss of a traditional high-power supply in a standby state can be effectively reduced by the circuit, the problem of low efficiency in a light load state is solved, and the power supply can meet the requirements of energy conservation and emission reduction. The high power supply may be, for example, a high power supply of 100W or more.
As shown in fig. 1, in the first embodiment of the present invention, the frequency-division-interleaved power control circuit includes a sampling circuit 10, a signal modulation circuit 20, and a phase-interleaving processing circuit 30;
the sampling circuit 10 is directly connected or connected with the signal modulation circuit 20 in an isolation feedback mode, and the signal modulation circuit 20 is connected with the phase interleaving processing circuit 30;
the sampling circuit 10 is used for sampling the output electric signal of the power supply and outputting the sampling signal to the signal modulation circuit 20;
the signal modulation circuit 20 is configured to process the sampling signal and output a pulse width signal to the phase interleaving circuit 30;
the phase interleaving processing circuit 30 is configured to receive the pulse width signal output by the signal modulation circuit 30, and when the frequency of the pulse width signal satisfies a first preset condition, use the frequency of the pulse width signal as its main control frequency and process the pulse width signal into two paths of signals interleaved in frequency division.
Specifically, the first preset condition is as follows: the frequency of the pulse width signal outputted from the signal modulation circuit 20 is 50-100 times of the preset frequency of the phase interleaving circuit 30.
The high-power switching power supply using the old integrated control chip only realizes high-power supply through the phase interleaving processing circuit 30, but the power supply of the scheme is generally designed for constant-frequency output, that is, the output frequency of the switching power supply is not changed under the condition of no-load or light load output, so that the loss is increased under the condition of no-load or light load output of the switching power supply, and the effect of energy saving cannot be achieved. Meanwhile, the chip used in the scheme has poor protection performance on the switching power supply, and a large number of peripheral circuits and components need to be lapped to achieve the perfect protection function of the current switching power supply, so that the cost is increased, and the reliability of the power supply is reduced.
In this embodiment, by adding the sampling circuit 10 and the signal modulation circuit 20, the power supply to which the frequency-division interleaved power supply control circuit is applied can operate at the maximum operating frequency when the power supply is fully loaded, and can operate or wait at a lower operating frequency when the power supply is unloaded or lightly loaded, so as to achieve the energy-saving effect.
As shown in fig. 2, the frequency-division interleaved power supply control circuit of the present embodiment further includes a phase-interleaved pulse width output circuit 40 connected to the phase-interleaved processing circuit 30 based on the first embodiment; the phase-interleaved pulse width output circuit 40 is used for driving the load to work.
Specifically, the phase-interleaved pulse width output circuit 40 is a push-pull driving circuit, and the push-pull driving circuit increases the driving capability of the two channels of frequency-division-interleaved signals output by the phase-interleaved processing circuit 30 in a push-pull driving manner.
Further, a pulse width driving output circuit 50 is further included, which is connected between the signal modulation circuit 20 and the phase interleaving circuit 30, and the pulse width driving output circuit 50 is configured to transmit the single pulse width signal output by the signal modulation circuit 20 to the phase interleaving circuit 30. The pulse width drive output circuit 50 can suppress the high frequency component of the pulse width signal output from the signal modulation circuit 20, thereby improving the anti-interference capability of the circuit.
Specifically, the sampling circuit 10 is a current sampling circuit and/or a voltage sampling circuit;
the current sampling circuit is used for sampling an output current signal of the switching power supply, filtering the current signal and supplying the filtered current signal to the signal modulation circuit 20;
the voltage sampling circuit is used for sampling an output voltage signal of the switching power supply, filtering the voltage signal and supplying the filtered voltage signal to the signal modulation circuit 20.
It is understood that the sampling circuit 10 may select the current sampling circuit and/or the voltage sampling circuit to be used according to the control mode of the signal modulation circuit 20. The current sampling circuit is used if the signal modulation circuit 20 is in the current control mode, and the voltage control circuit is used if the signal modulation circuit 20 is in the voltage control mode.
Specifically, the signal modulation circuit 20 is a pulse width modulation circuit or a frequency modulation circuit;
when the signal modulation circuit 20 is a pulse width modulation circuit, a pulse width signal with a fixed frequency is output;
when the signal modulation circuit 20 is a frequency modulation circuit, a pulse width signal of a variable frequency is output.
When the signal modulation circuit 20 is a pulse width modulation circuit, the circuit includes a pulse width modulation chip and a switching power tube. Specifically, the pulse width modulation chip may be a UC3842 current control type pulse width modulation chip. The operation principle when the signal modulation circuit 20 is a pulse width modulation circuit is explained in detail below:
if the pwm chip is a UC3842 current-controlled pwm chip, the sampling circuit 10 is a current sampling circuit to collect the output current of the power supply, when the power supply is under light load or no load, the current is very small or 0, the duty ratio of the pulse width signal output by the pulse width modulation chip is very small, the power switch tube is in an off state for a long time or all the time, the phase interleaving processing circuit 30 cannot receive the pulse width signal output by the pulse width modulation circuit, and the phase interleaving processing circuit 30 operates at its own preset frequency, which can be understood that the preset operating frequency of the phase interleaving processing circuit 30 is low when the signal modulation circuit 20 is a pulse width modulation circuit, and therefore, the power supply operates or waits at a low operating frequency when the power supply is under light load or no load. When the power load is large or fully loaded, the current collected by the sampling circuit 10 is large, the duty ratio of the pulse width signal output by the pulse width modulation chip is large, the power switch tube is in a conducting state for a long time or is always in a conducting state, the pulse width modulation circuit outputs a pulse width signal with a fixed frequency to the phase interleaving processing circuit 30, because the frequency of the pulse width signal output by the pulse width modulation circuit is far greater than the preset working frequency of the phase interleaving processing circuit 30 (as can be understood, the condition that the frequency of the pulse width signal output by the pulse width modulation circuit is 50-100 times of the preset working frequency of the phase interleaving processing circuit 30, and the specific multiple is set as required), the phase interleaving processing circuit 30 takes the frequency of the pulse width signal output by the pulse width modulation circuit as the main control output frequency thereof, and then outputs a pulse width signal with a frequency division, and output in a push-pull driving manner through the phase-interleaved pulse width output circuit 40.
When the signal modulation circuit 20 is a frequency modulation circuit, a frequency modulation chip is included. Specifically, the frequency modulation chip may be an NCP1840 frequency modulation chip. The operation principle when the signal modulation circuit 20 is a frequency modulation circuit is explained in detail below:
the sampling circuit 10 samples the output electrical signal of the power supply and outputs the sampling signal to the signal modulation circuit 20, the signal modulation circuit 20 processes the sampling signal, and determines whether the power supply is in a full load, a heavy load, a light load or an idle load state according to the magnitude of the sampling signal, if the power supply is in the full load or the heavy load state, the signal modulation circuit 20 outputs a pulse width signal with the maximum frequency to the phase interleaving circuit 30, that is, the frequency of the pulse width signal output by the signal modulation circuit 20 is 50-100 times (the specific multiple can be set according to the actual requirement) of the preset frequency of the phase interleaving circuit 30, at this time, the phase interleaving circuit 30 takes the frequency of the pulse width signal as the main control frequency and processes the pulse width signal into two paths of signals interleaved in frequency division, and similarly, if the power supply load is heavy, as long as the frequency of the pulse width signal output by the signal modulation circuit 20 is 50-100 times of the preset frequency of the, the phase interleaving circuit 30 takes the frequency of the pulse width signal as its master frequency. If the power supply is in a light load state, the signal modulation circuit 20 will reduce the frequency of the output pulse width signal, and it can be understood that the reduced frequency cannot reach 50-100 times of the preset frequency of the phase interleaving circuit 30, and at this time, the phase interleaving circuit 30 will operate at its own preset frequency, and it can be understood that the preset frequency will be set to a lower value. If the power supply is idle, the signal modulation circuit 20 will decrease the frequency of the output pulse width signal and enter the skip cycle mode to achieve the energy saving effect.
The conventional high-power switching power supply also realizes high-power supply only through the phase interleaving processing circuit 30, but such a scheme is generally designed for constant-frequency output, and even under the condition that the output of the switching power supply is in no-load or light-load, the output frequency of the switching power supply is not changed, so that the loss is increased under the condition that the output of the switching power supply is in no-load or light-load, and the energy-saving effect cannot be achieved. Meanwhile, the chip used in the scheme has poor protection performance on the switching power supply, and a large number of peripheral circuits and components need to be lapped to achieve the perfect protection function of the current switching power supply, so that the cost is increased, and the reliability of the power supply is reduced.
In the second embodiment, the sampling circuit 10 and the signal modulation circuit 20 are used to determine the state of the power supply, and adjust the output pulse width signal according to the state of the power supply, and when the pulse width signal output by the signal modulation circuit 20 is much greater (50-100 times) than the main control frequency of the phase interleaving circuit 30, the phase interleaving circuit 30 uses the frequency of the pulse width signal as the main control frequency thereof, so that the switching power supply operates at the frequency. Otherwise, the phase interleaving circuit 30 will operate at its own preset smaller operating frequency. Therefore, when the power supply is lightly loaded or unloaded, the power supply works at a lower frequency to achieve the effect of energy conservation. Meanwhile, the scheme simplifies the high integration level, does not need a large number of peripheral circuits and components, simplifies the circuit structure, reduces the cost and improves the reliability of the power supply.
As shown in fig. 3, fig. 3 is a schematic block diagram of a second embodiment of a frequency-division interleaved power control circuit according to the present invention. In particular, the method comprises the following steps of,
the pulse width drive output circuit 50 includes: a first resistor R1 and a first capacitor C1;
one end of the first resistor R1 is connected to the signal modulation circuit 20, and the other end of the first resistor R1 is connected to the phase interleaving circuit 30 via a first capacitor C1. By the circuit, high-frequency cost in the pulse width signal output by the signal modulation circuit 20 can be inhibited from entering a next-stage circuit, and the anti-interference performance of the circuit is improved.
The phase interleaving processing circuit 30 includes: a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a phase-interleaved integrated control chip U1,
a fifth pin CT of the phase-interleaved integrated control chip U1 is grounded in series through a second capacitor C2 and a second resistor R2, a fourth resistor R4 is directly connected between the fifth pin CT and a seventh pin DISCHRG of the phase-interleaved integrated control chip U1, a sixth pin RT of the phase-interleaved integrated control chip U1 is grounded through a third resistor R3, an eighth pin S-S of the phase-interleaved integrated control chip U1 is grounded, and a twelfth pin GND of the phase-interleaved integrated control chip U1 is grounded;
when the frequency of the pulse width signal output by the signal modulation circuit 20 is 50-100 times of the sawtooth frequency at the fifth pin CT of the phase-interleaved integrated control chip U1, the phase-interleaved integrated control chip U1 will use the frequency of the pulse width signal output by the signal modulation circuit 20 as the master frequency and process the pulse width signal output by the signal modulation circuit 20 into a pulse width signal of two frequencies, and output the pulse width signal through the eleventh pin OUT-a and the fourteenth pin OUT-B of the phase-interleaved integrated control chip U1.
The phase interleaving integrated control chip U1 may be an integrated control chip such as UC3846, SG3525, TL494, or the like.
The specific working principle is as follows: the constant current source in the phase-interleaved integrated control chip U1 charges and discharges the second capacitor C2 through the fifth pin CT, a sawtooth wave is formed on the pin, and the sixth pin RT is connected to the third resistor R3 to determine the magnitude of the charging and discharging current of the second capacitor C2 from the constant current source in the U1, so as to determine the magnitude of the output frequency of the U1 chip (i.e., the preset frequency of the U1 chip). When the signal modulation circuit 20 applies a pulse width signal to the second capacitor C2 and the second resistor R2 through the first resistor R1 and the first capacitor C1, which affects the frequency of the sawtooth wave on the fifth pin CT of the chip U1, when the pulse width frequency output by the signal modulation circuit 20 is much higher than (the pulse width frequency output by the signal modulation circuit 20 is 50-100 times the sawtooth wave frequency on the CT pin) the sawtooth wave frequency on the CT pin of the fifth pin, the integrated control chip U1 takes the frequency output by the signal modulation circuit 20 as the main control output frequency, and then outputs a pulse width signal of two-times frequency by the internal circuit of the integrated control chip, so as to complete the process of frequency division interleaving control output.
In addition, the invention also provides a high-power supply, which comprises the frequency division interleaved power supply control circuit provided by any one of the embodiments. The UC3842 and NCP1840 lamp flyback control chips which are applied in large batch at present are combined with SG3525 and other integrated control chips, so that the power supply can meet the requirements of energy conservation and emission reduction at present when the power supply is applied at high power of more than 100W, namely the power consumption is very low when the power supply is loaded or lightly loaded, meanwhile, power supply enterprises do not need to stock foreign high-end high-power control chips for a long time, the capital pressure of the enterprises is reduced, and the situation that the power supply is limited by people is prevented.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A frequency division interleaved power supply control circuit is characterized by comprising a sampling circuit (10), a signal modulation circuit (20) and a phase interleaving processing circuit (30);
the sampling circuit (10) is directly connected or connected with an isolated feedback with the signal modulation circuit (20), and the signal modulation circuit (20) is connected with the phase interleaving processing circuit (30);
the sampling circuit (10) is used for sampling an output electric signal of a power supply and outputting a sampling signal to the signal modulation circuit (20);
the signal modulation circuit (20) is used for processing the sampling signal and outputting a pulse width signal to the phase interleaving processing circuit (30);
the phase interleaving processing circuit (30) is used for receiving the pulse width signal output by the signal modulation circuit (30), and when the frequency of the pulse width signal meets a first preset condition, taking the frequency of the pulse width signal as the main control frequency of the pulse width signal and processing the pulse width signal into two paths of signals which are interleaved in a frequency division manner.
2. The cross-over power control circuit of claim 1, wherein the first predetermined condition is: the frequency of the pulse width signal output by the signal modulation circuit (20) is 50-100 times of the preset frequency of the phase interleaving processing circuit (30).
3. The frequency-division interleaved power supply control circuit as claimed in claim 1 comprising a phase interleaved pulse width output circuit (40) coupled to said phase interleaving circuit (30);
the phase-interleaved pulse width output circuit (40) is used for driving a load to work.
4. A cross-over power control circuit according to claim 3, wherein the phase-interleaved pulse width output circuit (40) is a push-pull drive circuit.
5. The frequency-division interleaved power supply control circuit according to any of claims 1-4 further comprising a pulse width drive output circuit (50) connected between said signal modulation circuit (20) and said phase interleaving circuit (30),
the pulse width driving output circuit (50) is used for transmitting the single-path pulse width signal output by the signal modulation circuit (20) to the phase interleaving processing circuit (30).
6. The frequency-division interleaved power supply control circuit as claimed in claim 5 wherein said pulse width driven output circuit (50) comprises: a first resistor R1 and a first capacitor C1;
one end of the first resistor R1 is connected with the signal modulation circuit (20), and the other end of the first resistor R1 is connected with the phase interleaving processing circuit (30) through the first capacitor C1.
7. The frequency-division interleaved power supply control circuit as claimed in claim 2 wherein said phase interleaving processing circuit (30) comprises: a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a phase-interleaved integrated control chip U1,
the fifth pin CT of the phase-interleaved integrated control chip U1 is grounded in series through the second capacitor C2 and the second resistor R2, the fourth resistor R4 is directly connected between the fifth pin CT and the seventh pin DISCHRG of the phase-interleaved integrated control chip U1, the sixth pin RT of the phase-interleaved integrated control chip U1 is grounded through the third resistor R3, the eighth pin S-S of the phase-interleaved integrated control chip U1 is grounded, and the twelfth pin GND of the phase-interleaved integrated control chip U1 is grounded;
when the frequency of the pulse width signal output by the signal modulation circuit (20) is 50-100 times of the frequency of the sawtooth wave on the fifth pin CT of the phase-interleaved integrated control chip U1, the phase-interleaved integrated control chip U1 takes the frequency of the pulse width signal output by the signal modulation circuit (20) as a master frequency and processes the pulse width signal output by the signal modulation circuit (20) into a pulse width signal with two-division frequency, and the pulse width signal is output through the eleventh pin OUT-a and the fourteenth pin OUT-B of the phase-interleaved integrated control chip U1.
8. The cross-over power supply control circuit according to claim 1, wherein the sampling circuit (10) is a current sampling circuit and/or a voltage sampling circuit;
the current sampling circuit is used for sampling an output current signal of the switching power supply, filtering the current signal and supplying the filtered current signal to the signal modulation circuit (20);
the voltage sampling circuit is used for sampling an output voltage signal of the switching power supply, filtering the voltage signal and supplying the filtered voltage signal to the signal modulation circuit (20).
9. The frequency-division interleaved power supply control circuit as claimed in claim 1 wherein said signal modulation circuit (20) is a pulse width modulation circuit or a frequency modulation circuit;
when the signal modulation circuit (20) is a pulse width modulation circuit, a pulse width signal with a fixed frequency is output;
when the signal modulation circuit (20) is a frequency modulation circuit, a variable-frequency pulse width signal is output.
10. A high power supply comprising the frequency-division interleaved power supply control circuit as claimed in any one of claims 1 to 9.
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