CN111373479B

CN111373479B - Method for maximizing power efficiency in memory interface block

Info

Publication number: CN111373479B
Application number: CN201980005894.4A
Authority: CN
Inventors: M·泽哈维; M·阿斯弗; Y·扎弗里尔
Original assignee: Western Digital Technologies Inc
Current assignee: Western Digital Technologies Inc
Priority date: 2018-05-03
Filing date: 2019-02-11
Publication date: 2023-08-22
Anticipated expiration: 2039-02-11
Also published as: US20190341120A1; DE112019000162T5; US10446254B1; CN111373479A; WO2019212620A1

Abstract

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device at a first voltage level through the host interface or the memory interface to determine a first write value. The controller reads the first data test written to the memory device at a second voltage level through the same interface, either the host interface or the memory interface, to determine a first read value. The controller then changes the second voltage to a third voltage based on determining whether the first read value is equal to the first write value to dynamically change an operating voltage level of the memory device in response to changing process, voltage, and temperature conditions.

Description

Method for maximizing power efficiency in memory interface block

Cross Reference to Related Applications

The present application claims priority from U.S. application Ser. No. 15/970,832, filed on 5/3/2018, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to data storage devices and, more particularly, to interface buses between components of data storage devices.

Background

During operation of the data storage device, data may be communicated between a controller and a memory of the data storage device via a data bus that couples the controller and the memory. The speed at which data can be communicated between the controller and memory of the data storage device is an important factor. However, some common events may occur that adversely affect the speed. For example, these events may include speed limits of the data storage device itself, altering the operating temperature of the data storage device, and altering the power usage of the data storage device. Each of these events may reduce the operating speed of the data storage device and cause frequent changes in the process, voltage, and temperature (PVT) conditions of the device.

The PVT conditions of a storage device are dynamic and can vary widely between different devices and operating environments at any given time. In order to improve the reliability performance of the memory device at the maximum system frequency, the specific voltage level covering all PVT conditions is selected, and typically the specific voltage level that ensures that the device is able to handle the worst case (e.g. slow devices operating under high temperature conditions). However, this voltage level may be too high for devices with faster and improved PVT conditions, and thus, heat wastes additional power. In data storage devices with battery packs, such as mobile platforms, unnecessary heating devices may result in lost battery power and battery life.

Accordingly, there is a need in the art for a memory system that is capable of dynamically changing the operating voltage level in response to changing PVT conditions.

Disclosure of Invention

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to the memory device through the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device at the second voltage level through the same interface, i.e., the host interface or the memory interface, to determine a first read value. The controller then changes the second voltage to a third voltage based on determining whether the first read value is equal to the first write value to dynamically change an operating voltage level of the memory device in response to changing the PVT condition.

In one embodiment, a method for monitoring voltage effects of a read operation of a memory device includes initializing a system of the memory device with a first voltage level. The storage device includes a controller and one or more memory devices, and the controller includes a host interface and a memory interface. The method further includes writing, with the controller, a first data test to a first memory device of the one or more memory devices at a second voltage level through the host interface to determine a write value of the controller, and reading, with the controller, the first data test at a third voltage level through the host interface to determine a read value. The third voltage level is lower than the second voltage level. The method comprises the following steps: determining whether the read value is equal to the write value; determining if the third voltage level is the same as a predetermined minimum voltage level of the host interface when the read value is equal to the write value; and reducing the third voltage level to a fourth voltage level supplied to the system when the third voltage level is not the same as the predetermined minimum voltage level to dynamically change an operating voltage level of the memory device in response to changing the PVT condition.

In another embodiment, a method for monitoring voltage effects of a write operation of a memory device includes initializing a system of the memory device with a first voltage level. The storage device includes a controller and one or more memory devices, and the controller includes a memory interface and a host interface. The method further includes writing, with the controller, a first data test to a first memory device of the one or more memory devices at a second voltage level through the memory interface to determine a write value, and reading, with the controller, the first data test at a third voltage level through the memory interface to determine a read value. The third voltage level is higher than the second voltage level. The method comprises the following steps: determining whether the read value is equal to the write value; and increasing the third voltage level to a fourth voltage level supplied to the system when the read value is not equal to the write value to dynamically change the operating voltage level of the memory device in response to changing the PVT condition.

In yet another embodiment, a data storage device includes one or more memory devices and a controller having a first interface and a second interface. The controller is configured to write a first data test to a first memory device of the one or more memory devices at a first voltage level through a first interface of the controller to determine a first write value. The controller is further configured to read a first data test written to the first memory device through the first interface at a second voltage level to determine a first read value. The controller is further configured to change the second voltage to a third voltage based on determining whether the first read value is equal to the first write value to dynamically change an operating voltage level of the memory device in response to changing the PVT condition.

In another embodiment, a data storage device includes: one or more memory devices; means for writing a first data test to a first memory device of the one or more memory devices at a first voltage level through a first interface to determine a first write value; means for reading a first data test written to the first memory device through the first interface at a second voltage level to determine a first read value; and means for comparing the first read value to the first write value and dynamically changing an operating voltage level of the system based on determining whether the first read value is equal to the first write value.

In another embodiment, a data storage system includes a host device and a storage device coupled to the host device. The storage device includes a controller having a host interface coupled to the host device and a memory interface coupled to one or more memory devices. The controller is configured to write a first data test to a first memory device of the one or more memory devices through the host interface at a first voltage level to determine a write value, and is configured to read the first data test written to the first memory device through the host interface at a second voltage level to determine a read value. The controller is further configured to compare the read value to the write value and is further configured to dynamically change an operating voltage level of the system based on determining whether the read value is equal to the write value.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, for other equally effective embodiments may admit to other equally effective embodiments.

FIG. 1 is a block diagram of an illustrative example of a data storage system, according to one embodiment.

FIG. 2 is a block diagram of an illustrative example of a storage module including multiple data storage systems that may each contain a controller, according to another embodiment.

FIG. 3 is a block diagram of an illustrative example of a hierarchical data storage system including multiple controllers in accordance with another embodiment.

Fig. 4 is a block diagram illustrating an example of a controller according to one embodiment.

FIG. 5 is a block diagram illustrating exemplary components of a nonvolatile memory die that may be coupled to a controller according to one embodiment.

FIG. 6 is a block diagram of a particular illustrative example of a data storage system including a data storage device, according to one embodiment.

FIGS. 7A-7B illustrate a method for monitoring voltage effects of read and write operations of a memory system, according to one embodiment

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Specific examples in accordance with the disclosure are described below with reference to the drawings. In the specification, common features are denoted by common reference numerals. As used herein, "exemplary" may refer to examples, implementations, and/or aspects, and should not be construed as limiting or indicating a preference or preferred implementation. Moreover, it should be appreciated that particular ordinal terms such as "first" or "second" may be provided for identification and ease of reference, without necessarily implying any physical characteristics or order. Thus, as used herein, ordinal terms such as "first," "second," "third," etc., used to modify an element such as a structure, component, operation, etc., do not necessarily indicate a priority or order of the element relative to another element, but merely distinguish between the element and another element having the same name (but different ordinal terms used). In addition, as used herein, the indefinite articles "a" and "an" may indicate "one or more" than "one". As used herein, a structure or operation that "comprises" or "includes" an element may include one or more other elements not explicitly recited. Furthermore, operations performed "based on" conditions or circumstances may also be performed based on one or more other conditions or circumstances that are not explicitly recited.

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device at a first voltage level through the host interface or the memory interface to determine a first write value. The controller reads the first data test written to the memory device at a second voltage level through the same interface, either the host interface or the memory interface, to determine a first read value. The controller then changes the second voltage to a third voltage based on determining whether the first read value is equal to the first write value to dynamically change an operating voltage level of the storage device in response to changing PVT conditions.

Memory systems suitable for implementing aspects of the present disclosure are shown in fig. 1-3. FIG. 1 is a block diagram illustrating a data storage system 100 according to an example of the subject matter described herein. Referring to FIG. 1, a data storage system 100 includes a controller 102 and non-volatile memory, which may be comprised of one or more non-volatile memory dies 104. As used herein, the term "memory die" refers to a collection of non-volatile memory cells formed on a single semiconductor substrate, and associated circuitry for managing the physical operation of those non-volatile memory cells. The controller 102 interfaces with the host system and transmits command sequences for read, program, and erase operations to the nonvolatile memory die 104.

The controller 102 (which may be a flash memory storage controller) may be in the form of a processing circuit, a microprocessor or processor, and a computer readable medium storing computer readable program code (e.g., firmware) executable by: such as (micro) processors, logic gates, switches, application specific integrated circuits (application specific integrated circuit, ASIC), programmable logic controllers and embedded microcontrollers. The controller 102 may be configured with hardware and/or firmware to perform the various functions shown in the following description and flowcharts. Also, some components shown as being internal to the controller may also be stored external to the controller, and other components may be used. Further, the phrase "operatively communicates" may mean direct communication or indirect (wired or wireless) communication via one or more components that may or may not be shown or described herein.

As used herein, a flash memory storage controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. In addition to the specific functionality described herein, the flash memory storage controller may also have various functionalities. For example, the flash memory controller may format the flash memory, find bad flash memory cells, and allocate spare cells to replace future failed cells. Some portion of the spare unit may be used to hold firmware to operate the flash memory controller and implement other features. In operation, the host communicates with the flash memory storage controller when the host is used to read data from or write data to the flash memory. If the host provides a logical address to which data is to be read/written, the flash memory storage controller may translate the logical address received from the host into a physical address in the flash memory. Alternatively, the host may provide a physical address. The flash memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing specific memory blocks that would otherwise be written repeatedly) and garbage collection (after a block is full, only valid data pages are moved to a new block so that the full block can be erased and reused).

The non-volatile memory die 104 may include any suitable non-volatile memory medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells may be in the form of solid state (e.g., flash) memory cells, and may be one-time programmable, less-time programmable, or more-time programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), or use other now known or later developed memory cell level technologies. Also, the memory cell may be fabricated in two or three dimensions.

The interface between the controller 102 and the nonvolatile memory die 104 may be any suitable flash interface, such as a Toggle Mode 200, 400, or 800. In one embodiment, data storage system 100 may be a card-based system, such as a Secure Digital (SD) or micro-secure digital (micro secure digital, micro-SD) card. In alternative embodiments, the data storage system 100 may be part of an embedded memory system.

Although in the example shown in fig. 1, the data storage system 100 includes a single channel between the controller 102 and the nonvolatile memory die 104, the subject matter described herein is not limited to having a single memory channel. For example, in some NAND memory system architectures (such as those shown in fig. 2 and 3), there may be 2, 4, 8, or more NAND channels between the controller and the NAND memory device, depending on the controller capability. In any of the embodiments described herein, there may be more than a single channel between the controller 102 and the nonvolatile memory die 104, even though a single channel is shown in the figures.

Fig. 2 illustrates a memory module 200 containing a plurality of data storage systems 100. Accordingly, the storage module 200 may include a controller 202 that interfaces with a host and with a storage system 204, the storage system 204 including a plurality of data storage systems 100. The interface between the controller 202 and the data storage system 100 may be a bus interface, such as a serial advanced technology attachment (serial advanced technology attachment, SATA) or a peripheral component interface express (peripheral component interface express, PCIe) interface. In one embodiment, the storage module 200 may be a solid state drive (solid state drive, SSD) as seen in, for example, a portable computing device such as a laptop computer and a tablet computer.

Fig. 3 is a block diagram illustrating a hierarchical storage system 300. The hierarchical storage system 300 includes a plurality of controllers 304, each of the plurality of controllers 304 controlling a respective storage system 306. The controller 304 may access memory within the hierarchical storage system 300 via a bus interface. In one embodiment, the bus interface may be an NVMe or fibre channel over ethernet (fiber channel over Ethernet, FCoE) interface. In one embodiment, the hierarchical storage system 300 illustrated in FIG. 3 may be a rack-mountable mass storage system accessible by a plurality of host computers 302, such as hosts that can be found in a data center or other location requiring mass storage.

Fig. 4 is a block diagram illustrating exemplary components of controller 102 in more detail. The controller 102 includes a front-end module 408 that interfaces with the host, a back-end module 410 that interfaces with one or more nonvolatile memory die 104, and various other modules that perform other functions. The modules may, for example, take the form: a packaged-function hardware unit designed for use with other components, a portion of program code (e.g., software or firmware) executable by a (micro) processor or processing circuit that typically performs the specific function of the relevant function, or a self-contained hardware or software component that interfaces with a larger system.

Referring again to the modules of the controller 102, the buffer manager/bus controller 414 manages buffers in the random access memory (random access memory, RAM) 416 and controls internal bus arbitration of the controller 102. A Read Only Memory (ROM) 418 stores the system boot code. Although shown in fig. 4 as being located within controller 102, in other embodiments, one or both of RAM 416 and ROM 418 may be located external to controller 102. In still other embodiments, portions of the RAM and ROM may be located both within the controller 102 and external to the controller 102.

The front end module 408 includes a host interface 420 and a physical layer interface (physical layer interface, PHY) 422 that provide electrical interface with a host or next level controller. The choice of the type of host interface 420 may depend on the type of memory being used. Examples of host interface 420 include, but are not limited to, SATA express, SAS, fibre channel, USB, PCIe, and NVMe. The host interface 120 generally facilitates the transfer of data, control signals, and timing signals.

The back-end module 410 includes an error correction code (error correction code, ECC) engine 424 that encodes data received from the host and decodes and error corrects data read from the non-volatile memory. The command sequencer 426 generates command sequences, such as program and erase command sequences, to be transferred to the nonvolatile memory die 104. A redundant array of independent drives (Redundant Array of Independent Drive, RAID) module 428 manages the generation of RAID parity and the recovery of failure data. RAID parity may be used as an additional level of integrity protection for writing data into the nonvolatile memory die 104. In some cases, RAID module 428 may be part of ECC engine 424. The memory interface 430 provides command sequences to the nonvolatile memory die 104 and receives status information from the nonvolatile memory die 104. For example, the memory interface 430 may be a Double Data Rate (DDR) interface, such as a switch mode 200, 400, or 800 interface. The flash control layer 432 controls the overall operation of the back-end module 410.

Additional components of the data storage system 100 shown in fig. 4 include a power management module 412 and a media management layer 438, the media management layer 438 performing wear leveling of memory cells of the nonvolatile memory die 104. The data storage system 100 also includes other discrete components 440, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller 102. In alternative embodiments, one or more of physical layer interface 422, RAID module 128, media management layer 138, and buffer management/bus controller 114 are optional components omitted from controller 102.

Fig. 5 is a block diagram illustrating exemplary components of the nonvolatile memory die 104 in more detail. The nonvolatile memory die 104 includes peripheral circuitry 541 and a nonvolatile memory array 542. The nonvolatile memory array 542 includes nonvolatile memory cells for storing data. The nonvolatile memory cells may be any suitable nonvolatile memory cells, including NAND flash memory cells and/or NOR flash memory cells in two-dimensional and/or three-dimensional configurations. Peripheral circuitry 541 includes a state machine 552 that provides state information to controller 102. Peripheral circuitry 541 also includes a power management or data latch control module 554. The nonvolatile memory die 104 further includes discrete components 540, an address decoder 548, an address decoder 550, and a data cache 556 that caches data.

FIG. 6 depicts an illustrative example of a data storage system 600. The data storage system 600 includes a data storage device 602 (e.g., the data storage system 100) and a host device 670 (e.g., the host 302).

The data storage 602 includes a memory device, such as memory device 603. The memory device 603 may include one or more memory dies (e.g., one memory die, two memory dies, eight memory dies, or another number of memory dies). By way of further illustration, the memory device 603 may include a non-volatile memory die 104. The memory device 603 includes memory 604, such as non-volatile memory of storage elements included in a memory die of the memory device 603. For example, as an illustrative example, memory 604 may include: flash memory, such as NAND flash memory; or resistive memory, such as resistive random access memory (resistive random access memory, reRAM). The memory 604 may have a three-dimensional (3D) memory configuration. As an example, the memory 604 may have a 3D vertical bit line (vertical bit line, VBL) configuration. In a particular implementation, the memory 604 is a non-volatile memory having a 3D memory configuration that is integrally formed in one or more physical levels of a memory cell array having an active area disposed over a silicon substrate. Alternatively, the memory 604 may have another configuration, such as a two-dimensional (2D) memory configuration or a non-monolithic 3D memory configuration (e.g., a stacked-die 3D memory configuration).

Memory 604 may include one or more regions of storage elements (also referred to herein as memory cells), such as memory region 608. One example of a memory region is a block, such as a NAND flash erase memory element group. Another example of a memory region 608 is a word line of a memory element. The word lines may function as Single Level Cell (SLC) word lines or as multi-level cell (MLC) word lines (e.g., three bit word lines per cell or two bit word lines per cell, as illustrative examples). Each memory element of memory 604 may be programmed to indicate a state of one or more bit values (e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration).

The memory device 603 further includes read/write circuitry 610. Read/write circuitry 610 is configured to program values into storage elements of memory 604 and to sense values from memory elements of memory 604. The memory device 603 may further include circuitry 616 (e.g., one or more data latches, one or more control latches, or a combination thereof).

The data storage 602 further includes a controller 630, such as the controller 102 of fig. 1 and 4. The controller 630 includes a first interface 638 (e.g., a host interface), an Error Correction Code (ECC) engine 634, a timing device 636, a second interface 632 (e.g., a memory interface), and one or more voltage regulators 642. For example, ECC engine 634 may correspond to ECC engine 424, first interface 638 may correspond to host interface 420, and second interface 632 may correspond to memory interface 430. By way of further illustration, the first interface 638 may include one or more latches to receive data and commands from the host device 670, and the second interface 632 may include one or more bus drivers to send data and commands to the circuitry 616 of the memory device 603. The controller 630 may store (or access) a file table 640, such as a file allocation table (file allocation table, FAT).

Host device 670 includes circuitry 672. For example, circuitry 672 may include one or more bus drivers. The circuitry 672 may be integrated within a processor or controller of the host device 670 or coupled to a processor or controller of the host device 670, such as within a host processing device 674 (e.g., an application processor).

The data storage device 602 and the host processing device 674 are coupled via a connection 650 (e.g., a bus). For example, fig. 6 shows that the connection 650 includes one or more data lines 651 and one or more control lines 652. The connection 650 is coupled to the first interface 638 and to circuitry 672. In some implementations, the connection 650 may include or may be coupled to the physical layer interface 422 of fig. 4.

The memory device 603 and the controller 630 are coupled via a connection 620 (e.g., a bus). For example, fig. 6 shows that the connection 620 may include one or more data lines 621, one or more control lines 622. The connection 620 is coupled to the circuitry 616 and to the second interface 632.

In an illustrative implementation, the data storage system 600 further includes a power supply connection 673 (e.g., a "rail" that is used to provide a supply voltage, such as VDD, VCC, or both). The power connection 673 may be coupled to the memory device 603, the controller 630, and the host processing device 674. Depending on the particular implementation, the power connection 673 may be supplied by a battery (e.g., a mobile device battery) or by a power device (e.g., a transformer) coupled to a primary power source. In other implementations, the memory device 603, the controller 630, and/or the host processing device 674 are connected to separate power connections.

During operation, controller 630 is configured to receive data and instructions from host device 670 using first interface 638. For example, the controller 630 may receive the data 660 from the host device 670 via the first interface 638. By way of further illustration, data 660 may be received via one or more data lines 651 in connection with a write access request sent via one or more control lines 652. The controller 630 may also be configured to receive instructions or messages 662 from the host device 670 via one or more control lines 652.

The ECC engine 634 may be configured to receive the data 660 and to generate one or more ECC codewords based on the data 660. ECC engine 634 may include a Hamming (Hamming) encoder, a Reed-Solomon (RS) encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity-density parity check (LDPC) encoder, a turbo code encoder, an encoder configured to encode data according to one or more other ECC schemes, or a combination thereof.

The controller 630 is configured to send data and commands to the memory device 603 using the second interface 632 and to receive data from the memory device 603 using the second interface 632. For example, the controller 630 is configured to send data (e.g., one or more ECC codewords generated by the ECC engine 634) and write commands (e.g., command 624) to cause the memory device 603 to store the data to specified addresses of the memory 604. The write command may specify a physical address of the memory 604 to store a portion of the data. As further illustrated, the controller 630 may send data to the memory device 603 via one or more data lines 621 in connection with write commands sent via one or more control lines 622. After the memory device 603 writes data in response to the received command, a write value for the controller 630 may be determined.

In one embodiment, in response to receiving message 662, controller 630 may use connection 620 to cause second interface 632 to send data 606 and a write command (e.g., command 624) to circuitry 616. The write command may specify one or more physical addresses of the memory 604, such as physical addresses of the memory region 608. After receiving the data 606 at circuitry 616, the memory device 603 may cause the read/write circuitry 610 to program the data 606 to the memory 604. In response to programming the data 606 to the memory 604, the memory device 603 may send a status indication indicating the status of the write operation (e.g., a pass or fail status) and a write value to the controller 630.

The controller 630 is configured to send read commands (e.g., command 624) to the memory device 603 to access data from specified addresses of the memory 604. For example, the controller 630 may send a read command to the memory device 603 in response to receiving a read access request from the host device 670. The read command may specify a physical address of a portion of the memory 604. For example, a read command may specify a physical address of a portion of the memory 604 that stores data. In response to the read command, the memory device 603 may cause the read/write circuitry 610 to sense portions of the memory 604 storing data to generate sensed data 628 (e.g., a representation of the data that may be different relative to the data due to one or more bit errors). In addition, the read value of the controller 630 may be determined after the controller 630 sends a read command to the memory device 603.

For example, the controller 630 may send a read command (e.g., command 624) to the memory device 603 using the connection 620. The read command may specify a physical address of the memory region 608. The memory device 603 may cause the read/write circuitry 610 to sense the memory region 608 to generate sense data 628. The memory device 603 may provide the sense data 628 to the controller 630 using the connection 620, and the controller 630 may receive the sense data 628 using the second interface 632.

The controller 630 is configured to receive the sense data 628 from the memory device 603 via the second interface 632. The controller 630 may input the sensed data 628 to the ECC engine 634 to initiate a decoding process to correct one or more bits (if any) in the sensed data within a particular error correction capability of a particular ECC technique. In response to decoding the sensed data 628, the ecc engine 634 may output the data 660. The controller 630 may provide the data 660 to the host device 670 using the first interface 638.

The controller 630 is further configured to monitor the voltage effects of the data storage device 602 during read and write operations, which allows the controller 630 to monitor the speed, operating temperature, and power usage of the data storage device 602. The controller 630 monitors the voltage impact through the first interface 638 (or the host interface) to monitor the voltage impact of the read operation of the data storage 602 (i.e., check the voltage impact from the controller 630). The controller 630 also monitors the voltage impact through the second interface 632 (or the memory interface) to monitor the voltage impact of the write operation (i.e., check the voltage impact from the memory device 603). In response to monitoring the voltage across the host interface and the memory interface, the controller 630 changes the operating voltage level during operation of the data storage device 602 to reduce power consumption. Accordingly, the operating voltage level of the memory device 602 is adjusted in real time to meet the current requirements of the memory system 600.

To monitor the voltage impact of a read operation through the host interface 638, the controller 630 may write a data test to the memory device 603 at a high host interface voltage level to determine a write value. The controller 630 may then read the data test from the memory device 603 at a low host interface voltage level to determine the read value. The controller 630 may then compare the written value to the read value to see if the written value and the read value are the same.

To monitor the voltage impact of a write operation through the memory interface 632, the controller 630 may write a data test to the memory device 603 at a low memory interface voltage level to determine a write value. The controller 630 may then read the data test from the memory device 603 at a high memory interface voltage level to determine the read value. The controller 630 may then compare the written value to the read value to see if the written value and the read value are the same.

The controller 630 is further configured to change the operating voltage level of the data storage device 602 in response to comparing the written value to the read value. In one embodiment, the voltage regulator 642 of the controller 630 is configured to change the operating voltage level of the data storage 602. A write value of the controller 630 equal to the read value may indicate that the data storage device 602 currently has a satisfactory setup/save margin, and that the data storage device 602 is currently operating at an optimal operating voltage level. Thus, a read value equal to a write value may indicate that the power consumption of data storage system 600 has been optimized.

Even if the controller 630 determines that the read value is equal to the write value, the controller 630 may determine that the operating voltage level is not optimized. In one embodiment, controller 630 is configured to compare the operating voltage level of data storage device 602 to a predetermined minimum voltage level. If the operating voltage level is not equal to the predetermined minimum voltage level, then controller 630 may change the operating voltage level to optimize the power consumption of data storage system 600.

A write value not equal to a read value may indicate a risk of violating the set/save, and a set/save margin is not satisfactory. The write value not being equal to the read value may result in excessive power being generated, causing the data storage system 600 to unnecessarily waste heat. Thus, if the write value is not equal to the read value, the controller 630 may change the operating voltage level of the data storage device 602 to minimize power consumption. By utilizing one of the storage device vendor specific function lines implemented for both upper and lower level operations, the operating voltage level optimization or minimization can be accomplished "on the fly" using an interrupt mechanism or timer trigger. By changing the operating voltage level of the data storage device 602 "on the fly," the power consumption of the data storage device 602 may be reduced to avoid generating excessive power and heat.

Fig. 7A-7B illustrate a method 700 and a method 750, respectively, for monitoring voltage effects of read and write operations of a memory system, according to one embodiment. The storage system may be data storage system 100 of FIG. 1, data storage system 300 of FIG. 3, or data storage system 600 of FIG. 6. The data storage system may include a host device and a storage device, such as data storage device 602 and host device 670 of fig. 6. The storage devices may include a controller and one or more memory devices, such as controller 630 and memory device 603 of fig. 6, or controller 102 of fig. 1 and 4. The controller may include a host interface and a memory interface, such as host interface 638 and memory interface 632 of fig. 6, or host interface 420 and memory interface 430 of fig. 4.

Fig. 7A shows a flowchart of a method 700, the method 700 monitoring the voltage impact of a read operation to determine if the controller is operating at an optimal operating voltage level for the host interface operating frequency. Fig. 7B shows a flowchart of a method 750, the method 750 monitoring the voltage impact of a write operation to determine if the controller is operating at an optimal operating voltage level for the memory interface operating frequency. Operations 702, 704, 710, 712, 714, 716, 718, 720, and 722 of method 700 and 750 are the same.

In operation 702, a system of a memory device is initialized with a first voltage level. The first voltage level may be a nominal voltage level. In operation 704, the system is caused to monitor voltage effects using a timer trigger during a defined interval time or using an interrupt mechanism during an idle time associated with the data storage device (e.g., when the host device does not request a read access or a write access). If the system of storage devices is already in operation, method 700 and method 750 may begin at operation 704.

In operation 706 of method 700, the controller writes a data test to the first memory device at a second voltage level through the host interface to determine a write value of the controller. The second voltage level may be higher than the first voltage level. In operation 706 of method 700, the controller may write to the memory at an approved high voltage level. In operation 708 of the method 700, the controller reads the data test at a third voltage level through the host interface to determine a read value of the controller. In method 700, the third voltage level may be lower than the second voltage level. In one embodiment of method 700, the second voltage level is an upper limit of the operating voltage level and the third voltage is a lower limit of the operating voltage level.

In operation 752 of method 750, the controller writes a data test to the first memory device at the second voltage level through the memory interface to determine a write value of the controller. The second voltage level may be higher than the first voltage level. In operation 754 of method 750, the controller reads the data test at a third voltage level through the memory interface to determine a read value of the controller. In method 750, the third voltage level may be higher than the second voltage level. In one embodiment of the method 750, the second voltage level is a lower limit of the operating voltage level and the third voltage is an upper limit of the operating voltage level. Thus, in operation 754 of method 750, the controller may read from memory at an approved high voltage level.

In operation 710 of both method 700 and method 750, the controller determines whether the read value is equal to the write value. If the read value is equal to the write value, then method 700 and method 750 continue to operation 712. If the read value is not equal to the write value, then method 700 and method 750 continue to operation 722. A read value not equal to the write value indicates a risk of violating the set/save, and the set/save margin is not satisfactory. Thus, in operation 722, the controller increases the third voltage level to the fourth voltage level to reduce the risk of violating the set/save.

In operation 712 of both method 700 and method 750, if the controller determines that the read value is equal to the write value, the controller then determines whether the third voltage level is the same as the predetermined minimum voltage level. In one embodiment, the predetermined minimum voltage level is based on the set-up and hold time required for a read operation or a write operation. The predetermined minimum voltage level may be based on at least one of an operating voltage, a change in operating temperature, or a loading of the host interface or the memory interface. The predetermined minimum voltage level may include: a minimum host interface voltage level at which the system can operate during a read operation while maintaining a satisfactory setup/save margin; and a minimum memory interface voltage level at which the system can operate during a write operation while still maintaining a satisfactory setup/save margin.

The controller determines in operation 712 that the third voltage level is the same as the predetermined minimum voltage level may indicate that the system is operating at optimal power consumption and that the operating voltage level is not necessarily changed. If the controller makes this determination, then the corresponding method (method 700 or method 750) repeats one or more times from operation 704 to ensure that the third voltage level maintains the optimal operating voltage level of the system in response to changing the PVT conditions. In one embodiment, method 700 and method 750 may be used interchangeably in operation. For example, once method 700 completes operation 712, the system will begin method 750 instead of restarting method 700.

If, in operation 712, the controller determines that the third voltage level is not the same as the predetermined minimum voltage level, then the method 700 and the method 750 each proceed to operation 714. In operation 714, the controller reads the data test using the fifth voltage level (instead of the third voltage level) to temporarily lower the third voltage level to the fifth voltage level and loops a predetermined number of times from operation 704 through the corresponding method (method 700 or method 750). Operation 714 tests and determines if the fifth voltage level is a stable operating voltage level for the operating system. The controller counts each successful period in which the fifth voltage level is determined to be the stable operating voltage level and determines a stable voltage count. When the regulated voltage count reaches a predetermined threshold, the methods 700 and 750 continue to operation 716.

In operation 716, if the regulated voltage count reaches a predetermined threshold, the controller remains lowered to a fifth voltage level such that the fifth voltage level becomes the most recently optimized operating voltage level of the memory device. In one embodiment, the fifth voltage level may be equal to or greater than the predetermined minimum voltage level. Thus, the operating voltage level of the host interface or the memory interface is dynamically reduced after the fifth voltage level is determined to be the stable operating voltage level. Thus, in response to altering the PVT conditions, the operating voltage level is adjusted "on the fly" or in real time during operation. The operating voltage level varies as PVT conditions change during system operation, thereby reducing and optimizing power consumption.

Once the operating voltage level is set equal to the fifth operating voltage level in operation 716, the regulated voltage count is reset and cleared from the controller in operation 718. Additionally, once the third voltage level is increased to the fourth voltage level in operation 722, the method 700 and method 750 proceed to operation 718 and reset the regulated voltage count. Then, since the PVT conditions may be continuously altered, the method 700 may again begin at operation 704 to monitor the voltage effects of the read operation of the system, or the method 750 may begin. Similarly, method 750 may again begin at operation 704 to monitor the voltage impact of a write operation of the system, or method 700 may begin. By repeating method 700 and method 750, the operating voltage level may be gradually reduced to a lower limit, or reduced to slightly above the failure voltage level. The disabling voltage level may be a first voltage level that results in a violation of a setup/save or rendering the system inoperable. The failure voltage level may be less than a predetermined minimum voltage level. The failure voltage level is dynamic and may change as PVT conditions change.

During operation 714, if the regulated voltage count fails to reach the predetermined threshold, then method 700 and method 750 alternatively continue to operation 720. Failure of the regulated voltage count to meet the predetermined threshold may indicate that the fifth voltage level is unstable and, therefore, too low to serve as an operating voltage level for the system. Failure of the regulated voltage count to meet the predetermined threshold may indicate that the fifth voltage level is equal to or less than the failed voltage level, and may indicate a risk of violating the set/save. Accordingly, in operation 720, the fifth voltage level increases. In one embodiment, the fifth voltage level increases back to the third voltage level. In another embodiment, the fifth voltage level may be increased to a sixth voltage level. The sixth voltage level may be less than the third voltage level but greater than the predetermined minimum voltage level.

Increasing the fifth voltage level allows the device to continue writing and reading operations in the event that PVT conditions are poor. After operation 720, method 700 may again restart from operation 704 to monitor the voltage impact of a read operation of the system, or method 750 may again restart from operation 704 to monitor the voltage impact of a write operation of the system. By restarting either method 700 or method 750, the operating voltage level of the system can be updated and adjusted based on changing the PVT conditions of the system. Thus, if the bad PVT conditions of the memory device improve, the operating voltage level of the memory device can be reduced and optimized directly in response. Instead of maintaining a higher voltage level, the storage device may monitor the voltage effects and again reduce the operating voltage level as PVT conditions improve to save power and prevent wasting heat. Continuously monitoring the voltage effects allows the operating voltage level to be adapted in real time to meet the current requirements of the memory system.

In one embodiment, method 700 and method 750 are used interchangeably in operation. For example, once method 700 completes operation 712, operation 718, or operation 720, the system will begin method 750 instead of restarting method 700. Once method 750 completes operation 712, operation 718, or operation 720, the system may then restart operation 700. Thus, the system may alternate between writing and reading data tests through the host interface and writing and reading data tests through the memory interface to continuously monitor voltage effects during read and write operations. In one embodiment, the system constantly alternates between method 700 and method 750 to monitor the voltage interface while the device is still operating.

By monitoring the voltage effects of read and write operations of the memory system, the operating voltage level of the system is dynamically changed "on the fly" in direct response to changing PVT conditions. Where feasible, the system is able to save power by operating at reduced voltage levels, thereby reducing overall power consumption and preventing waste of heat. In addition, monitoring the voltage effects at the host interface and at the memory interface allows monitoring of device speed, operating temperature, and power usage.

By varying the operating voltage in real time during operation, the system is tuned to operate continuously at optimal power consumption and improves the performance of the memory device at maximum system frequency. Continuously monitoring the voltage effects allows the operating voltage level to be adapted in real time to meet the current requirements of the memory system. In addition, monitoring the voltage effects and in response dynamically changing the operating voltage level also results in increased battery life and battery power for storage devices that utilize battery operation (e.g., mobile platforms) because the storage devices no longer generate wasted heat, resulting in unnecessary heating of the device.

The writing of the first data test may be performed during a defined interval time frame. A read value equal to a write value may indicate that the system may operate at a fourth voltage level that is lower than the second voltage level. The fourth voltage level may be equal to or greater than the predetermined minimum voltage level. The method may further include increasing the third voltage level to a fifth voltage level supplied to the system when the read value is not equal to the write value. The fifth voltage may be a changed operating voltage of the system. The fifth voltage level may be equal to or greater than the predetermined minimum voltage level. The third voltage level may remain unchanged when the third voltage is the same as the predetermined minimum voltage level.

The method may further comprise repeating the operations of: writing, with the controller, a first data test to a first memory device of the one or more memory devices at a second voltage level through the host interface to determine a write value of the controller; reading, by the controller, the first data test at a third voltage level through the host interface to determine a read value, wherein the third voltage level is lower than the second voltage level; determining whether the read value is equal to the write value; determining if the third voltage level is the same as a predetermined minimum voltage level of the system when the read value is equal to the write value; and reducing the third voltage level to a fourth voltage level supplied to the system to gradually reduce the fourth voltage level when the third voltage level is not the same as the predetermined minimum voltage level of the host interface.

The writing of the first data test may be performed during an idle interrupt of the system. A read value that is not equal to a write value may indicate that there is a risk of violating the system's setup/save. The fourth voltage level may be a changed operating voltage level. The first voltage level may be a nominal voltage level. The method may further include reducing the third voltage level to a fifth voltage level supplied to the system when the read value is equal to the write value.

The third voltage level may be lower than the second voltage level when the controller determines that the first read value is equal to the first write value. The third voltage level may be higher than the second voltage when the controller determines that the first read value is not equal to the first write value. The first interface may be a host interface and the second interface may be a memory interface, and the first voltage level may be higher than the second voltage level. The controller may be further configured to: writing a second data test to the first memory device through the second interface at a fifth voltage level to determine a second write value; reading a second data test written to the first memory device through the second interface at a sixth voltage level to determine a second read value; and changing the sixth voltage to a seventh voltage based on determining whether the second read value is equal to the second write value, wherein the seventh voltage is a changed operating voltage, and wherein the first interface may be a host interface and the second interface may be a memory interface. The controller may be further configured to alternately write and read the first data test through the first interface and write and read the second data test through the second interface.

In another embodiment, a data storage device includes: one or more memory devices; means for writing a first data test to a first memory device of the one or more memory devices at a first voltage level through a first interface to determine a first write value; means for reading a first data test written to the first memory device through the first interface at a second voltage level to determine a first read value; and means for comparing the first read value to the first write value and dynamically changing an operating voltage level of the system based on determining whether the first read value is equal to the first write value. The changed operating voltage level may be equal to or greater than a predetermined minimum voltage level of the system.

In another embodiment, a data storage system includes a host device and a storage device coupled to the host device. The storage device includes a controller having a host interface coupled to the host device and a memory interface coupled to one or more memory devices. The controller is configured to write a first data test to a first memory device of the one or more memory devices through the host interface at a first voltage level to determine a write value, and is configured to read the first data test written to the first memory device through the host interface at a second voltage level to determine a read value. The controller is further configured to compare the read value to the write value and is further configured to dynamically change an operating voltage level of the system based on determining whether the read value is equal to the write value. The operating voltage level may be lower than the first voltage level.

The above-described methods for improved operation of a data storage device are provided. In particular, the method allows for "on the fly" dynamic changes in the operating voltage level of the memory device in response to changing PVT conditions by monitoring the voltage effects of read and write operations. Dynamically changing the operating voltage level of the memory device in real time can reduce and optimize power consumption so that heat is not wasted and battery life is increased.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method for monitoring voltage effects of a read operation of a memory device, comprising:

a system for initializing the storage device with a first voltage level, wherein the storage device comprises a controller and one or more memory devices, and wherein the controller comprises a host interface and a memory interface;

writing, with the controller, a first data test to a first memory device of the one or more memory devices at a second voltage level through the host interface, wherein the second voltage level is a write value of the controller;

Reading, by the controller, the first data test at a third voltage level through the host interface, wherein the third voltage level is a read value, and wherein the third voltage level is lower than the second voltage level;

determining whether the read value is equal to the write value;

determining if the third voltage level is the same as a predetermined minimum voltage level of the host interface when the read value is equal to the write value; and

reducing the third voltage level to a fourth voltage level supplied to the system when the third voltage level is not the same as the predetermined minimum voltage level to dynamically change an operating voltage level of the memory device in response to changing process, voltage, and temperature conditions.

2. The method of claim 1, wherein writing the first data test occurs during a defined interval time frame.

3. The method of claim 1, wherein the read value being equal to the write value indicates that the system is capable of operating at the fourth voltage level, the fourth voltage level being lower than the second voltage level.

4. A method according to claim 3, further comprising:

The following operations were repeated:

writing, with the controller, the first data test to the first one of the one or more memory devices at the second voltage level through the host interface, wherein the second voltage level is the write value of the controller;

reading, by the controller, the first data test at the third voltage level through the host interface, wherein the third voltage level is the read value, and wherein the third voltage level is lower than the second voltage level;

determining whether the read value is equal to the write value;

determining if the third voltage level is the same as a predetermined minimum voltage level of the system when the read value is equal to the write value; and

reducing the third voltage level to a fourth voltage level supplied to the system to gradually reduce the fourth voltage level when the third voltage level is not the same as the predetermined minimum voltage level of the host interface.

5. The method of claim 4, wherein the fourth voltage level is equal to or greater than the predetermined minimum voltage level.

6. The method as recited in claim 1, further comprising: the third voltage level is increased to a fifth voltage level supplied to the system when the read value is not equal to the write value.

7. The method of claim 6, wherein the fifth voltage level is a changed operating voltage level of the system.

8. The method of claim 7, wherein the fifth voltage level is equal to or greater than the predetermined minimum voltage level.

9. The method of claim 1, wherein the third voltage level remains unchanged when the third voltage level is the same as the predetermined minimum voltage level.

10. A method for monitoring voltage effects of a write operation of a memory device, comprising:

a system for initializing the storage device with a first voltage level, wherein the storage device comprises a controller and one or more memory devices, and wherein the controller comprises a memory interface and a host interface;

writing, with the controller, a first data test to a first memory device of the one or more memory devices at a second voltage level through the memory interface, wherein the second voltage level is a write value;

Reading, with the controller, the first data test at a third voltage level through the memory interface, wherein the third voltage level is a read value, and wherein the third voltage level is higher than the second voltage level;

determining whether the read value is equal to the write value; and

the third voltage level is increased to a fourth voltage level supplied to the system when the read value is not equal to the write value to dynamically change an operating voltage level of the memory device in response to changing process, voltage, and temperature conditions.

11. The method of claim 10, wherein writing the first data test occurs during an idle interrupt of the system.

12. The method of claim 10, wherein the read value not being equal to the write value indicates that there is a risk of violating a setup/save of the system.

13. The method of claim 10, wherein the fourth voltage level is a changed operating voltage level.

14. The method of claim 10, wherein the first voltage level is a nominal voltage level.

15. The method as recited in claim 10, further comprising: the third voltage level is reduced to a fifth voltage level supplied to the system when the read value is equal to the write value.

16. A data storage device, comprising:

one or more memory devices; and

a controller having a first interface and a second interface, the controller configured to write a first data test to a first memory device of the one or more memory devices through the first interface of the controller at a first voltage level, wherein the first voltage level is a first write value;

the controller is further configured to read the first data test written to the first memory device through the first interface at a second voltage level, wherein the second voltage level is a first read value; and is also provided with

The controller is further configured to change the second voltage level to a third voltage level based on determining whether the first read value is equal to the first write value to dynamically change an operating voltage level of the memory device in response to changing process, voltage, and temperature conditions.

17. The data storage device of claim 16, wherein the third voltage level is lower than the second voltage level when the controller determines that the first read value is equal to the first write value.

18. The data storage device of claim 16, wherein the third voltage level is higher than the second voltage level when the controller determines that the first read value is not equal to the first write value.

19. The data storage device of claim 16, wherein the first interface is a host interface and the second interface is a memory interface, and wherein the first voltage level is higher than the second voltage level.

20. The data storage device of claim 16, wherein the controller is further configured to: writing a second data test to the first memory device through the second interface at a fifth voltage level, wherein the fifth voltage level is a second write value; reading the second data test written to the first memory device through the second interface at a sixth voltage level, wherein the sixth voltage level is a second read value; and changing the sixth voltage level to a seventh voltage level based on determining whether the second read value is equal to the second write value, wherein the seventh voltage level is a changed operating voltage level.

21. The data storage device of claim 20, wherein the first interface is a host interface and the second interface is a memory interface.

22. The data storage device of claim 20, wherein the fifth voltage level is lower than the sixth voltage level.

23. The data storage device of claim 20, wherein the controller is further configured to alternately write and read the first data test through the first interface and write and read the second data test through the second interface.

24. A data storage system, comprising:

a host device; and

a storage device coupled to the host device, the storage device comprising:

a controller having a host interface coupled to the host device and a memory interface coupled to one or more memory devices, wherein the controller is configured to: writing a first data test to a first memory device of the one or more memory devices through the host interface at a first voltage level, wherein the first voltage level is a write value; and reading, by the host interface, the first data test written to the first memory device at a second voltage level, wherein the second voltage level is a read value, wherein the controller is further configured to compare the read value with the write value and further configured to dynamically change an operating voltage level of the system based on determining whether the read value is equal to the write value.

25. The data storage system of claim 24, wherein the operating voltage level is lower than the first voltage level.