CN111370468A - Super junction device and manufacturing method thereof - Google Patents
Super junction device and manufacturing method thereof Download PDFInfo
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- CN111370468A CN111370468A CN202010326163.4A CN202010326163A CN111370468A CN 111370468 A CN111370468 A CN 111370468A CN 202010326163 A CN202010326163 A CN 202010326163A CN 111370468 A CN111370468 A CN 111370468A
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- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 6
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- 239000012535 impurity Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 238000003780 insertion Methods 0.000 abstract description 5
- 230000037431 insertion Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 25
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- 230000005684 electric field Effects 0.000 description 25
- 238000004088 simulation Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 15
- 239000003086 colorant Substances 0.000 description 8
- 241001270131 Agaricus moelleri Species 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract
The invention discloses a super junction device, comprising: the buffer layer and the first epitaxial layer on the semiconductor substrate and the surface; the P-type column of the super junction is composed of a P-type doped second epitaxial layer filled in the groove; the angle and depth of the side surface of the groove have differences caused by photoetching and etching processes; at least part of the bottom of the groove penetrates into the buffer layer; the doping concentration of the buffer layer is greater than that of the first epitaxial layer and less than that of the semiconductor substrate; the doping concentration of the buffer layer is also satisfied, so that the withstand voltage of the bottom insertion part of each corresponding super junction unit is determined by the doping concentration of the buffer layer, and the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer. The invention also discloses a manufacturing method of the super junction device. The invention can improve the uniformity of the withstand voltage of the super junction unit formed at each position on the wafer, thereby improving the product yield.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers, also called P-type pillars (pilar), and N-type thin layers, also called N-type pillars, formed in a semiconductor substrate, and the device employing the super junction is a super junction device such as a super junction MOSFET. The technology of reducing the surface electric field (Resurf) in a body by utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and simultaneously keep smaller on-resistance.
The PN-spaced Pillar structure of the super junction is the biggest characteristic of the super junction. The conventional method for manufacturing the p-n spaced pilar structure mainly comprises two methods, one is obtained by multiple times of epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxy (EPI) filling. The latter method is to fabricate the super junction device by a trench process, in which a trench with a certain depth and width is first etched on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then a P-type doped silicon epitaxy is filled on the etched trench by an epitaxial Filling (EPI Filling) method.
In the latter method for manufacturing a super junction device by using the trench etching and filling process scheme, due to the characteristics of the etching process, the depth and the angle of the trench have in-plane differences. The depth and angle differences both affect the Breakdown Voltage (BV) of the device, the angle mainly affects the BV in terms of charge matching, and the depth directly affects the breakdown voltage in terms of the thickness of the effective voltage resistance layer. For a general device, the minimum value of the breakdown voltage of the device is only needed to meet the requirement. However, a high-current product has a high requirement on the distribution range of the breakdown voltage values of the device, and both too high and too low breakdown voltages cannot meet the requirement, which can affect the yield of the product to a certain extent. Fig. 1A is a schematic diagram of a super junction in a shallow trench depth region of a conventional super junction device; an N-type epitaxial layer 102 is formed on the surface of an N-type heavily doped semiconductor substrate such as a silicon substrate 101, a trench 103 is formed in the N-type epitaxial layer 102, a P-type epitaxial layer is filled in the trench 103 and forms a P-type column 104 by the P-type epitaxial layer filled in the trench 103, an N-type column is formed by the N-type epitaxial layer 102 between the P-type columns 104, the P-type columns 104 and the N-type columns are alternately arranged to form a super junction, a Buffer layer (Buffer) is formed by the N-type epitaxial layer 102 at the bottom of the super junction, and one P-type column 104 and a corresponding one of the N-type columns form a super junction unit.
FIG. 1B is a schematic diagram of a super junction in a region with a deep trench depth of a conventional super junction device; the super junction shown in fig. 1B and the super junction in fig. 1A are both formed on the same wafer (wafer) made of the semiconductor substrate 101 and simultaneously formed by the same process, but they are formed on different regions of the wafer, which makes the depth of the trench 103 different, and the trench in fig. 1B is individually marked with a mark 103a, and the depth of the trench 103a is greater than the depth of the trench 103 in fig. 1A. The depth of the trench 103a is increased due to the process characteristics of the etching process itself, that is, due to the characteristics of the etching process itself, even though the width and the depth of the designed trench are the same, it cannot be avoided that the actual depth of the trench formed on different regions of the wafer is different. This difference in the depth of the trenches eventually causes the breakdown voltages of the corresponding super junction cells to differ. Corresponding to the super junction product with large current, the breakdown voltage is too large and too small, which is not in accordance with the requirement.
The following is a description of a super junction device with specific parameters:
taking a 600V super junction device as an example, a general process will set the depth of the trench of the 600V super junction device to be about 42 μm, and then the depth of the trench is controlled within 10%, that is, about 4 μm, and may be smaller than 3 μm. According to the estimation of the withstand voltage change of 15V/mum-20V/mum, 4 micrometers will affect the breakdown voltage of 60V-80V. Unfortunately, both of these characteristics lead to an increase in breakdown voltage, since the edge region of the wafer is also at a greater angle and at a greater depth. Superposition of the two tends to result in excessive breakdown voltage values, as well as excessive BV in-plane spread (range).
In order to obtain lower resistivity, As is generally used As a doping impurity of the semiconductor substrate 101; the doping impurity of the N-type epitaxial layer 102 is typically phosphorus, and the thickness is 50 micrometers; the trench 103 is designed to have a depth of 42 microns and the remaining 8 microns of the N-epi layer 102 at the bottom of the trench 103 acts as a buffer layer. The buffer layer is mainly used for avoiding the etching of the groove into the N-type heavily doped semiconductor substrate 101, and if the N-type heavily doped semiconductor substrate 101 is directly contacted with the groove, N-type impurities in the semiconductor substrate 101 can be diffused into the P-type column 104 formed in the groove, so that the doping of the P-type column 104 is abnormal. The buffer layer is typically doped to a concentration that is consistent with the doping concentration of N-type epitaxial layer 102, and is typically formed directly from N-type epitaxial layer 102, and is not distinguishable from the overall N-type epitaxial layer 102.
As shown in fig. 2a1, which is a simulation diagram of the doping concentration profile of the conventional super junction device corresponding to fig. 1A; in the simulation graph of the doping concentration distribution, in the original simulation graph, different colors are adopted to represent different doping concentrations, and after the simulation graph is printed into a black-white graph, the different colors are converted into different gray scales; the depth direction of the trench is defined as an X-coordinate, and the direction along the surface of the wafer is defined as a Y-coordinate, as shown in fig. 2a 1. As shown in fig. 2a2, it is a simulation diagram of the doping concentration profile of the conventional super junction device corresponding to fig. 1B; it can be seen that the depth of the trench 103a is deeper than the depth of the trench 103 in figure 2a1, the trench 103 being 42 microns and the trench 103a being 46 microns.
Fig. 2B is a corresponding longitudinal doping concentration profile along the depth direction of the N-type pillar of fig. 2a1 or fig. 2a 2; the N-type epitaxial layer 102 corresponding to the N-type columns in fig. 2a1 and fig. 2a2 are the same, and the curve 201 is the doping concentration profile of the N-type epitaxial layer 102 along the X-coordinate, and it can be seen that the doping concentration of the N-type epitaxial layer 102 is 3E +15cm-3。
As shown in fig. 2C1, the electric field intensity distribution of the conventional super junction device corresponding to fig. 1A is simulated, in fig. 2C1, the electric field intensity is absolute value (ABS), in the original simulation, different colors are used to represent different doping concentrations, and after the original simulation is printed as a black-and-white image, the different colors are converted into different gray scales. FIG. 2C2 is a simulated graph of electric field strength distribution of the prior art super junction device corresponding to FIG. 1B; it can be seen that the maximum electric field intensity appears at the bottom of the trench 103a and the trench 103, the electric field intensity drops to 0V/cm in the semiconductor substrate 101 after passing through the buffer layer, and the super junction unit corresponding to the trench 103a has a larger withstand voltage because the depth of the bottom of the trench 103a is deeper. As shown in fig. 2D, is a corresponding electric field strength distribution curve along the depth direction of the N-type column of fig. 2C1 and 2C 2; curve 202 is the electric field strength distribution curve obtained from the X-axis of fig. 2C1, and curve 203 is the electric field strength distribution curve obtained from the X-axis of fig. 2C 2; it can be seen that the curve 203 extends to the bottom of the trench than the curve 202, so that the coverage area of the curve 203 is increased, and the breakdown voltage of the corresponding super junction cell is also increased.
As shown in fig. 2E, is a corresponding voltage distribution curve along the depth direction of the N-type pillar of fig. 1A and 1B; curve 204 corresponds to the breakdown voltage of the super junction cell corresponding to trench 103 of fig. 1A, and curve 205 corresponds to the breakdown voltage of the super junction cell corresponding to trench 103a of fig. 1B, and the final breakdown voltage of curve 205 increases due to the greater depth of trench 103 a. As shown in fig. 2E1, is an enlarged plot of the voltage distribution in fig. 2E corresponding to the bottom of the super junction; it can be seen that the difference between the two breakdown voltages is greater than 70V, i.e. BV > 70V.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a super junction device, which can improve the uniformity of the withstand voltage of the super junction unit formed at each position on a wafer, thereby improving the yield of products. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the above technical problem, the super junction device provided by the present invention comprises: the semiconductor device comprises an N-type heavily-doped semiconductor substrate, wherein an N-type doped buffer layer and an N-type doped first epitaxial layer are sequentially formed on the surface of the semiconductor substrate.
The super junction is formed by alternately arranging a plurality of P-type columns and N-type columns, and a super junction unit is formed by one P-type column and one corresponding N-type column.
The P-type columns are composed of a P-doped second epitaxial layer filled in the corresponding trenches.
The grooves are formed in the first epitaxial layer through photoetching definition and etching processes, the semiconductor substrate forms a wafer, and the depths of the grooves are different in different areas of the wafer; at least part of the bottom of the trench penetrates through the first epitaxial layer and enters the buffer layer; the N-type columns are formed by the first epitaxial layers or the buffer layers between the P-type columns.
The doping concentration of the buffer layer is greater than that of the first epitaxial layer and is less than that of the semiconductor substrate; the bottom inserting part of the super junction unit, the bottom of which is inserted into the buffer layer, is a part positioned in the buffer layer, the doping concentration of the buffer layer is also satisfied, the withstand voltage of the bottom inserting part of each corresponding super junction unit is determined by the doping concentration of the buffer layer, the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer, and therefore the uniformity of the withstand voltage of each super junction unit on the wafer is improved.
In a further improvement, on the same wafer, the bottom surface of the trench with the shallowest depth is in contact with the top surface of the buffer layer; alternatively, on the same wafer, the bottom surface of the trench having the shallowest depth is located below the top surface of the buffer layer.
The further improvement is that the doping concentration of the buffer layer is more than 3 times of the doping concentration of the first epitaxial layer.
In a further improvement, the minimum value of the depth variation range of the groove in the wafer surface is less than 10%.
In a further improvement, the semiconductor substrate is a silicon substrate, and the doping impurity of the semiconductor substrate is arsenic.
In a further improvement, the buffer layer, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.
In a further improvement, the doping impurities of the buffer layer and the first epitaxial layer are both phosphorus.
In a further improvement, the super junction device comprises a super junction MOSFET, the super junction device comprises a plurality of super junction device units connected in parallel, and each super junction device unit is formed on the corresponding super junction unit.
In order to solve the above technical problem, the method for manufacturing a super junction device provided by the present invention comprises the following steps:
providing an N-type heavily-doped semiconductor substrate, wherein the semiconductor substrate forms a wafer, and an N-type doped buffer layer and an N-type doped first epitaxial layer are sequentially formed on the surface of the semiconductor substrate; the doping concentration of the buffer layer is greater than that of the first epitaxial layer and is less than that of the semiconductor substrate.
And secondly, forming grooves in the first epitaxial layer by adopting a photoetching definition and etching process, wherein the depths of the grooves are different in different areas of the wafer, and at least part of the bottoms of the grooves penetrate through the first epitaxial layer and enter the buffer layer.
Filling a second P-type doped epitaxial layer in each groove to form a corresponding P-type column; the N-type columns are formed by the corresponding first epitaxial layers or the buffer layers between the P-type columns; a plurality of P-type columns and N-type columns are alternately arranged to form a super junction, and one P-type column and one corresponding N-type column form a super junction unit.
The bottom inserting part of the super junction unit, the bottom of which is inserted into the buffer layer, is a part positioned in the buffer layer, the doping concentration of the buffer layer is also satisfied, the withstand voltage of the bottom inserting part of each corresponding super junction unit is determined by the doping concentration of the buffer layer, the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer, and therefore the uniformity of the withstand voltage of each super junction unit on the wafer is improved.
In a further improvement, on the same wafer, the bottom surface of the trench with the shallowest depth is in contact with the top surface of the buffer layer; alternatively, on the same wafer, the bottom surface of the trench having the shallowest depth is located below the top surface of the buffer layer.
The further improvement is that the doping concentration of the buffer layer is more than 3 times of the doping concentration of the first epitaxial layer.
In a further improvement, the minimum value of the depth variation range of the groove in the wafer surface is less than 10%.
In a further improvement, the semiconductor substrate is a silicon substrate, and the doping impurity of the semiconductor substrate is arsenic.
In a further improvement, the buffer layer, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.
In a further improvement, the doping impurities of the buffer layer and the first epitaxial layer are both phosphorus.
The super junction in the super junction device adopts a structure that the super junction is isolated from the heavily doped semiconductor substrate at the bottom, so that the N-type heavily doped semiconductor substrate can be prevented from generating adverse effects on the doping of a P-type column of the super junction. The invention also makes special arrangement for the buffer layer between the super junction and the semiconductor substrate, mainly making the doping concentration of the buffer layer independent of the doping concentration of the top N-type doped first epitaxial layer and setting the doping concentration of the buffer layer to be larger than that of the first epitaxial layer, and setting the doping concentration of the buffer layer to make the withstand voltage of the super junction unit corresponding to the trench with the bottom extending into the buffer layer in the buffer layer determined by the doping concentration of the buffer layer, thus, even if the depth of the trench generates fluctuation caused by the etching process, the withstand voltage after extending into the buffer layer is the same, so the withstand voltage difference of each super junction unit is only determined by the upper part of the buffer layer, namely the top part of the super junction unit, thus greatly reducing the withstand voltage, namely the breakdown voltage difference between the super junction units, the voltage resistance difference of the super junction unit caused by the depth difference of the grooves can be reduced or eliminated, the voltage resistance fluctuation of the super junction unit is basically determined by the thickness fluctuation of the first epitaxial layer, the thickness of the first epitaxial layer formed by the epitaxial process can be controlled accurately, the voltage resistance uniformity of the super junction unit formed at each position on the wafer can be improved finally, and the product yield can be improved.
The invention can enable the bottom of a part of deeper grooves to be inserted into the buffer layer, and the bottoms of other shallower grooves are not inserted into the buffer layer, at this time, the actual withstand voltage depth of the corresponding super junction units inserted into the buffer layer is approximately equal to the distance between the top surface of the buffer layer and the top surface of the first epitaxial layer; the actual withstand voltage depth corresponding to the super junction unit corresponding to the trench, the bottom of which is not inserted into the buffer layer, is the depth of the super junction unit itself, that is, the depth of the trench, obviously, the maximum difference of the breakdown voltage of each super junction unit is only determined by the distance from the bottom surface of the shallowest trench to the top surface of the buffer layer, but not by the depth difference between the shallowest trench and the deepest trench, so that the uniformity of the withstand voltage of the super junction unit formed at each position on the wafer can be finally improved.
In addition, when the shallowest groove is also contacted with or inserted into the buffer layer, the actual withstand voltage depth of all super junction units on the wafer is approximately equal to the distance from the top surface of the buffer layer to the top surface of the first epitaxial layer, and the uniformity of breakdown voltage among the super junction units is better.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1A is a schematic diagram of a super junction in a shallow trench depth region of a conventional super junction device;
FIG. 1B is a schematic diagram of a super junction in a region with a deeper trench depth of a conventional super junction device;
FIG. 2A1 is a simulation plot of the doping concentration profile of the prior art super junction device corresponding to FIG. 1A;
FIG. 2A2 is a simulation plot of the doping concentration profile of the prior art super junction device corresponding to FIG. 1B;
FIG. 2B is a corresponding longitudinal doping concentration profile along the depth direction of the N-type column of FIG. 2A1 or FIG. 2A 2;
FIG. 2C1 is a simulated graph of electric field strength distribution for the prior art super-junction device corresponding to FIG. 1A;
FIG. 2C2 is a simulated graph of electric field strength distribution of the prior art super junction device corresponding to FIG. 1B;
fig. 2D is a corresponding electric field strength distribution curve in the depth direction of the N-type pillars of fig. 2C1 and 2C 2;
FIG. 2E is a voltage profile along the depth of the N-type pillars of FIGS. 1A and 1B;
FIG. 2E1 is an enlarged plot of the voltage distribution in FIG. 2E corresponding to the bottom of the super junction;
FIG. 3A is a schematic diagram of a super junction in a shallow trench depth region of a super junction device in accordance with an embodiment of the present invention;
FIG. 3B is a schematic diagram of a super junction in a region with a deeper trench depth of a super junction device according to an embodiment of the present invention;
FIG. 4A1 is a simulation plot of the doping concentration profile of the super junction device of the embodiment of the present invention corresponding to FIG. 3A;
FIG. 4A2 is a simulation plot of the doping concentration profile of the super junction device of the embodiment of the present invention corresponding to FIG. 3B;
FIG. 4B is a corresponding longitudinal doping concentration profile along the depth direction of the N-type pillar of FIG. 4A1 or FIG. 4A 2;
FIG. 4C is a voltage profile corresponding along the depth direction of the N-type pillars of FIGS. 3A and 3B;
FIG. 4C1 is an enlarged plot of the voltage distribution in FIG. 4C corresponding to the bottom of the super junction;
FIG. 4D1 is a simulated graph of the electric field strength distribution of the super junction device of the embodiment of the invention corresponding to FIG. 3A;
FIG. 4D2 is a simulation plot of the electric field strength distribution of the super junction device of the embodiment of the present invention corresponding to FIG. 3B;
fig. 4E is a corresponding electric field intensity distribution curve in the depth direction of the N-type pillars of fig. 4D1 and 4D 2.
Detailed Description
Fig. 3A is a schematic diagram of a super junction in a shallow trench 3 region of a super junction device according to an embodiment of the present invention; fig. 3B is a schematic diagram of a super junction in a region with a deep trench 3 of the super junction device according to the embodiment of the present invention; the super junction device of the embodiment of the invention comprises: the semiconductor device comprises an N-type heavily-doped semiconductor substrate 1, wherein an N-type doped buffer layer 5 and an N-type doped first epitaxial layer 2 are sequentially formed on the surface of the semiconductor substrate 1.
The super junction is formed by alternately arranging a plurality of P-type columns 4 and N-type columns, and a super junction unit is formed by one P-type column 4 and one corresponding N-type column.
The P-type columns 4 are composed of a second epitaxial layer of P-type doping filled in the corresponding trenches 3.
The trenches 3 are formed in the first epitaxial layer 2 by photolithography definition and etching processes, the semiconductor substrate 1 forms a wafer, the depths of the trenches 3 are different in different regions of the wafer, and in fig. 3B, the deeper trenches are individually denoted by reference numeral 3 a; at least part of the bottom of the trench 3 penetrates through the first epitaxial layer 2 into the buffer layer 5; the N-type columns are formed by the first epitaxial layer 2 or the buffer layer 5 which correspond to the P-type columns 4.
The doping concentration of the buffer layer 5 is greater than that of the first epitaxial layer 2, and the doping concentration of the buffer layer 5 is less than that of the semiconductor substrate 1; the bottom insertion part of the super junction unit, the bottom of which is inserted into the buffer layer 5, is a part located in the buffer layer 5, the doping concentration of the buffer layer 5 is also such that the withstand voltage of the bottom insertion part of each corresponding super junction unit is determined by the doping concentration of the buffer layer 5, and the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer 5, that is, the actual withstand voltage depth of the corresponding super junction unit is the distance from the top surface of the buffer layer 5 to the top surface of the first epitaxial layer 2, that is, the thickness of the first epitaxial layer 2, and is not determined by the depth of the corresponding trench, so as to improve the uniformity of withstand voltage of each super junction unit on the wafer.
In the embodiment of the present invention, as long as the bottom of the partially deeper trench 3a is inserted into the buffer layer 5, the effect of improving the uniformity of the withstand voltage of each super junction unit on the wafer can be achieved. The preferred choices are: on the same wafer, the bottom surface of the trench 3 with the shallowest depth is in contact with the top surface of the buffer layer 5; alternatively, on the same wafer, the bottom surface of the trench 3 with the shallowest depth is located below the top surface of the buffer layer 5.
The doping concentration of the buffer layer 5 is more than 3 times of the doping concentration of the first epitaxial layer 2, and the typical value is 6.6 times.
The minimum value of the depth variation range of the groove 3 in the wafer surface is less than 10%. The depth variation range of the trench 3 is generally related to the width of the trench 3, and generally, the depth variation range of the trench 3 in the wafer surface can be controlled within 10%; for a trench 3 with a large aspect ratio, the depth variation range of the trench 3 in the wafer plane may be more than 10%.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the impurity doped in the semiconductor substrate 1 is arsenic.
The buffer layer 5, the first epitaxial layer 2 and the second epitaxial layer are all silicon epitaxial layers.
The doping impurities of the buffer layer 5 and the first epitaxial layer 2 are both phosphorus.
The super junction device comprises a super junction MOSFET, the super junction device comprises a plurality of super junction device units which are connected in parallel, and each super junction device unit is formed on the corresponding super junction unit. In other embodiments, the super junction device can also be a super junction IGBT, a super junction diode.
The super junction in the super junction device provided by the embodiment of the invention adopts a structure that the super junction is isolated from the heavily doped semiconductor substrate 1 at the bottom, so that the N-type heavily doped semiconductor substrate 1 can be prevented from generating adverse effects on the doping of the P-type column 4 of the super junction. The embodiment of the invention also makes special arrangement for the structure of the buffer layer 5 between the super junction and the semiconductor substrate 1, mainly a doping structure, and mainly makes the doping concentration of the buffer layer 5 independent of the doping concentration of the first epitaxial layer 2 doped with N type at the top, and sets the doping concentration of the buffer layer 5 to be larger than that of the first epitaxial layer 2, and also sets the doping concentration of the buffer layer 5 to make the withstand voltage of the super junction unit corresponding to the trench 3 with the bottom extending into the buffer layer 5 in the buffer layer 5 be determined by the doping concentration of the buffer layer 5, so that even if the depth of the trench 3 generates fluctuation caused by the etching process, the withstand voltage after extending into the buffer layer 5 is the same, the withstand voltage size difference of each super junction unit is only determined by the upper part of the buffer layer 5, namely the top part of the super junction unit, thus the withstand voltage difference between the super junction units, namely the breakdown voltage, can be greatly reduced, therefore, the uniformity of the withstand voltage of the super junction unit formed at each position on the wafer can be improved, and the product yield can be improved.
According to the embodiment of the invention, the bottoms of the partial deep grooves 3 are inserted into the buffer layer 5, and the bottoms of other shallow grooves 3 are not inserted into the buffer layer 5, so that the actual withstand voltage depth of the corresponding super junction units inserted into the buffer layer 5 is approximately equal to the distance from the top surface of the buffer layer 5 to the top surface of the first epitaxial layer 2; the actual withstand voltage depth corresponding to the super junction unit with the bottom being the trench 3 inserted into the buffer layer 5 is the depth of the super junction unit itself, that is, the depth of the trench 3, and obviously, the maximum difference of the breakdown voltages of the super junction units is only determined by the distance from the bottom surface of the shallowest trench 3 to the top surface of the buffer layer 5, but not by the depth difference between the shallowest trench and the deepest trench 3, so that the uniformity of the withstand voltage of the super junction unit formed at each position on the wafer can be finally improved.
In addition, in the embodiment of the present invention, when the shallowest trench 3 also contacts the buffer layer 5 or is inserted into the buffer layer 5, the actual withstand voltage depth of all super junction units on the wafer will be approximately equal to the distance from the top surface of the buffer layer 5 to the top surface of the first epitaxial layer 2, and then the uniformity of the breakdown voltage between the super junction units is better.
The device structure of the embodiment of the invention is described by combining specific parameters and carrying out simulation:
FIG. 4A1 is a simulation graph of the doping concentration profile of the super junction device of FIG. 3A according to an embodiment of the present invention; in the simulation graph of the doping concentration distribution, in the original simulation graph, different colors are adopted to represent different doping concentrations, and after the simulation graph is printed into a black-white graph, the different colors are converted into different gray scales; the depth direction of the trench is defined as an X-coordinate, and the direction along the surface of the wafer is defined as a Y-coordinate, as shown in fig. 4a 1.
FIG. 4A2 is a simulation graph of the doping concentration profile of the super junction device of FIG. 3B according to an embodiment of the present invention; it can be seen that the depth of the trench 3a is deeper than the depth of the trench 3 in fig. 4a1, the trench 3 being 42 microns and the trench 3a being 46 microns.
As shown in fig. 4B, is a corresponding longitudinal doping concentration profile along the depth direction of the N-type pillar of fig. 4a1 or fig. 4a 2; n- type epitaxial layers 2 and 2 of the N-type columns of FIGS. 4A1 and 4A2, respectivelyThe buffer layers 5 are all the same, and the curve 301 is the doping concentration distribution curve of the N-type epitaxial layer 2 and the buffer layer 5 along the X-coordinate, and it can be seen that the doping concentration of the N-type epitaxial layer 102 is 3E +15cm-3. The doping concentration of the buffer layer 5 is 2E +16cm-3。
As shown in fig. 4C, is a corresponding voltage profile along the depth direction of the N-type pillar of fig. 3A and 3B; curve 302 corresponds to the withstand voltage of the super junction cell corresponding to trench 3 of fig. 3A, and curve 303 corresponds to the withstand voltage of the super junction cell corresponding to trench 3A of fig. 3B. As shown in fig. 4C1, is an enlarged plot of the voltage distribution in fig. 4C corresponding to the bottom of the super junction; it can be seen that the difference between the two breakdown voltages is less than 10V, i.e. BV < 10V. Compared with the prior BV > 70V shown in FIG. 2E1, the uniformity of breakdown voltage of each super-junction unit is greatly improved.
FIG. 4D1 is a simulation diagram of the electric field intensity distribution of the super junction device of the embodiment of the present invention shown in FIG. 3A; the absolute value of the electric field intensity (ABS) is obtained, different colors are adopted to represent different doping concentrations in an original simulation diagram, and after the original simulation diagram is printed into a black-white diagram, different colors are converted into different gray scales. FIG. 4D2 is a simulation diagram of the electric field intensity distribution of the super junction device of the embodiment of the present invention corresponding to FIG. 3B; in the embodiment of the present invention, the bottom of the trench 3 is directly contacted with the top surface of the buffer layer 5, and the bottom of the trench 3a is inserted into the buffer layer 5, it can be seen that the maximum electric field strength of the super junction unit corresponding to the trench 3a and the trench 3 is present at the surface position of the buffer layer 5 and will be reduced by about 0V/cm in the buffer layer 5, so the voltage endurance capability of the super junction unit corresponding to the trench 3a and the trench 3 is equivalent. As shown in fig. 4E, is a corresponding electric field intensity distribution curve along the depth direction of the N-type column of fig. 4D1 and 4D 2; curve 304 is the electric field strength distribution curve obtained from the X-axis of fig. 4D1, and curve 305 is the electric field strength distribution curve obtained from the X-axis of fig. 4D 2; it can be seen that the electric field strength of curve 305 has dropped significantly from the surface of the buffer layer 5, although the electric field width is greater due to the trench depth, resulting in a significant drop in breakdown voltage due to the loss of the triangular spike electric field at the bottom.
The manufacturing method of the super junction device comprises the following steps:
providing an N-type heavily-doped semiconductor substrate 1, forming a wafer on the semiconductor substrate 1, and sequentially forming an N-type doped buffer layer 5 and an N-type doped first epitaxial layer 2 on the surface of the semiconductor substrate 1; the doping concentration of the buffer layer 5 is greater than that of the first epitaxial layer 2 and the doping concentration of the buffer layer 5 is less than that of the semiconductor substrate 1.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate, and the doped impurity of the semiconductor substrate 1 is arsenic.
The buffer layer 5, the first epitaxial layer 2 and the subsequent second epitaxial layer are all silicon epitaxial layers.
The doping impurities of the buffer layer 5 and the first epitaxial layer 2 are both phosphorus.
Step two, forming a groove 3 in the first epitaxial layer 2 by adopting a photoetching definition and etching process, wherein the depth of the groove 3 is different in different areas of the wafer, and at least part of the bottom of the groove 3 penetrates through the first epitaxial layer 2 and enters the buffer layer 5.
The minimum value of the depth variation range of the groove 3 in the wafer surface is less than 10%.
Filling a second P-type doped epitaxial layer in each trench 3 to form a corresponding P-type column 4; the N-type columns are formed by the corresponding first epitaxial layers 2 or the buffer layers 5 between the P-type columns 4; a plurality of P-type columns 4 and N-type columns are alternately arranged to form a super junction, and one P-type column 4 and one corresponding N-type column form a super junction unit.
The bottom insertion part of the super junction unit with the bottom inserted into the buffer layer 5 is a part located in the buffer layer 5, the doping concentration of the buffer layer 5 is also such that the withstand voltage of the bottom insertion part of each corresponding super junction unit is determined by the doping concentration of the buffer layer 5, the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer 5, and therefore the uniformity of the withstand voltage of each super junction unit on the wafer is improved.
Preferably, on the same wafer, the bottom surface of the trench 3 with the shallowest depth is in contact with the top surface of the buffer layer 5; alternatively, on the same wafer, the bottom surface of the trench 3 with the shallowest depth is located below the top surface of the buffer layer 5.
The doping concentration of the buffer layer 5 is more than 3 times of the doping concentration of the first epitaxial layer 2.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A super junction device, comprising: the semiconductor device comprises an N-type heavily-doped semiconductor substrate, wherein an N-type doped buffer layer and an N-type doped first epitaxial layer are sequentially formed on the surface of the semiconductor substrate;
the super junction is formed by alternately arranging a plurality of P-type columns and N-type columns, and a super junction unit is formed by one P-type column and one corresponding N-type column;
the P-type columns are composed of P-type doped second epitaxial layers filled in the corresponding grooves;
the grooves are formed in the first epitaxial layer through photoetching definition and etching processes, the semiconductor substrate forms a wafer, and the depths of the grooves are different in different areas of the wafer; at least part of the bottom of the trench penetrates through the first epitaxial layer and enters the buffer layer; the N-type columns are formed by the corresponding first epitaxial layers or the buffer layers between the P-type columns;
the doping concentration of the buffer layer is greater than that of the first epitaxial layer and is less than that of the semiconductor substrate; the bottom inserting part of the super junction unit, the bottom of which is inserted into the buffer layer, is a part positioned in the buffer layer, the doping concentration of the buffer layer is also satisfied, the withstand voltage of the bottom inserting part of each corresponding super junction unit is determined by the doping concentration of the buffer layer, the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer, and therefore the uniformity of the withstand voltage of each super junction unit on the wafer is improved.
2. The super-junction device of claim 1, wherein: on the same wafer, the bottom surface of the groove with the shallowest depth is contacted with the top surface of the buffer layer; alternatively, on the same wafer, the bottom surface of the trench having the shallowest depth is located below the top surface of the buffer layer.
3. The super-junction device of claim 1 or 2, wherein: the doping concentration of the buffer layer is more than 3 times of that of the first epitaxial layer.
4. The super-junction device of claim 1, wherein: the minimum value of the depth variation range of the groove in the wafer surface is less than 10%.
5. The super-junction device of claim 1, wherein: the semiconductor substrate is a silicon substrate, and the doped impurities of the semiconductor substrate are arsenic.
6. The super-junction device of claim 5, wherein: the buffer layer, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.
7. The super-junction device of claim 6, wherein: the doping impurities of the buffer layer and the first epitaxial layer are phosphorus.
8. The super-junction device of claim 1, wherein: the super junction device comprises a super junction MOSFET, the super junction device comprises a plurality of super junction device units which are connected in parallel, and each super junction device unit is formed on the corresponding super junction unit.
9. A method for manufacturing a super junction device is characterized by comprising the following steps:
providing an N-type heavily-doped semiconductor substrate, wherein the semiconductor substrate forms a wafer, and an N-type doped buffer layer and an N-type doped first epitaxial layer are sequentially formed on the surface of the semiconductor substrate; the doping concentration of the buffer layer is greater than that of the first epitaxial layer and is less than that of the semiconductor substrate;
step two, forming grooves in the first epitaxial layer by adopting a photoetching definition and etching process, wherein the depths of the grooves are different in different areas of the wafer, and at least part of the bottoms of the grooves penetrate through the first epitaxial layer and enter the buffer layer;
filling a second P-type doped epitaxial layer in each groove to form a corresponding P-type column; the N-type columns are formed by the corresponding first epitaxial layers or the buffer layers between the P-type columns; a plurality of P-type columns and N-type columns are alternately arranged to form a super junction, and one P-type column and one corresponding N-type column form a super junction unit;
the bottom inserting part of the super junction unit, the bottom of which is inserted into the buffer layer, is a part positioned in the buffer layer, the doping concentration of the buffer layer is also satisfied, the withstand voltage of the bottom inserting part of each corresponding super junction unit is determined by the doping concentration of the buffer layer, the actual withstand voltage depth of each super junction unit is determined by the part above the top surface of the buffer layer, and therefore the uniformity of the withstand voltage of each super junction unit on the wafer is improved.
10. The method of manufacturing a super junction device of claim 9, wherein: on the same wafer, the bottom surface of the groove with the shallowest depth is contacted with the top surface of the buffer layer; alternatively, on the same wafer, the bottom surface of the trench having the shallowest depth is located below the top surface of the buffer layer.
11. The method of manufacturing a super junction device according to claim 9 or 10, wherein: the doping concentration of the buffer layer is more than 3 times of that of the first epitaxial layer.
12. The method of manufacturing a super junction device of claim 9, wherein: the minimum value of the depth variation range of the groove in the wafer surface is less than 10%.
13. The method of manufacturing a super junction device of claim 9, wherein: the semiconductor substrate is a silicon substrate, and the doped impurities of the semiconductor substrate are arsenic.
14. The method of manufacturing a super junction device of claim 13, wherein: the buffer layer, the first epitaxial layer and the second epitaxial layer are all silicon epitaxial layers.
15. The method of manufacturing a super junction device of claim 14, wherein: the doping impurities of the buffer layer and the first epitaxial layer are phosphorus.
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