CN111367731A - Method and equipment for testing low delay of storage performance - Google Patents
Method and equipment for testing low delay of storage performance Download PDFInfo
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- CN111367731A CN111367731A CN202010108208.0A CN202010108208A CN111367731A CN 111367731 A CN111367731 A CN 111367731A CN 202010108208 A CN202010108208 A CN 202010108208A CN 111367731 A CN111367731 A CN 111367731A
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- 238000012360 testing method Methods 0.000 title claims abstract description 156
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000011056 performance test Methods 0.000 claims abstract description 20
- 230000004044 response Effects 0.000 claims abstract description 7
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 230000007334 memory performance Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 description 8
- 238000004590 computer program Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention provides a method and equipment for testing low delay of storage performance, wherein the method comprises the following steps: setting the path of the IO test as the path of the storage performance test; setting the IOPS size of the IO test as a preset threshold value, and setting the IO test item proportion as a preset proportion; responding to the received instruction of the IO test, executing the IO test according to the IO test item under the path and monitoring IO information; and starting the storage performance test in response to the IO information reaching the stable state. By using the scheme of the invention, the problem of test failure caused by overhigh test delay can be solved by starting the IO test in the background under the condition of not influencing the IOPS of the test, and the storage test performance is improved.
Description
Technical Field
The field relates to the field of computers, and more particularly to a method and apparatus for low latency memory performance testing.
Background
The storage performance test is directed to the performance of the storage subsystem in executing the critical business application. These applications are mainly characterized by random IO operations, including query and update operations. Examples of such applications include OLTP, database operations, and mail server operations, among others. As medium and high-end storage systems tend to act as a data base platform for critical business applications in the user's system environment.
In the storage performance test, a key index that the test can successfully pass is test delay, a test tool used by the test tool is to set an IOPS (number of times of read-write (I/O) operation per second) value, namely the number of times of reading and writing data per second of the storage system to reflect the performance of the storage system and run the IOPS value, all test process delay in the running process must be less than 30ms, the test is successful, and the final test result is the preset IOPS value.
If the higher end performance is better if the storage is in the test, the final IOPS value of the test is higher, the IOPS value set in the test is higher, and when the IOPS value is high, the IOPS is suddenly increased to the maximum value in a short time (the IOPS is increased to the maximum value within 1 minute required by a test tool) from zero in the test process, so that IO read-write is suddenly increased, and the system delay is too high. So that it cannot be guaranteed that the delay in the whole test process is less than 30ms, resulting in a whole test loss.
The test tool used is mainly divided into three test phases: pre-population, main test and data consistency test. The main test phase has a sustatin test phase (100% IOPS test in the sustatin phase) of at least 8 hours and a repeatability (25% IOPS test in the sustatin phase) phase, the system is in an empty load state before the test in the two phases, the disk IOPS is suddenly increased from the empty load phase to the sustatin and repeatability phases, and the test can cause the delay to suddenly increase to thousands or even ten thousand milliseconds, and finally cause the test to fail. The prior art can only not suddenly increase high delay when the IOPS is slowly increased from 0 to the maximum, and cannot solve the high delay phenomenon of the starting process of the two stages. At present, the problem is solved only by replacing a disk with higher performance and higher read-write speed, part of the problems can be solved by replacing the disk with higher performance in the prior art, but the problem cannot be solved under the condition of higher IOPS, and the disk with higher performance has high cost.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method and a device for testing storage performance with low latency, which can solve the problem of test failure caused by too high test latency by starting an IO test in a background without affecting an IOPS of the test, and improve the storage test performance.
In view of the above object, an aspect of the embodiments of the present invention provides a method for low latency memory performance test, including the steps of:
setting the path of the IO test as the path of the storage performance test;
setting the IOPS size of the IO test as a preset threshold value, and setting the IO test item proportion as a preset proportion;
responding to the received instruction of the IO test, executing the IO test according to the IO test item under the path and monitoring IO information;
and starting the storage performance test in response to the IO information reaching the stable state.
According to an embodiment of the present invention, the preset threshold is 20000.
According to one embodiment of the invention, the IO test items include random reads and random writes.
According to one embodiment of the invention, the preset ratio is a ratio of random read to random write of 7 to 3.
According to one embodiment of the present invention, responding to the IO information reaching the steady state includes:
and responding to the increase of the IOPS from 0 to a preset threshold value in the IO test, and judging that the IO information reaches a stable state.
In another aspect of the embodiments of the present invention, there is also provided an apparatus for low latency memory performance testing, the apparatus including:
the path setting module is configured to set the path of the IO test as a path of the storage performance test;
the parameter setting module is configured to set the size of the IOPS of the IO test as a preset threshold value and set the proportion of IO test items as a preset proportion;
the IO test module is configured to respond to a received IO test instruction, execute an IO test according to an IO test item under a path and monitor IO information;
and the storage performance testing module is configured to respond to the IO information reaching a stable state and start the storage performance testing.
According to an embodiment of the present invention, the preset threshold is 20000.
According to one embodiment of the invention, the IO test items include random reads and random writes.
According to one embodiment of the invention, the preset ratio is a ratio of random read to random write of 7 to 3.
According to an embodiment of the present invention, the storage performance testing module is further configured to determine that the IO information reaches the steady state in response to the IOPS increasing from 0 to the preset threshold in the IO test.
The invention has the following beneficial technical effects: according to the method for realizing the low delay of the storage performance test, provided by the embodiment of the invention, the path of the IO test is set as the path of the storage performance test; setting the IOPS size of the IO test as a preset threshold value, and setting the IO test item proportion as a preset proportion; responding to the received instruction of the IO test, executing the IO test according to the test item under the path and monitoring IO information; the technical scheme of starting the storage performance test in response to the fact that the IO information reaches the stable state can solve the problem of test failure caused by too high test delay by starting the IO test in the background under the condition that the IOPS of the test is not influenced, and the storage test performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method of implementing low latency memory performance testing in accordance with one embodiment of the present invention;
FIG. 2 is a diagram of an apparatus for implementing low latency memory performance testing, according to one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a method for memory performance testing with low latency. Fig. 1 shows a schematic flow diagram of the method.
As shown in fig. 1, the method may include the steps of:
s1, setting the path of the IO test as the path of the storage performance test, and selecting the hard disk to be tested to be consistent with the hard disk of the storage performance test, otherwise, the test is meaningless;
s2, setting the size of the IOPS for the IO test as a preset threshold, setting the proportion of the IO test items as a preset proportion, stipulating and setting the size of the IOPS and the proportion of the test items and items, and setting the size of the IOPS for the IO test as 20000;
s3, responding to the received instruction of the IO test, executing the IO test according to the IO test item and monitoring IO information under the path, monitoring and acquiring the IO information in real time through a command, judging whether the IO is increased from 0 to a stable state of a preset threshold value, and continuously collecting the IO information if the IO is not increased to the stable state;
and S4, responding to the fact that the IO information reaches a stable state, starting a storage performance test, starting a sustatin long-time stability test, continuing the IO test for 4 minutes, after 4 minutes, forcibly finishing the IO test, wherein the IO test execution step in the Repeat test stage is consistent with the sustatin stage, and is not described again.
Because of the limitation of a storage performance testing tool, the IO testing pressure needs to be increased by setting a specific IOPS value, so as to solve the problem of storage performance testing delay fluctuation, but in the prior art, there is no tool for directly setting an IOPS value to test IO, wherein the IO testing standard includes sequential reading, sequential writing, random reading, random writing and mixed read-write operation. In order to solve the problem of sudden high delay of the storage performance test, IO test is added, and the purpose of increasing enough pressure to the hard disk can be achieved by selecting the mixed operation of random reading and random writing. The pressure of sequential reading and writing is small.
By the technical scheme, the problem of test failure caused by overhigh test delay can be solved by starting the IO test through the background under the condition of not influencing the IOPS of the test, and the storage test performance is improved.
In a preferred embodiment of the present invention, the preset threshold is 20000, an IO test cannot be directly performed by specifying the size of the IOPS in the prior art, and this specification of 20000IOPS does not change, because optimal data is obtained for multiple test experiments.
In a preferred embodiment of the present invention, the IO test items include random read and random write. In a preferred embodiment of the invention, the predetermined ratio is a ratio of random read to random write of 7 to 3. The random reading and the random writing respectively account for 70 percent and 30 percent, and the random reading and writing proportion is specified to obtain the optimal data for a plurality of test experiments and cannot be changed.
In a preferred embodiment of the present invention, the response to the IO information reaching the steady state comprises:
and responding to the increase of the IOPS from 0 to a preset threshold value in the IO test, and judging that the IO information reaches a stable state. If the test is stable 10 minutes after the superstain and repeat tests reach the appointed IOPS values after starting, the IO test started in advance can be stopped, and delay fluctuation can not be caused.
The method of the invention gives a read-write pressure to the disk in advance before starting the storage performance test, and continuously runs until the sustain and repeat run stably, so that the test failure caused by overhigh delay due to the sudden increase of the IOPS can not occur when testing the ustain and the repeat, and the IO test delay can not fluctuate after the sustain and repeat test is stable.
By the technical scheme, the problem of test failure caused by overhigh test delay can be solved by starting the IO test through the background under the condition of not influencing the IOPS of the test, and the storage test performance is improved.
It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the above programs may be stored in a computer-readable storage medium, and when executed, the programs may include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
In view of the above object, a second aspect of the embodiments of the present invention proposes a device for low latency memory performance testing, as shown in fig. 2, the device 200 includes:
the path setting module is configured to set the path of the IO test as a path of the storage performance test;
the parameter setting module is configured to set the size of the IOPS of the IO test as a preset threshold value and set the proportion of IO test items as a preset proportion;
the IO test module is configured to respond to a received IO test instruction, execute an IO test according to an IO test item under a path and monitor IO information;
and the storage performance testing module is configured to respond to the IO information reaching a stable state and start the storage performance testing.
In a preferred embodiment of the present invention, the preset threshold is 20000.
In a preferred embodiment of the present invention, the IO test items include random read and random write.
In a preferred embodiment of the invention, the predetermined ratio is a ratio of random read to random write of 7 to 3.
In a preferred embodiment of the present invention, the storage performance testing module is further configured to determine that the IO information reaches the steady state in response to the IOPS increasing from 0 to the preset threshold in the IO test.
It should be particularly noted that the embodiment of the system described above employs the embodiment of the method described above to specifically describe the working process of each module, and those skilled in the art can easily think that the modules are applied to other embodiments of the method described above.
Further, the above-described method steps and system elements or modules may also be implemented using a controller and a computer-readable storage medium for storing a computer program for causing the controller to implement the functions of the above-described steps or elements or modules.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A method for memory performance testing with low latency, comprising the steps of:
setting the path of the IO test as the path of the storage performance test;
setting the IOPS size of the IO test as a preset threshold value, and setting the IO test item proportion as a preset proportion;
responding to an instruction of receiving an IO test, executing the IO test according to the IO test item under the path and monitoring IO information;
and responding to the IO information reaching a stable state, and starting the storage performance test.
2. The method according to claim 1, wherein the preset threshold is 20000.
3. The method of claim 1, wherein the IO test items include random reads and random writes.
4. The method of claim 3, wherein the predetermined ratio is a ratio of the random read to the random write of 7 to 3.
5. The method of claim 1, wherein responding to the IO information reaching a steady state comprises:
and responding to the increase of the IOPS from 0 to the preset threshold value in the IO test, and judging that the IO information reaches a stable state.
6. An apparatus for memory performance testing with low latency, the apparatus comprising:
a path setting module configured to set a path of an IO test as a path of the storage performance test;
the parameter setting module is configured to set the size of the IOPS of the IO test as a preset threshold value and set the proportion of the IO test items as a preset proportion;
the IO test module is configured to respond to a received IO test instruction, execute the IO test according to the IO test item under the path and monitor IO information;
and the storage performance testing module is configured to respond to the IO information reaching a stable state and start the storage performance testing.
7. The apparatus of claim 6, wherein the preset threshold is 20000.
8. The device of claim 6, wherein the IO test items comprise random reads and random writes.
9. The apparatus of claim 8, wherein the preset ratio is a ratio of the random read to the random write of 7 to 3.
10. The device of claim 6, wherein the storage performance testing module is further configured to determine that the IO information reaches a steady state in response to the IOPS increasing from 0 to the preset threshold during the IO test.
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| CN202010108208.0A CN111367731A (en) | 2020-02-21 | 2020-02-21 | Method and equipment for testing low delay of storage performance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117476086A (en) * | 2023-12-26 | 2024-01-30 | 成都佰维存储科技有限公司 | Memory performance test method and device, readable storage medium and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117476086A (en) * | 2023-12-26 | 2024-01-30 | 成都佰维存储科技有限公司 | Memory performance test method and device, readable storage medium and electronic equipment |
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Application publication date: 20200703 |