CN111355290A

CN111355290A - Multi-path wireless charging and transmitting system for small unmanned aerial vehicle

Info

Publication number: CN111355290A
Application number: CN202010303452.2A
Authority: CN
Inventors: 高博; 任昊达; 霍佳雨; 田小建; 吴戈; 王俊凯; 温继贤; 汝玉星
Original assignee: Jilin University
Current assignee: Zhuhai Haoxun Optoelectronic Technology Co ltd
Priority date: 2020-04-16
Filing date: 2020-04-16
Publication date: 2020-06-30
Anticipated expiration: 2040-04-16
Also published as: CN111355290B

Abstract

The invention discloses a multipath wireless charging and transmitting system for a small unmanned aerial vehicle, and belongs to the technical field of electronic equipment. The structure of the device is that the device is provided with a power management circuit (1), a control time sequence generating circuit (8), a reference voltage circuit (9) and an output matrix (10); the output matrix (10) comprises n output channels, the n output channels have the same circuit structure, and each output channel comprises a voltage regulating circuit (2), an energy transmitting circuit (3), a current detection amplifying circuit (4), a signal shaping circuit (5), an output automatic control circuit (6) and a voltage detection circuit (7). The invention can wirelessly charge a plurality of unmanned aerial vehicles at the same time, is convenient to use, and improves the efficiency of the energy emission module because the energy emission module in the output channel always works at the optimal voltage.

Description

Multi-path wireless charging and transmitting system for small unmanned aerial vehicle

Technical Field

The invention belongs to the technical field of electronic equipment, and particularly relates to a multi-path wireless charging and transmitting system for a small unmanned aerial vehicle.

Background

An unmanned aerial vehicle (namely an unmanned plane) is a wide variety of remote control aircrafts without boarding and driving by a driver. Unmanned aerial vehicles were first applied to the military because of their good performance such as fast flight speed, target-hitting standard. After the nineties of the twentieth century, along with the rapid development of micro-electro-mechanical systems (MEMS) technology and the continuous improvement of single chip microcomputer performance, multi-rotor unmanned aerial vehicles carrying small inertial navigation systems have come out. Therefore, the miniature and civil wave of the unmanned aerial vehicle is opened. In recent years, unmanned aerial vehicles are gradually applied to the aspects of aerial photography, express delivery logistics, environmental monitoring, equipment inspection and the like. At present, the market development of domestic small unmanned aerial vehicles in China is rapid, and the application scenes of the small unmanned aerial vehicles are continuously widened. However, unmanned aerial vehicles on the market mostly adopt the mode of artifical wired charging, and it is very inconvenient to charge when unmanned aerial vehicle carries out the operation in the open air, and this has restricted unmanned aerial vehicle's extensive use to a certain extent. Meanwhile, in recent years, wireless charging technology is continuously mature, and the wireless charging technology is successfully applied to automobiles, mobile phones and small household appliances within a certain range. Compare in wired energy transmission mode, wireless charging does not receive the space restriction, and does not have to connect and insert the link, does not have naked conductor that leaks, is fit for more being the energy supply of unmanned aerial vehicle.

The closest prior art to this application is: chinese patent with publication number CN110789369, "a charging platform and charging method of unmanned aerial vehicle based on wireless charging", made innovation in the aspects of coil electromagnetic optimization, etc.; the chinese patent with application number 2018108887219, "an adaptive reactance wireless energy transmission system", provides some improvements to the wireless charging transmission system in impedance matching and the like. However, the above patents also have certain disadvantages: 1. the adopted high-frequency inverter circuit supplies power for fixed voltage, the equivalent impedance reflected to a transmitting system by a receiving end is ever-changing, when the reflection impedance is reduced, the inverter current is increased, so that the system is threatened and even damaged, otherwise, when the reflection impedance is increased, the inverter current is reduced, the charging power is too low, and the charging speed is slowed down. On the other hand, when the load disappears completely (such as being full or removing the charged device), the system does not automatically stop transmitting energy, and according to the mutual inductance coupling theory, the transmitting system can transmit energy at the maximum power instead, resulting in energy loss and system damage. 2. The wireless charger structure has poor expansibility, one charger can only charge the single unmanned aerial vehicle device to be charged, and the charger is not suitable for use scenes such as small unmanned aerial vehicles and the like which need large-scale charging.

In summary, the existing unmanned aerial vehicle charging and launching system still has further improvement space.

Disclosure of Invention

The invention mainly aims to provide a multi-channel wireless charging transmitting system suitable for a small unmanned aerial vehicle, which is improved aiming at the prior art, further improves the efficiency and expands the maximum capacity of a receiving system.

The specific technical scheme of the invention is as follows:

a multipath wireless charging and transmitting system for a small unmanned aerial vehicle is structurally provided with a power supply management circuit 1, a control time sequence generating circuit 8, a reference voltage circuit 9 and an output matrix 10; the output end of the power management circuit 1 provides direct current power for all the modules, and the input end of the power management circuit is connected with commercial power; the reference voltage circuit 9 provides reference voltage for each output channel circuit in the output matrix 10, and the control timing sequence generating circuit 8 provides PWM signals for each output channel circuit in the output matrix 10; the output matrix 10 comprises n output channels, n is an integer of 2-8, the n output channels have the same circuit structure, each output channel comprises a voltage regulating circuit 2, an energy transmitting circuit 3, a current detecting amplifying circuit 4, a signal shaping circuit 5, an output automatic control circuit 6 and a voltage detecting circuit 7, wherein the output end of the voltage regulating circuit 2 is connected with the input end of the energy transmitting circuit 3 and the input end of the output automatic control circuit 6, the output end of the energy transmitting circuit 3 is connected with the input end of the current detecting amplifying circuit 4, the output end of the current detecting amplifying circuit 4 is connected with the input end of the signal shaping circuit 5, the input end of the voltage regulating circuit 2 is respectively connected with the output end of the signal shaping circuit 5 and the output end of a reference voltage circuit 9, the output end of the reference voltage circuit 9 is also connected with the input end of the output automatic control circuit 6, the output end of the output automatic control circuit 6 is connected with the bridge driving circuit 7, the output end of the bridge driving circuit 7 is connected with the input end of the energy emission circuit 3, and the bridge driving circuit 7 is controlled by the output end of the control time sequence generation circuit 8;

the power management circuit 1 is structurally characterized in that the input end of a transformer T1 is connected with commercial power, and the three output ends are respectively connected with the input ends of a rectifier bridge D101 and a rectifier bridge D102; the cathode of the output end of the rectifier bridge D101 is connected with the cathode of the electrolytic capacitor C101 and grounded, and the anode of the output end of the rectifier bridge D101 is connected with the anode of the electrolytic capacitor C101 and serves as the first output end of the power management circuit 1, which is marked as a port HV _ out, and supplies power to the voltage regulating circuit 2; the negative electrode of the output end of the rectifier bridge D102 is connected with the negative electrode of the electrolytic capacitor C102 and grounded, the positive electrode of the output end of the rectifier bridge D102 is connected with the positive electrode of the electrolytic capacitor C102 and connected with the port 1 of the chip LM7812, and also connected with one end of the capacitor C103, the other end of the capacitor C103 is connected with the port 2 of the chip LM7812 and grounded, one end of the capacitor C14 is grounded, the other end of the capacitor C592 is connected with the port 3 of the chip LM7812 and connected with one end of the resistor R2, and is used as the second output end of the power management circuit 1 and recorded as the port P _ out1 to provide power VDD for each module in the system, the other end of the resistor R2 is connected with one end of the resistor R1 and the non-inverting input end of the operational amplifier U1A, the other end of the resistor R1 is grounded, the inverting input end of the operational amplifier U1A is connected with the output end, and is used as the third output;

the voltage regulating circuit 2 is structurally characterized in that a non-inverting input end of an operational amplifier U3.1 is connected with one end of a resistor R8 and one end of a resistor R9, an inverting input end of the operational amplifier U3.1 is connected with one end of a capacitor C3, one end of a resistor R7 and an inverting input end of an operational amplifier U4.2, the other end of the resistor R7 is connected with an output end of the operational amplifier U3.1 and the other end of a resistor R9, and the other end of the capacitor C3 is connected with the other end of the resistor R8 and connected with a power supply VDD/2 in parallel; the output end of the operational amplifier U4.2 is connected with the grid of the field effect transistor Q2, the positive power supply end of the operational amplifier U4.2 is connected with a power supply VDD, the negative power supply end of the operational amplifier U4.2 is grounded, the source electrode of the field effect transistor Q2 is connected with the cathode of the diode D2 and one end of the inductor L2, and the drain electrode of the field effect transistor Q2 is used as the voltage input end of the voltage regulating circuit 2, is recorded as a port HV _ in, and is connected with a port HV _ out of the power supply management circuit 1; the other end of the inductor L2 is connected to the anode of the electrolytic capacitor C4, and serves as a compensation output end of the voltage regulation circuit 2, which is recorded as a port ADV _ out and is connected to a port ADV _ in1 of the energy emission circuit 3 and a port ADV _ in2 of the output automatic control circuit 6, respectively; the cathode of the electrolytic capacitor C4 is connected with the anode of the diode D2 and is connected with the ground; the non-inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R12 and one end of a resistor R13, the inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R10 and one end of a resistor R11, the other end of the resistor R10 is connected with the output end of the operational amplifier U5.1 and the non-inverting input end of an operational amplifier U4.2, the other end of the resistor R11 serves as the reference input end of a voltage regulating circuit, is marked as a port Vref _ in1, and is connected with a port Vref _ out1 of a reference voltage circuit 9; the other end of the resistor R12 is used as a sampling input end of the voltage regulating circuit, is recorded as a port ReshapeV _ in, and is connected with a port ReshapeV _ out of the signal shaping circuit 5; the other end of the resistor R13 is connected with a power supply VDD/2;

the energy emission circuit 3 has a structure that a gate of a field effect transistor Q3 is used as a first driving end of the energy emission circuit 3, is marked as a port Drv _ in1, and is connected with a port Drv _ out1 of the bridge driving circuit 7; the source of the fet Q3 is connected to the drain of the fet Q4 and one end of the capacitor C5, respectively, and serves as the second driving end of the energy emitting circuit 3, which is denoted as port Drv _ in2, and is connected to the port Drv _ out2 of the bridge driving circuit 7; the gate of the field effect transistor Q4 is connected to one end of the R14, and serves as a third driving end of the energy emitting circuit 3, which is denoted as a port Drv _ in3, and is connected to a port Drv _ out3 of the bridge driving circuit 7; the gate of the field effect transistor Q5, which is used as the fourth driving terminal of the energy emitting circuit 3 and is denoted as a port Drv _ in4, is connected to the port Drv _ out4 of the bridge driving circuit 7; the source of the field-effect transistor Q5 is connected to the drain of the field-effect transistor Q6 and one end of the inductor L3, respectively, and serves as the fifth driving end of the energy emission circuit 3, which is denoted as a port Drv _ in5, and is connected to the port Drv _ out5 of the bridge driving circuit 7, and the other end of the inductor L3 is connected to the other end of the capacitor C5; the gate of the field effect transistor Q6 is connected to one end of the resistor R15, and serves as the sixth driving end of the energy emitting circuit 3, which is denoted as a port Drv _ in6, and is connected to a port Drv _ out6 of the bridge driving circuit 7; the other end of the resistor R15 is connected to the other end of the resistor R14, the source of the fet Q4, and the source of the fet Q6, respectively, and serves as a sampling output terminal of the energy emitting circuit 3, which is denoted as a port SampV _ out, and is connected to a port SampV _ in of the current detecting and amplifying circuit 4; the drain of the field effect transistor Q3 is connected to the drain of the field effect transistor Q5, and serves as a compensation input end of the energy emission circuit 3, which is marked as a port ADV _ in1 and connected to a port ADV _ out of the voltage regulation circuit 2;

the current detection amplifying circuit 4 is structurally characterized in that a non-inverting input end of an operational amplifier U7.2 is connected with one end of a resistor RS1, is used as a sampling input end of the current detection amplifying circuit 4 and is marked as a port SampV _ in to be connected with a port SampV _ out of the energy transmitting circuit 3, an inverting input end of the operational amplifier U7.2 is respectively connected with one end of a resistor R16, one end of a resistor R17, one end of a variable resistor W2 and a movable contact of the variable resistor W2, an output end of the operational amplifier U7.2 is connected with the other end of a resistor R16 and is used as an amplifying output end of the current detection amplifying circuit 4 and is marked as a port AmpV _ out to be connected with a port AmpV _ in of the signal shaping circuit; the other end of the variable resistor W2 is respectively connected with one end of a resistor R18, one end of a resistor R19 and the inverting input end of an operational amplifier U6.1, the other end of the resistor R17 is respectively connected with the other end of the resistor R18 and the output end of the operational amplifier U6.1, the other end of the resistor R19 is connected with a power supply VDD/2, the non-inverting input end of the operational amplifier U6.1 is respectively connected with the negative power supply end of the operational amplifier U6.1 and the other end of the resistor RS1 and is grounded, and the positive power supply end of the operational amplifier U6.1 is connected with the;

the signal shaping circuit 5 has a structure that a positive power terminal of an operational amplifier U8.2 is connected with a power supply VDD, a negative power terminal of the operational amplifier U8.2 is grounded, an inverting input terminal of the operational amplifier U8.2 is respectively connected with one end of a resistor R21 and one end of a capacitor C7, a non-inverting input terminal of the operational amplifier U8.2 is connected with one end of a capacitor C6 and is grounded, the other end of the capacitor C6 is respectively connected with one end of a resistor R20, the other end of a resistor R21 and one end of a resistor R22, the other end of the resistor R20 is used as a voltage input terminal of the signal shaping circuit 5, is recorded as a port AmpV _ in and is connected with a port AmpV _ out of the; the other end of the resistor R22 is respectively connected with the other end of the capacitor C7, one end of the resistor R23 and the output end of the operational amplifier U8.2; the inverting input end of the operational amplifier U9.1 is respectively connected with one end of a resistor R24 and one end of a capacitor C9, the non-inverting input end of the operational amplifier U9.1 is connected with one end of a capacitor C8 and grounded, and the other end of the capacitor C8 is respectively connected with one end of a resistor R25, the other end of a resistor R24 and the other end of a resistor R23; the other end of the resistor R25 is connected with the other end of the capacitor C9 and the output end of the operational amplifier U9.1 respectively, is used as the shaping output end of the signal shaping circuit 5, is recorded as a port ReshapeV _ out, and is connected with a port ReshapeV _ in of the voltage regulating circuit 2;

the structure of the output automatic control circuit 6 is that the positive power terminal of the operational amplifier U10.2 is connected to the power supply VDD, the negative power terminal of the operational amplifier U10.2 is grounded, the inverting input terminal of the operational amplifier U10.2 is used as the reference input terminal of the output automatic control circuit 6 and is marked as the port Vref _ in2, and is connected to the port Vref _ out2 of the reference voltage circuit 9, the non-inverting input terminal of the operational amplifier U10.2 is connected to the cathode of the zener diode D3 and one end of the resistor R26, the anode of the zener diode D5 is grounded, the other end of the resistor R26 is used as the compensation input terminal of the output automatic control circuit 6 and is marked as the port ADV _ in2, and is connected to the port ADV _ out of the voltage regulating; the output end of the operational amplifier U10.2 is connected with the base of a triode Q7, the collector of a triode Q7 is connected with a power supply VDD, the emitters are respectively connected with one end of a resistor R27, one end of a resistor R28 and the emitter of a triode Q8, the other end of a resistor R27 is connected with one end of a capacitor C10 and the input end of an inverter U13.4, the other end of the resistor R28 and the other end of the capacitor C10 are grounded, the output end of the inverter U13.4 is connected with a clock signal end Cp of a D flip-flop U11.1, a trigger signal end D of the D flip-flop U11.1 is respectively connected with a clear end Cd and one end of a capacitor C11 and grounded, the other end of the capacitor C11 is respectively connected with the anode of a diode D4, one end of the resistor R29 and a preset end Sd of the D flip-flop U11.1, the cathode of a diode D4 is not connected with the other end of the resistor R29 and the opposite phase output end Q of the D flip-flop U11.1, the same phase output end Q of the D, the output end of the inverter U15.2 is used as the control output end of the output automatic control circuit 6, is recorded as a port CtrlV _ out, and is connected with a port CtrlV _ in of the bridge drive circuit 7; a trigger signal end D of the D trigger U12.2 is respectively connected with a zero clearing end Cd of the D trigger U12.2 and one end of a capacitor C12, the other end of the capacitor C12 is connected with an anode of a diode D5, one end of a resistor R30 and a preset end Sd of the D trigger U12.2, a cathode of the diode D5 is respectively connected with the other end of a resistor R30 and an inverted phase output end Q of the D trigger U12.2, the same phase output end Q of the D trigger U12.2 is connected with an input end of an inverter U14.1, an output end of the inverter U14.1 is connected with a base electrode of a triode Q8, and a collector electrode of the triode Q8 is connected with a power supply VDD;

the bridge driving circuit 7 has a structure that a voltage input terminal VCC of a bridge driver U16 and one end of a capacitor C13 are connected to a power supply VDD, the other end of a capacitor C13 and a COM terminal of a bridge driver U16 are grounded, a high level input terminal HIN of a bridge driver U16 is connected to a drain of a fet Q9 and a low level input terminal LIN of a bridge driver U17, respectively, and serves as a first control input terminal of the bridge driving circuit 7, which is denoted as a port TsV _ in1, and is connected to a port TsV _ out1 of a control timing generating circuit 8, a VB terminal of the bridge driver U16 is connected to a cathode of a diode D6 and one end of a capacitor C15, a VS terminal of a bridge driver U16 is connected to the other end of a capacitor C15 and one end of a resistor R33, and serves as a second output terminal of the bridge driving circuit 7, which is denoted as a port Drv _ out2, and is connected to a port Drv _ in2 of the energy emitting circuit 3, and a high level output terminal HO of, the other end of the resistor R32 is connected to the other end of the resistor R33, and serves as a first output end of the bridge driving circuit 7, which is denoted as a port Drv _ out1, and is connected to a port Drv _ in1 of the energy transmitting circuit 3, the anode of the diode D6 is connected to one end of a resistor R31, the other end of the resistor R31 is connected to the power supply VDD, the low level output end LO of the bridge driver U16 is connected to one end of the resistor R34, and the other end of the resistor R34 serves as a third output end of the bridge driving circuit 7, which is denoted as a port Drv _ out3, and is connected to a port Drv _ in3 of the energy transmitting circuit; a voltage input terminal VCC of the bridge driver U17 and one end of a capacitor C14 are connected to the power supply VDD, the other end of the capacitor C14 and a COM terminal of the bridge driver U17 are grounded, a high level input terminal HIN of the bridge driver U17 is connected to the drain of the fet Q10 and the low level input terminal LIN of the bridge driver U16, respectively, and serves as a second control input terminal of the bridge driver circuit 7, which is denoted as a port TsV _ in2, and is connected to a port TsV _ out2 of the control timing generation circuit 8, a VB terminal of the bridge driver U17 is connected to the cathode of the diode D7 and one end of the capacitor C16, a VS terminal of the bridge driver U17 is connected to the other end of the capacitor C16 and one end of the resistor R36, and serves as a fifth output terminal of the bridge driver circuit 7, which is denoted as a port Drv _ out5, and is connected to a port Drv _ in 42 of the energy emission circuit 3, a high level output terminal of the bridge driver, the other end of the resistor R37 is connected to the other end of the resistor R36, and serves as a fourth output end of the bridge driving circuit 7, which is denoted as a port Drv _ out4, and is connected to a port Drv _ in4 of the energy transmitting circuit 3, the anode of the diode D7 is connected to one end of the resistor R38, the other end of the resistor R38 is connected to the power supply VDD, the low level output end LO of the bridge driver U17 is connected to one end of the resistor R35, and the other end of the resistor R35 serves as a sixth output end of the bridge driving circuit 7, which is denoted as a port Drv _ out6, and is connected to a port Drv _ in6 of the energy transmitting circuit; the source electrode of the field effect transistor Q9 and the source electrode of the field effect transistor Q10 are grounded, the grid electrode of the field effect transistor Q9 is connected with the grid electrode of the field effect transistor Q10 and serves as the third control input end of the bridge driving circuit 7, is recorded as a port CtrlV _ in and is connected with a port CtrlV-out of the output automatic control circuit 6;

the control timing generation circuit 8 is structurally characterized in that a ground end GND of a 555 timer U27 is grounded and is respectively connected with one end of a capacitor C17, one end of a capacitor C18 and one end of a capacitor C19, the other end of the capacitor C18 is connected with a control end CVOLT of a 555 timer U27, a trigger input end TRIG of the 555 timer U27 is respectively connected with a threshold end THR of the 555 timer U27, one end of an R40 and the other end of a C17, the other end of the R40 is respectively connected with one end of an R39 and a discharge end DIS of the 555 timer U27, and the other end of the R39 is respectively connected with a reset end RST of the 555 timer U27 and a voltage input end + VCC and is connected with a power supply VDD; an output end OUT of the 555 timer U27 is respectively connected with an input end of the inverter 25.6 and an input end of the inverter 26.5, an output end of the inverter 26.5 is used as a first control output end of the control timing sequence generating circuit 8, is marked as a port TsV _ OUT1, and is connected with the bridge driving circuit 7; the output end of the inverter 25.6 is connected to one end of a resistor R41, the other end of the resistor R41 is connected to the other end of a capacitor C19 and the input end of the inverter U20.6, the output end of the inverter U20.6 is connected to the clock signal end Cp of the D flip-flop U18.1, the preset end Sd of the D flip-flop U18.1 is connected to one end of a capacitor C20, one end of a resistor R42 and the anode of a diode D8, the other end of the capacitor C20 is connected to the trigger signal end D of the D flip-flop U18.1 and the clear end Cd of the D flip-flop U18.1, the other end of the resistor R42 is not connected to the cathode of a diode D8 and the inverted phase output end Q of the D flip-flop U18.1, the in-phase output end Q of the D flip-flop U18.1 is connected to the input end of the inverter 19.3, the output end of the inverter U19.3 is used as a second control output end of the timing generation circuit 8;

the reference voltage circuit 9 has a structure that an input end IN of a reference voltage source U24 is connected with one end of a capacitor C21 and connected with a power supply VDD IN parallel, an NR end of a reference voltage source U24 is connected with one end of a capacitor C22, a ground end GND of a reference voltage source U24 is respectively connected with the other end of a capacitor C21, the other end of a capacitor C22, one end of a capacitor C23 and one end of a resistor R43 and connected with ground, the other end of the capacitor C23 is respectively connected with an output end OUT of a reference voltage source U24, a TRIM end of a reference voltage source U24, an I.C./3 end of the reference voltage source U24 and a non-inverting input end of an operational amplifier U21.1, an inverting input end of the operational amplifier U21.1 is respectively connected with the other end of a resistor R43, one end of a capacitor C24 and one end of a resistor R44, the other end of the capacitor C24 is respectively connected with an output end of an operational amplifier U21.1, one end of a variable resistor W3, one end of, the output end of the operational amplifier U22.2 is fed back to the inverting input end, and serves as the first reference output end of the reference voltage circuit 9, which is marked as a port Vref _ out1, and is connected with a port Vref _ in1 of the voltage regulating circuit 2; the movable contact of the variable resistor W4 is connected with the non-inverting input end of the operational amplifier U23.1, the output end of the operational amplifier U23.1 is fed back to the inverting input end, and is used as the second reference output end of the reference voltage circuit 9, which is marked as a port Vref _ out2 and connected with a port Vref _ in2 of the output automatic control circuit 6; the other end of the variable resistor W3 and the other end of the variable resistor W4 are grounded.

In the energy transmitting circuit 3, the inductance L3 is preferably 10 mH; the capacitance C5 is preferably 100 pF; the resistors R14, R15 are preferably 18k Ω.

In the current detection amplifying circuit 4, the resistor has the preferred value: the resistances R16, R17, R18, and R19 were 10k Ω, the resistance RS1 was 0.1 Ω, and the variable resistance W2 was 100k Ω.

In the output automatic control circuit 6, the preferred value of the capacitor is as follows: the capacitance C10 is 200nF, the capacitance C11 is 1 muF, and the capacitance C12 is 100 nF; the optimized value of the resistance is as follows: the resistance R26 is 20k Ω, the resistance R27 is 10k Ω, the resistance R28 is 2k Ω, the resistance R29 is 1M Ω, and the resistance R30 is 100k Ω.

In the control timing generation circuit 8, the capacitance preferred value is: the capacitance C17 is 100 muF, and the capacitances C18, C19 and C20 are 4.3 nF; the optimized value of the resistance is as follows: the resistance R39 is 700 Ω, the resistance R40 is 3.1k Ω, the resistance R41 is 250 Ω, and the resistance R42 is 8.2k Ω.

Has the advantages that:

1. the invention can wirelessly charge a plurality of unmanned aerial vehicles at the same time, and is convenient to use.

2. The invention enables the energy emission module in the output channel to always work at the optimal voltage through the voltage regulating circuit, thereby improving the efficiency of the emission module.

3. The invention enables the energy emission module to automatically power off when in no load and automatically start when in load through the output automatic control circuit, thereby improving the reliability and convenience.

Drawings

Fig. 1 is a block diagram of the overall architecture of the present invention.

FIG. 2 is a block diagram of a single output channel circuit connection.

Fig. 3 is a schematic circuit diagram of a power management circuit.

Fig. 4 is a schematic circuit diagram of a voltage regulating circuit.

Fig. 5 is a schematic circuit diagram of an energy transmission circuit.

Fig. 6 is a schematic circuit diagram of the current detection amplifying circuit.

Fig. 7 is a schematic circuit diagram of a signal shaping circuit.

Fig. 8 is a schematic circuit diagram of the output automatic control.

Fig. 9 is a schematic circuit diagram of the bridge driving circuit.

Fig. 10 is a schematic circuit diagram of a control timing generation circuit.

Fig. 11 is a schematic circuit diagram of the reference voltage circuit.

Detailed Description

The following further describes embodiments of the present invention with reference to the drawings.

As shown in fig. 1, the multi-path wireless charging and transmitting system for the small unmanned aerial vehicle of the invention comprises a power management circuit 1, a control timing generation circuit 8, a reference voltage circuit 9 and an output matrix 10. The output matrix 10 comprises a plurality of circuit output channels (2-8 can be selected according to actual requirements). The power management circuit 1 converts the 220V alternating current of the commercial power into a direct current stabilized power supply to provide required voltage for other modules; the reference voltage circuit 9 provides a reference voltage for each output channel circuit in the output matrix 10, and the control timing generation circuit 8 provides a PWM signal for each output channel circuit in the output matrix 10.

EXAMPLE 2 construction of the output channels

Each output channel in the output matrix 10 in the system has the same structure, each output channel can wirelessly charge an unmanned aerial vehicle, fig. 2 shows a structural block diagram of a single output channel, and the structure of the single output channel includes a voltage regulating circuit 2, an energy transmitting circuit 3, a current detection amplifying circuit 4, a signal shaping circuit 5, an output automatic control circuit 6, and a voltage detection circuit 7. The output end of the voltage regulating circuit 2 is connected with the input end of the energy transmitting circuit 3 and the input end of the output automatic control circuit 6, the output end of the energy transmitting circuit 3 is connected with the input end of the current detection amplifying circuit 4, the output end of the current detection amplifying circuit 4 is connected with the input end of the signal shaping circuit 5, the input end of the voltage regulating circuit 2 is respectively connected with the output end of the signal shaping circuit 5 and the output end of the reference voltage circuit 9, the output end of the reference voltage circuit 9 is also connected with the input end of the output automatic control circuit 6, the output end of the output automatic control circuit 6 is connected with the bridge driving circuit 7, the output end of the bridge driving circuit 7 is connected with the input end of the energy transmitting circuit 3, and the bridge driving circuit 7 is controlled by the output end of the control.

Embodiment 3 Power management Circuit

The structure of the power management circuit 1 is shown in fig. 3: the input end of the transformer T1 is connected with the commercial power, and the three output ends are respectively connected with the input ends of the rectifier bridge D101 and the rectifier bridge D102; the cathode of the output end of the rectifier bridge D101 is connected with the cathode of the electrolytic capacitor C101 and grounded, and the anode of the output end of the rectifier bridge D101 is connected with the anode of the electrolytic capacitor C101 and serves as the first output end of the power management circuit 1, which is marked as a port HV _ out, and supplies power to the voltage regulating circuit 2; the negative electrode of the output end of the rectifier bridge D102 is connected with the negative electrode of the electrolytic capacitor C102 and grounded, the positive electrode of the output end of the rectifier bridge D102 is connected with the positive electrode of the electrolytic capacitor C102 and connected with the port 1 of the chip LM7812, and also connected with one end of the capacitor C103, the other end of the capacitor C103 is connected with the port 2 of the chip LM7812 and grounded, one end of the capacitor C14 is grounded, the other end of the capacitor C592 is connected with the port 3 of the chip LM7812 and connected with one end of the resistor R2, and is used as the second output end of the power management circuit 1 and recorded as the port P _ out1 to provide power VDD for each module in the system, the other end of the resistor R2 is connected with one end of the resistor R1 and the non-inverting input end of the operational amplifier U1A, the other end of the resistor R1 is grounded, the inverting input end of the operational amplifier U1A is connected with the output end, and is used as the third output.

The power management circuit 1 converts the 220V commercial power into 3 different dc voltages to be provided to each module of the system: a 48V voltage for providing high power to the voltage regulating circuit, and is output through a port HV _ out; VDD for providing +5V power supply for analog circuits in each module is output through a port P _ out 1; VDD/2, which is used to provide 2.5V power to each block, is output through port P _ out 2.

Embodiment 4 Voltage regulating Circuit

The structure of the voltage regulating circuit 2 is shown in fig. 4: the non-inverting input end of the operational amplifier U3.1 is connected with one end of a resistor R8 and one end of a resistor R9, the inverting input end of the operational amplifier U3.1 is connected with one end of a capacitor C3, one end of a resistor R7 and the inverting input end of an operational amplifier U4.2, the other end of the resistor R7 is connected with the output end of the operational amplifier U3.1 and the other end of a resistor R9, and the other end of the capacitor C3 is connected with the other end of the resistor R8 and connected with a power supply VDD/2 in parallel; the output end of the operational amplifier U4.2 is connected with the grid of the field effect transistor Q2, the positive power supply end of the operational amplifier U4.2 is connected with a power supply VDD, the negative power supply end of the operational amplifier U4.2 is grounded, the source electrode of the field effect transistor Q2 is connected with the cathode of the diode D2 and one end of the inductor L2, and the drain electrode of the field effect transistor Q2 is used as the voltage input end of the voltage regulating circuit 2, is recorded as a port HV _ in, and is connected with a port HV _ out of the power supply management circuit 1; the other end of the inductor L2 is connected to the anode of the electrolytic capacitor C4, and serves as a compensation output end of the voltage regulation circuit 2, which is recorded as a port ADV _ out and is connected to a port ADV _ in1 of the energy emission circuit 3 and a port ADV _ in2 of the output automatic control circuit 6, respectively; the cathode of the electrolytic capacitor C4 is connected with the anode of the diode D2 and is connected with the ground; the non-inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R12 and one end of a resistor R13, the inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R10 and one end of a resistor R11, the other end of the resistor R10 is connected with the output end of the operational amplifier U5.1 and the non-inverting input end of an operational amplifier U4.2, the other end of the resistor R11 serves as the reference input end of a voltage regulating circuit, is marked as a port Vref _ in1, and is connected with a port Vref _ out1 of a reference voltage circuit 9; the other end of the resistor R12 is used as a sampling input end of the voltage regulating circuit, is recorded as a port ReshapeV _ in, and is connected with a port ReshapeV _ out of the signal shaping circuit 5; the other end of the resistor R13 is connected with a power supply VDD/2.

The voltage regulating circuit 2 compares the current value (reflecting the size of the effective load and shaped by the signal shaping circuit 5) detected by the current detection amplifying circuit 6 with the reference value set by the reference voltage circuit 9 for difference, and then converts the 48V voltage (provided by the power management circuit 1) received by the HV-in port into a voltage matched with the actual load according to the difference value, and outputs the voltage to the energy emission bridge 3 through the port ADV-out as the working voltage of the energy emission bridge 3, so that the energy emission bridge 3 works in a stable current state.

EXAMPLE 5 energy emitting Circuit

The structure of the energy transmitting circuit 3 is shown in fig. 5: the gate of the field effect transistor Q3 is used as the first driving terminal of the energy emission circuit 3, and is denoted as a port Drv _ in1, and is connected with a port Drv _ out1 of the bridge driving circuit 7; the source of the fet Q3 is connected to the drain of the fet Q4 and one end of the capacitor C5, respectively, and serves as the second driving end of the energy emitting circuit 3, which is denoted as port Drv _ in2, and is connected to the port Drv _ out2 of the bridge driving circuit 7; the gate of the field effect transistor Q4 is connected to one end of the R14, and serves as a third driving end of the energy emitting circuit 3, which is denoted as a port Drv _ in3, and is connected to a port Drv _ out3 of the bridge driving circuit 7; the gate of the field effect transistor Q5, which is used as the fourth driving terminal of the energy emitting circuit 3 and is denoted as a port Drv _ in4, is connected to the port Drv _ out4 of the bridge driving circuit 7; the source of the field-effect transistor Q5 is connected to the drain of the field-effect transistor Q6 and one end of the inductor L3, respectively, and serves as the fifth driving end of the energy emission circuit 3, which is denoted as a port Drv _ in5, and is connected to the port Drv _ out5 of the bridge driving circuit 7, and the other end of the inductor L3 is connected to the other end of the capacitor C5; the gate of the field effect transistor Q6 is connected to one end of the resistor R15, and serves as the sixth driving end of the energy emitting circuit 3, which is denoted as a port Drv _ in6, and is connected to a port Drv _ out6 of the bridge driving circuit 7; the other end of the resistor R15 is connected to the other end of the resistor R14, the source of the fet Q4, and the source of the fet Q6, respectively, and serves as a sampling output terminal of the energy emitting circuit 3, which is denoted as a port SampV _ out, and is connected to a port SampV _ in of the current detecting and amplifying circuit 4; the drain of the fet Q3 is connected to the drain of the fet Q5 and serves as a compensation input terminal of the energy emission circuit 3, denoted as port ADV _ in1, which is connected to the port ADV _ out of the voltage regulation circuit 2.

The energy transmitting circuit 3 converts the voltage provided by the voltage regulating circuit 2 into an oscillating sine wave current under the control of the PWM time sequence (50kHz) provided by the control time sequence generating circuit 8, and the oscillating sine wave current flows through the inductor L3 (i.e., the transmitting coil), and the transmitting coil converts the current into a changing magnetic field energy for transmission, and the changing magnetic field energy is received by the receiving coil at the receiving end of the unmanned aerial vehicle, so that the wireless charging of the unmanned aerial vehicle is realized.

Embodiment 6 Current detection amplifying Circuit

The structure of the current detection amplifying circuit 4 is shown in fig. 6: the non-inverting input end of the operational amplifier U7.2 is connected with one end of a resistor RS1, is used as the sampling input end of the current detection amplifying circuit 4 and is recorded as a port SampV _ in, and is connected with the port SampV _ out of the energy transmitting circuit 3, the inverting input end of the operational amplifier U7.2 is respectively connected with one end of a resistor R16, one end of a resistor R17, one end of a variable resistor W2 and a movable contact of a variable resistor W2, the output end of the operational amplifier U7.2 is connected with the other end of a resistor R16 and is used as the amplifying output end of the current detection amplifying circuit 4 and is recorded as a port AmpV _ out, and is connected with a port AmpV _ in of the signal shaping; the other end of the variable resistor W2 is respectively connected with one end of a resistor R18, one end of a resistor R19 and the inverting input end of an operational amplifier U6.1, the other end of the resistor R17 is respectively connected with the other end of the resistor R18 and the output end of the operational amplifier U6.1, the other end of the resistor R19 is connected with a power supply VDD/2, the non-inverting input end of the operational amplifier U6.1 is respectively connected with the negative power supply end of the operational amplifier U6.1 and the other end of the resistor RS1 and is connected with the ground, and the positive power supply end of the operational amplifier U6.1 is.

The current detection amplifying circuit 4 samples and amplifies the working current of the energy transmitting circuit through the sampling resistor Rs and inputs the amplified working current to the signal shaping circuit 5.

Embodiment 7 Signal shaping Circuit

The structure of the signal shaping circuit 5 is shown in fig. 7: the signal shaping circuit 5 has a structure that a positive power terminal of an operational amplifier U8.2 is connected with a power supply VDD, a negative power terminal of the operational amplifier U8.2 is grounded, an inverting input terminal of the operational amplifier U8.2 is respectively connected with one end of a resistor R21 and one end of a capacitor C7, a non-inverting input terminal of the operational amplifier U8.2 is connected with one end of a capacitor C6 and is grounded, the other end of the capacitor C6 is respectively connected with one end of a resistor R20, the other end of a resistor R21 and one end of a resistor R22, the other end of the resistor R20 is used as a voltage input terminal of the signal shaping circuit 5, is recorded as a port AmpV _ in and is connected with a port AmpV _ out of the; the other end of the resistor R22 is respectively connected with the other end of the capacitor C7, one end of the resistor R23 and the output end of the operational amplifier U8.2; the inverting input end of the operational amplifier U9.1 is respectively connected with one end of a resistor R24 and one end of a capacitor C9, the non-inverting input end of the operational amplifier U9.1 is connected with one end of a capacitor C8 and grounded, and the other end of the capacitor C8 is respectively connected with one end of a resistor R25, the other end of a resistor R24 and the other end of a resistor R23; the other end of the resistor R25 is connected to the other end of the capacitor C9 and the output of the operational amplifier U9.1, respectively, and serves as the shaping output of the signal shaping circuit 5, which is denoted as port ReshapeV _ out, and is connected to the port ReshapeV _ in of the voltage regulating circuit 2.

The signal shaping circuit 5 shapes the signal output from the current detection amplifier circuit 4 and outputs the shaped signal to the voltage regulator circuit 2 to be compared with the reference voltage.

Embodiment 8 output automatic control Circuit

The structure of the output automatic control circuit 6 is shown in fig. 8: the positive power supply end of the operational amplifier U10.2 is connected with a power supply VDD, the negative power supply end of the operational amplifier U10.2 is grounded, the inverting input end of the operational amplifier U10.2 is used as the reference input end of the output automatic control circuit 6 and is recorded as a port Vref _ in2 to be connected with a port Vref _ out2 of a reference voltage circuit 9, the non-inverting input end of the operational amplifier U10.2 is connected with the cathode of a voltage stabilizing diode D3 and one end of a resistor R26, the anode of the voltage stabilizing diode D5 is grounded, the other end of the resistor R26 is used as the compensation input end of the output automatic control circuit 6 and is recorded as a port ADV _ in2 to be connected with a port ADV _ out of; the output end of the operational amplifier U10.2 is connected with the base of a triode Q7, the collector of a triode Q7 is connected with a power supply VDD, the emitters are respectively connected with one end of a resistor R27, one end of a resistor R28 and the emitter of a triode Q8, the other end of a resistor R27 is connected with one end of a capacitor C10 and the input end of an inverter U13.4, the other end of the resistor R28 and the other end of the capacitor C10 are grounded, the output end of the inverter U13.4 is connected with a clock signal end Cp of a D flip-flop U11.1, a trigger signal end D of the D flip-flop U11.1 is respectively connected with a clear end Cd and one end of a capacitor C11 and grounded, the other end of the capacitor C11 is respectively connected with the anode of a diode D4, one end of the resistor R29 and a preset end Sd of the D flip-flop U11.1, the cathode of a diode D4 is not connected with the other end of the resistor R29 and the opposite phase output end Q of the D flip-flop U11.1, the same phase output end Q of the D, the output end of the inverter U15.2 is used as the control output end of the output automatic control circuit 6, is recorded as a port CtrlV _ out, and is connected with a port CtrlV _ in of the bridge drive circuit 7; the trigger signal end D of the D trigger U12.2 is respectively connected with a clear end Cd of the D trigger U12.2 and one end of a capacitor C12, the other end of the capacitor C12 is connected with the anode of a diode D5, one end of a resistor R30 and a preset end Sd of the D trigger U12.2, the cathode of the diode D5 is respectively connected with the other end of a resistor R30 and the reverse phase output end Q of the D trigger U12.2, the same phase output end Q of the D trigger U12.2 is connected with the input end of an inverter U14.1, the output end of the inverter U14.1 is connected with the base electrode of a triode Q8, and the collector electrode of the triode Q8 is connected with a power supply VDD.

As can be seen from the description of embodiment 4, when the load is gradually decreased, the voltage output by the voltage regulating circuit 2 is gradually decreased, so that when the load is completely disappeared (i.e. no drone is charged or the voltage is fully charged), the voltage regulating circuit 2 outputs a very small voltage, and therefore when the voltage detected by the voltage detecting circuit is smaller than a certain preset value (set by the reference voltage circuit 9), it is determined that the system is in the idle state, and the port ctrl v-out outputs a high level to turn on the field effect transistors Q9 and Q10 in the bridge driving circuit 7, so that the PWM signals (provided by the control timing generating circuit 8) received by the ports TsV-in1 and TsV-in2 are locked to 0, and the bridge driving circuit 7 stops working, and further the energy emission bridge 3 stops emitting energy, so that the system enters the standby state, thereby effectively reducing the energy loss. The output automatic control circuit 6 also has an automatic starting function, a delay inverting structure composed of a D trigger U11.1, an inverter U12.2 and the like generates a trigger signal at a certain time interval during the system standby, so that the system tries to power on and detect, if a load is detected, the normal emission state of the circuit is maintained, if the system is still idle after the power on attempt, the system is controlled to enter a power off state again, and the process is continuously repeated in the standby process. The duration of the power-on detection is determined by the resistor R30 and the capacitor C12, the sleeping time between two attempts is determined by the resistor R29 and the capacitor C11, and since R29 is far larger than R30 and C11 is far larger than C12, the power consumption consumed by the system in the standby process is greatly reduced.

EXAMPLE 9 bridge drive Circuit

The structure of the bridge driving circuit 7 is shown in fig. 9: a voltage input terminal VCC of the bridge driver U16 and one end of a capacitor C13 are connected to the power supply VDD, the other end of the capacitor C13 and a COM terminal of the bridge driver U16 are grounded, a high level input terminal HIN of the bridge driver U16 is connected to the drain of the fet Q9 and the low level input terminal LIN of the bridge driver U17, respectively, and serves as a first control input terminal of the bridge driver circuit 7, which is denoted as a port TsV _ in1, and a port TsV _ out1 of the control timing generation circuit 8, a VB terminal of the bridge driver U16 is connected to the cathode of the diode D6 and one end of the capacitor C15, respectively, a VS terminal of the bridge driver U16 is connected to the other end of the capacitor C15 and one end of the resistor R33, and serves as a second output terminal of the bridge driver circuit 7, which is denoted as a port Drv _ out2, and is connected to a port Drv _ in 42 of the energy emission circuit 3, a high level output terminal of the bridge driver 46, the other end of the resistor R32 is connected to the other end of the resistor R33, and serves as a first output end of the bridge driving circuit 7, which is denoted as a port Drv _ out1, and is connected to a port Drv _ in1 of the energy transmitting circuit 3, the anode of the diode D6 is connected to one end of a resistor R31, the other end of the resistor R31 is connected to the power supply VDD, the low level output end LO of the bridge driver U16 is connected to one end of the resistor R34, and the other end of the resistor R34 serves as a third output end of the bridge driving circuit 7, which is denoted as a port Drv _ out3, and is connected to a port Drv _ in3 of the energy transmitting circuit; a voltage input terminal VCC of the bridge driver U17 and one end of a capacitor C14 are connected to the power supply VDD, the other end of the capacitor C14 and a COM terminal of the bridge driver U17 are grounded, a high level input terminal HIN of the bridge driver U17 is connected to the drain of the fet Q10 and the low level input terminal LIN of the bridge driver U16, respectively, and serves as a second control input terminal of the bridge driver circuit 7, which is denoted as a port TsV _ in2, and is connected to a port TsV _ out2 of the control timing generation circuit 8, a VB terminal of the bridge driver U17 is connected to the cathode of the diode D7 and one end of the capacitor C16, a VS terminal of the bridge driver U17 is connected to the other end of the capacitor C16 and one end of the resistor R36, and serves as a fifth output terminal of the bridge driver circuit 7, which is denoted as a port Drv _ out5, and is connected to a port Drv _ in 42 of the energy emission circuit 3, a high level output terminal of the bridge driver, the other end of the resistor R37 is connected to the other end of the resistor R36, and serves as a fourth output end of the bridge driving circuit 7, which is denoted as a port Drv _ out4, and is connected to a port Drv _ in4 of the energy transmitting circuit 3, the anode of the diode D7 is connected to one end of the resistor R38, the other end of the resistor R38 is connected to the power supply VDD, the low level output end LO of the bridge driver U17 is connected to one end of the resistor R35, and the other end of the resistor R35 serves as a sixth output end of the bridge driving circuit 7, which is denoted as a port Drv _ out6, and is connected to a port Drv _ in6 of the energy transmitting circuit; the source of the field effect transistor Q9 and the source of the field effect transistor Q10 are grounded, and the gate of the field effect transistor Q9 is connected to the gate of the field effect transistor Q10, serves as the third control input terminal of the bridge driving circuit 7, is denoted as a port ctrl v _ in, and is connected to a port ctrl v-out of the output automatic control circuit 6.

The bridge driving circuit 7 uses the MOS transistor driving chips U16 and U17 to boost the PWM signal output by the control timing generation circuit 8 to a level capable of driving the MOS transistors, so as to drive the MOS transistor bridge composed of Q3, Q4, Q5, and Q6 in the energy emission circuit 3.

Embodiment 10 control timing generating Circuit

The structure of the control timing generation circuit 8 is shown in fig. 10: a grounding end GND of a 555 timer U27 is grounded and is respectively connected with one end of a capacitor C17, one end of a capacitor C18 and one end of a capacitor C19, the other end of the capacitor C18 is connected with a control end CVOLT of a 555 timer U27, a trigger input end TRIG of a 555 timer U27 is respectively connected with a threshold end THR of the 555 timer U27, one end of an R40 and the other end of a C17, the other end of the R40 is respectively connected with one end of an R39 and a discharge end DIS of the 555 timer U27, and the other end of the R39 is respectively connected with a reset end RST of the 555 timer U27 and a voltage input end + VCC and is connected with a power supply VDD; an output end OUT of the 555 timer U27 is respectively connected with an input end of the inverter 25.6 and an input end of the inverter 26.5, an output end of the inverter 26.5 is used as a first control output end of the control timing sequence generating circuit 8, is marked as a port TsV _ OUT1, and is connected with the bridge driving circuit 7; the output end of the inverter 25.6 is connected to one end of a resistor R41, the other end of the resistor R41 is connected to the other end of a capacitor C19 and the input end of the inverter U20.6, the output end of the inverter U20.6 is connected to the clock signal end Cp of the D flip-flop U18.1, the preset end Sd of the D flip-flop U18.1 is connected to one end of a capacitor C20, one end of a resistor R42 and the anode of a diode D8, the other end of the capacitor C20 is connected to the trigger signal end D of the D flip-flop U18.1 and the clear end Cd of the D flip-flop U18.1, the other end of the resistor R42 is not connected to the cathode of a diode D8 and the inverted phase output end Q of the D flip-flop U18.1, the in-phase output end Q of the D flip-flop U18.1 is connected to the input end of the inverter 19.3, and the output end of the inverter U19.3 is used as a second control output end of the timing generator 8.

The control timing generation circuit 8 utilizes a 555 timer and a D trigger to generate two sets of PWM signals which are opposite and have a dead zone (used for protecting field effect transistors driven later), and the PWM signals are used for controlling the energy emission bridge 3 in each output channel to generate high-frequency oscillation signals after the power is boosted by the bridge driving circuit 7.

EXAMPLE 11 reference Voltage Circuit

The structure of the reference voltage circuit 9 is shown in fig. 11: an input end IN of a reference voltage source U24 is connected with one end of a capacitor C21 and connected with a power supply VDD IN parallel, an NR end of the reference voltage source U24 is connected with one end of a capacitor C22, a grounding end GND of a reference voltage source U24 is respectively connected with the other end of a capacitor C21, the other end of a capacitor C22, one end of a capacitor C23 and one end of a resistor R43 and connected with ground, the other end of a capacitor C23 is respectively connected with an output end OUT of the reference voltage source U24, a TRIM end of a reference voltage source U24, an I.C./3 end of the reference voltage source U24 and a non-inverting input end of an operational amplifier U21.1, an inverting input end of the operational amplifier U21.1 is respectively connected with the other end of a resistor R43, one end of a capacitor C24 and one end of a resistor R44, the other end of the capacitor C24 is respectively connected with an output end of the operational amplifier U21.1, one end of a variable resistor W3, one end of, the output end of the operational amplifier U22.2 is fed back to the inverting input end, and serves as the first reference output end of the reference voltage circuit 9, which is marked as a port Vref _ out1, and is connected with a port Vref _ in1 of the voltage regulating circuit 2; the movable contact of the variable resistor W4 is connected with the non-inverting input end of the operational amplifier U23.1, the output end of the operational amplifier U23.1 is fed back to the inverting input end, and is used as the second reference output end of the reference voltage circuit 9, which is marked as a port Vref _ out2 and connected with a port Vref _ in2 of the output automatic control circuit 6; the other end of the variable resistor W3 and the other end of the variable resistor W4 are grounded.

The reference voltage circuit 9 generates two sets of adjustable magnitude reference voltages Vref-out1, Vref-out2 for providing reference voltages for the output automatic control circuit 6 and the voltage regulating circuit 2 in each output channel.

Claims

1. A multipath wireless charging and transmitting system for a small unmanned aerial vehicle is structurally provided with a power supply management circuit (1), a control time sequence generating circuit (8), a reference voltage circuit (9) and an output matrix (10); the output end of the power management circuit (1) provides direct current power for all the modules, and the input end of the power management circuit is connected with commercial power; the reference voltage circuit (9) provides reference voltage for each output channel circuit in the output matrix (10), and the control time sequence generating circuit (8) provides PWM signals for each output channel circuit in the output matrix (10); the device is characterized in that the output matrix (10) comprises n output channels, n is an integer of 2-8, the n output channels have the same circuit structure, each output channel comprises a voltage regulating circuit (2), an energy emitting circuit (3), a current detection amplifying circuit (4), a signal shaping circuit (5), an output automatic control circuit (6) and a voltage detection circuit (7), wherein the output end of the voltage regulating circuit (2) is connected with the input end of the energy emitting circuit (3) and the input end of the output automatic control circuit (6), the output end of the energy emitting circuit (3) is connected with the input end of the current detection amplifying circuit (4), the output end of the current detection amplifying circuit (4) is connected with the input end of the signal shaping circuit (5), the input end of the voltage regulating circuit (2) is respectively connected with the output end of the signal shaping circuit (5) and the output end of a reference voltage circuit (9), the output end of the reference voltage circuit (9) is also connected with the input end of the output automatic control circuit (6), the output end of the output automatic control circuit (6) is connected with the bridge driving circuit (7), the output end of the bridge driving circuit (7) is connected with the input end of the energy emission circuit (3), and the bridge driving circuit (7) is controlled by the output end of the control time sequence generation circuit (8);

the power management circuit (1) is structurally characterized in that the input end of a transformer T1 is connected with commercial power, and the three output ends are respectively connected with the input ends of a rectifier bridge D101 and a rectifier bridge D102; the negative electrode of the output end of the rectifier bridge D101 is connected with the negative electrode of the electrolytic capacitor C101 and is grounded, the positive electrode of the output end of the rectifier bridge D101 is connected with the positive electrode of the electrolytic capacitor C101 and serves as the first output end of the power management circuit (1), and the port is marked as a port HV _ out to supply power to the voltage regulating circuit (2); the negative pole of the output end of the rectifier bridge D102 is connected with the negative pole of the electrolytic capacitor C102 and is grounded, the positive pole of the output end of the rectifier bridge D102 is connected with the positive pole of the electrolytic capacitor C102 and is connected with the port 1 of the chip LM7812 and is also connected with one end of the capacitor C103, the other end of the capacitor C103 is connected with the port 2 of the chip LM7812 and is grounded, one end of the capacitor C14 is grounded, the other end of the capacitor C14 is connected with the port 3 of the chip LM7812, the power supply management circuit is connected with one end of a resistor R2, serves as a second output end of the power supply management circuit (1), is recorded as a port P _ out1, and provides a power supply VDD for each module in the system, the other end of the resistor R2 is connected with one end of a resistor R1 and a non-inverting input end of an operational amplifier U1A, the other end of the resistor R1 is grounded, an inverting input end of the operational amplifier U1A is connected with the output end, serves as a third output end of the power supply management circuit (1), is recorded as a port P _ out2, and provides a power supply VDD/2 for the system;

the voltage regulating circuit (2) is structurally characterized in that the non-inverting input end of an operational amplifier U3.1 is connected with one end of a resistor R8 and one end of a resistor R9, the inverting input end of the operational amplifier U3.1 is connected with one end of a capacitor C3, one end of a resistor R7 and the inverting input end of an operational amplifier U4.2, the other end of the resistor R7 is connected with the output end of the operational amplifier U3.1 and the other end of a resistor R9, and the other end of the capacitor C3 is connected with the other end of the resistor R8 and connected with a power supply VDD/2 in parallel; the output end of the operational amplifier U4.2 is connected with the grid electrode of the field effect transistor Q2, the positive power supply end of the operational amplifier U4.2 is connected with a power supply VDD, the negative power supply end of the operational amplifier U4.2 is grounded, the source electrode of the field effect transistor Q2 is connected with the cathode of the diode D2 and one end of the inductor L2, and the drain electrode of the field effect transistor Q2 is used as the voltage input end of the voltage regulating circuit (2), is recorded as a port HV _ in and is connected with a port HV _ out of the power supply management circuit (1); the other end of the inductor L2 is connected with the anode of the electrolytic capacitor C4, is used as a compensation output end of the voltage regulating circuit (2), is recorded as a port ADV _ out, and is respectively connected with a port ADV _ in1 of the energy transmitting circuit (3) and a port ADV _ in2 of the output automatic control circuit (6); the cathode of the electrolytic capacitor C4 is connected with the anode of the diode D2 and is connected with the ground; the non-inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R12 and one end of a resistor R13, the inverting input end of the operational amplifier U5.1 is connected with one end of a resistor R10 and one end of a resistor R11, the other end of the resistor R10 is connected with the output end of the operational amplifier U5.1 and the non-inverting input end of an operational amplifier U4.2, the other end of the resistor R11 serves as the reference input end of a voltage regulating circuit, is marked as a port Vref _ in1, and is connected with a port Vref _ out1 of a reference voltage circuit (9); the other end of the resistor R12 is used as a sampling input end of the voltage regulating circuit, is recorded as a port ReshapeV _ in and is connected with a port ReshapeV _ out of the signal shaping circuit (5); the other end of the resistor R13 is connected with a power supply VDD/2;

the energy emission circuit (3) is structurally characterized in that the grid electrode of a field effect transistor Q3 is used as a first driving end of the energy emission circuit (3), is marked as a port Drv _ in1 and is connected with a port Drv _ out1 of the bridge driving circuit (7); the source electrode of the field effect transistor Q3 is respectively connected with the drain electrode of the field effect transistor Q4 and one end of the capacitor C5, is used as a second driving end of the energy emission circuit (3), is marked as a port Drv _ in2, and is connected with a port Drv _ out2 of the bridge driving circuit (7); the grid electrode of the field effect transistor Q4 is connected with one end of the R14, serves as a third driving end of the energy emission circuit (3), is marked as a port Drv _ in3, and is connected with a port Drv _ out3 of the bridge driving circuit (7); the grid electrode of the field effect transistor Q5 is used as a fourth driving end of the energy emission circuit (3), is marked as a port Drv _ in4, and is connected with a port Drv _ out4 of the bridge driving circuit (7); the source electrode of the field effect transistor Q5 is respectively connected with the drain electrode of the field effect transistor Q6 and one end of an inductor L3, is used as a fifth driving end of the energy emission circuit (3), is marked as a port Drv _ in5, is connected with a port Drv _ out5 of the bridge driving circuit (7), and the other end of the inductor L3 is connected with the other end of the capacitor C5; the grid of the field effect transistor Q6 is connected with one end of the resistor R15, serves as the sixth driving end of the energy emission circuit (3), is marked as a port Drv _ in6, and is connected with a port Drv _ out6 of the bridge driving circuit (7); the other end of the resistor R15 is respectively connected with the other end of the resistor R14, the source electrode of the field-effect transistor Q4 and the source electrode of the field-effect transistor Q6, is used as a sampling output end of the energy emission circuit (3), is recorded as a port SampV _ out, and is connected with a port SampV _ in of the current detection amplifying circuit (4); the drain electrode of the field effect transistor Q3 is connected with the drain electrode of the field effect transistor Q5, is used as a compensation input end of the energy emission circuit (3), is marked as a port ADV _ in1, and is connected with a port ADV _ out of the voltage regulation circuit (2);

the current detection amplifying circuit (4) is structurally characterized in that a non-inverting input end of an operational amplifier U7.2 is connected with one end of a resistor RS1, is used as a sampling input end of the current detection amplifying circuit (4) and is marked as a port SampV _ in and is connected with a port SampV _ out of an energy transmitting circuit (3), an inverting input end of the operational amplifier U7.2 is respectively connected with one end of a resistor R16, one end of a resistor R17, one end of a variable resistor W2 and a movable contact of the variable resistor W2, an output end of the operational amplifier U7.2 is connected with the other end of a resistor R16 and is used as an amplifying output end of the current detection amplifying circuit (4) and is marked as a port AmpV _ out and is connected with a port AmpV _ in of a signal shaping circuit (5); the other end of the variable resistor W2 is respectively connected with one end of a resistor R18, one end of a resistor R19 and the inverting input end of an operational amplifier U6.1, the other end of the resistor R17 is respectively connected with the other end of the resistor R18 and the output end of the operational amplifier U6.1, the other end of the resistor R19 is connected with a power supply VDD/2, the non-inverting input end of the operational amplifier U6.1 is respectively connected with the negative power supply end of the operational amplifier U6.1 and the other end of the resistor RS1 and is grounded, and the positive power supply end of the operational amplifier U6.1 is connected with the;

the signal shaping circuit (5) is structurally characterized in that a positive power supply end of an operational amplifier U8.2 is connected with a power supply VDD, a negative power supply end of the operational amplifier U8.2 is grounded, an inverting input end of the operational amplifier U8.2 is respectively connected with one end of a resistor R21 and one end of a capacitor C7, a non-inverting input end of the operational amplifier U8.2 is connected with one end of a capacitor C6 and is grounded, the other end of the capacitor C6 is respectively connected with one end of a resistor R20, the other end of a resistor R21 and one end of a resistor R22, the other end of the resistor R20 is used as a voltage input end of the signal shaping circuit (5) and is marked as a port AmpV _ in and is connected with a port AmpV _ out of a current detection; the other end of the resistor R22 is respectively connected with the other end of the capacitor C7, one end of the resistor R23 and the output end of the operational amplifier U8.2; the inverting input end of the operational amplifier U9.1 is respectively connected with one end of a resistor R24 and one end of a capacitor C9, the non-inverting input end of the operational amplifier U9.1 is connected with one end of a capacitor C8 and grounded, and the other end of the capacitor C8 is respectively connected with one end of a resistor R25, the other end of a resistor R24 and the other end of a resistor R23; the other end of the resistor R25 is respectively connected with the other end of the capacitor C9 and the output end of the operational amplifier U9.1, is used as the shaping output end of the signal shaping circuit (5), is recorded as a port ReshapeV _ out, and is connected with a port ReshapeV _ in of the voltage regulating circuit (2);

the structure of the output automatic control circuit (6) is that the positive power end of an operational amplifier U10.2 is connected with a power supply VDD, the negative power end of the operational amplifier U10.2 is grounded, the inverting input end of the operational amplifier U10.2 is used as the reference input end of the output automatic control circuit (6) and is marked as a port Vref _ in2, the inverting input end of the operational amplifier U10.2 is connected with a port Vref _ out2 of a reference voltage circuit (9), the non-inverting input end of the operational amplifier U10.2 is connected with the cathode of a voltage stabilizing diode D3 and one end of a resistor R26, the anode of the voltage stabilizing diode D5 is grounded, the other end of the resistor R26 is used as the compensation input end of the output automatic control circuit (6) and is marked as a port ADV _ in2, and is connected with; the output end of the operational amplifier U10.2 is connected with the base of a triode Q7, the collector of a triode Q7 is connected with a power supply VDD, the emitters are respectively connected with one end of a resistor R27, one end of a resistor R28 and the emitter of a triode Q8, the other end of a resistor R27 is connected with one end of a capacitor C10 and the input end of an inverter U13.4, the other end of the resistor R28 and the other end of the capacitor C10 are grounded, the output end of the inverter U13.4 is connected with a clock signal end Cp of a D flip-flop U11.1, a trigger signal end D of the D flip-flop U11.1 is respectively connected with a clear end Cd and one end of a capacitor C11 and grounded, the other end of the capacitor C11 is respectively connected with the anode of a diode D4, one end of the resistor R29 and a preset end Sd of the D flip-flop U11.1, the cathode of a diode D4 is not connected with the other end of the resistor R29 and the opposite phase output end Q of the D flip-flop U11.1, the same phase output end Q of the D, the output end of the inverter U15.2 is used as the control output end of the output automatic control circuit (6) and is recorded as a port CtrlV _ out which is connected with a port CtrlV _ in of the bridge drive circuit (7); a trigger signal end D of the D trigger U12.2 is respectively connected with a zero clearing end Cd of the D trigger U12.2 and one end of a capacitor C12, the other end of the capacitor C12 is connected with an anode of a diode D5, one end of a resistor R30 and a preset end Sd of the D trigger U12.2, a cathode of the diode D5 is respectively connected with the other end of a resistor R30 and an inverted phase output end Q of the D trigger U12.2, the same phase output end Q of the D trigger U12.2 is connected with an input end of an inverter U14.1, an output end of the inverter U14.1 is connected with a base electrode of a triode Q8, and a collector electrode of the triode Q8 is connected with a power supply VDD;

the bridge driving circuit (7) is configured such that a voltage input terminal VCC of a bridge driver U16 and one end of a capacitor C13 are connected to a power supply VDD, the other end of the capacitor C13 and a COM terminal of a bridge driver U16 are grounded, a high level input terminal HIN of the bridge driver U16 is connected to a drain of the fet Q9 and a low level input terminal LIN of the bridge driver U17, respectively, and serves as a first control input terminal of the bridge driving circuit (7), which is denoted as a port TsV _ in1, and is connected to a port TsV _ out1 of the control timing generating circuit (8), a VB terminal of the bridge driver U16 is connected to a cathode of a diode D6 and one end of a capacitor C15, a VS terminal of the bridge driver U16 is connected to the other end of a capacitor C15 and one end of a resistor R33, which serves as a second output terminal of the bridge driving circuit (7), which is denoted as a port Drv _ out2, and is connected to a port Drv _ in2 of the energy, a high level output end HO of the bridge driver U16 is connected to one end of a resistor R32, the other end of the resistor R32 is connected to the other end of the resistor R33, and serves as a first output end of the bridge driver circuit (7), which is denoted as a port Drv _ out1 and is connected to a port Drv _ in1 of the energy emission circuit (3), an anode of a diode D6 is connected to one end of a resistor R31, the other end of the resistor R31 is connected to a power supply VDD, a low level output end LO of the bridge driver U16 is connected to one end of a resistor R34, and the other end of the resistor R34 serves as a third output end of the bridge driver circuit (7), which is denoted as a port Drv _ out3 and is connected to a port Drv _ in3 of the energy emission circuit; a voltage input terminal VCC of the bridge driver U17 and one end of a capacitor C14 are connected to the power supply VDD, the other end of the capacitor C14 and a COM terminal of the bridge driver U17 are grounded, a high level input terminal HIN of the bridge driver U17 is connected to the drain of the fet Q10 and the low level input terminal LIN of the bridge driver U16, respectively, and serves as a second control input terminal of the bridge driver circuit (7), which is denoted as a port TsV _ in2, and is connected to a port TsV _ out2 of the control timing generation circuit (8), a VB terminal of the bridge driver U17 is connected to the cathode of the diode D7 and one end of the capacitor C16, a VS terminal of the bridge driver U17 is connected to the other end of the capacitor C16 and one end of the resistor R36, and serves as a fifth output terminal of the bridge driver circuit (7), which is denoted as a port Drv _ out5, and is connected to a port Drv _ in5 of the energy emission circuit (3), a high level output terminal HO of the bridge driver U46, the other end of the resistor R37 is connected with the other end of the resistor R36, and is used as a fourth output end of the bridge driving circuit (7) and is marked as a port Drv _ out4 to be connected with a port Drv _ in4 of the energy transmitting circuit (3), the anode of the diode D7 is connected with one end of a resistor R38, the other end of the resistor R38 is connected with a power supply VDD, a low-level output end LO of the bridge driver U17 is connected with one end of the resistor R35, the other end of the resistor R35 is used as a sixth output end of the bridge driving circuit (7) and is marked as a port Drv _ out6 to be connected with a port Drv _ in6 of the energy transmitting circuit (3); the source electrode of the field effect transistor Q9 and the source electrode of the field effect transistor Q10 are grounded, the grid electrode of the field effect transistor Q9 is connected with the grid electrode of the field effect transistor Q10 and serves as the third control input end of the bridge driving circuit (7), is recorded as a port CtrlV _ in and is connected with a port CtrlV-out of the output automatic control circuit (6);

the control timing sequence generating circuit (8) is structurally characterized in that a ground end GND of a 555 timer U27 is grounded and is respectively connected with one end of a capacitor C17, one end of a capacitor C18 and one end of a capacitor C19, the other end of the capacitor C18 is connected with a control end CVOLT of a 555 timer U27, a trigger input end TRIG of the 555 timer U27 is respectively connected with a threshold end THR of the 555 timer U27, one end of an R40 and the other end of a C17, the other end of the R40 is respectively connected with one end of an R39 and a discharge end DIS of the 555 timer U27, and the other end of the R39 is respectively connected with a reset end RST of the 555 timer U27 and a voltage input end + VCC and is connected with a power supply VDD; an output end OUT of the 555 timer U27 is respectively connected with an input end of an inverter 25.6 and an input end of an inverter 26.5, an output end of the inverter 26.5 is used as a first control output end of a control time sequence generation circuit (8), is marked as a port TsV _ OUT1 and is connected with a bridge drive circuit (7); the output end of the inverter 25.6 is connected with one end of a resistor R41, the other end of the resistor R41 is respectively connected with the other end of a capacitor C19 and the input end of an inverter U20.6, the output end of the inverter U20.6 is connected with a clock signal end Cp of a D flip-flop U18.1, a preset end Sd of the D flip-flop U18.1 is respectively connected with one end of a capacitor C20, one end of a resistor R42 is connected with the anode of a diode D8, the other end of a capacitor C20 is connected with a trigger signal end D of a D trigger U18.1 and a clear end Cd of the D trigger U18.1, the other end of the resistor R42 is not connected with the cathode of the diode D8 and an anti-phase output end Q of the D trigger U18.1, the in-phase output end Q of the D trigger U18.1 is connected with the input end of an inverter 19.3, the output end of the inverter U19.3 is used as a second control output end of a control timing generation circuit (8), is recorded as a port TsV _ out2 and is connected with a bridge drive circuit (7);

the reference voltage circuit (9) is structured IN that an input end IN of a reference voltage source U24 is connected with one end of a capacitor C21 and connected with a power supply VDD IN parallel, an NR end of a reference voltage source U24 is connected with one end of a capacitor C22, a ground end GND of a reference voltage source U24 is respectively connected with the other end of a capacitor C21, the other end of a capacitor C22, one end of a capacitor C23 and one end of a resistor R43 and connected with ground, the other end of the capacitor C23 is respectively connected with an output end OUT of the reference voltage source U24, the TRIM end of the reference voltage source U24, the I.C./3 end of the reference voltage source U24 and the non-inverting input end of an operational amplifier U21.1, the inverting input end of the operational amplifier U21.1 is respectively connected with the other end of a resistor R43, one end of the capacitor C24 and one end of the resistor R44, the other end of the capacitor C24 is respectively connected with the output end of the operational amplifier U21.1, one end of a variable resistor W3, one end of a, the output end of the operational amplifier U22.2 is fed back to the inverting input end, is used as a first reference output end of the reference voltage circuit (9), is marked as a port Vref _ out1, and is connected with a port Vref _ in1 of the voltage regulating circuit (2); the movable contact of the variable resistor W4 is connected with the non-inverting input end of the operational amplifier U23.1, the output end of the operational amplifier U23.1 is fed back to the inverting input end, and is used as the second reference output end of the reference voltage circuit (9), which is marked as a port Vref _ out2 and is connected with a port Vref _ in2 of the output automatic control circuit (6); the other end of the variable resistor W3 and the other end of the variable resistor W4 are grounded.

2. A drone wireless charging transmission system according to claim 1, characterised in that in the energy transmission circuit (3), the inductance L3 is 10 mH; the capacitor C5 is 100 pF; the resistors R14 and R15 are both 18k omega.

3. The multi-path wireless charging and transmitting system for the small unmanned aerial vehicle as claimed in claim 1, wherein in the current detection amplifying circuit (4), the resistors R16, R17, R18 and R19 are 10k Ω, the resistor RS1 is 0.1 Ω, and the variable resistor W2 is 100k Ω.

4. The multi-channel wireless charging and transmitting system for the small unmanned aerial vehicle as claimed in claim 1, wherein in the output automatic control circuit (6), the capacitor C10 is 200nF, the capacitor C11 is 1 μ F, and the capacitor C12 is 100 nF; the resistance R26 is 20k Ω, the resistance R27 is 10k Ω, the resistance R28 is 2k Ω, the resistance R29 is 1M Ω, and the resistance R30 is 100k Ω.

5. The multi-channel wireless charging and transmitting system for the small unmanned aerial vehicle as claimed in claim 1, wherein in the control timing generating circuit (8), the capacitance C17 is 100 μ F, and the capacitances C18, C19 and C20 are 4.3 nF; the resistance R39 is 700 Ω, the resistance R40 is 3.1k Ω, the resistance R41 is 250 Ω, and the resistance R42 is 8.2k Ω.