CN111354395A

CN111354395A - Memory cell arrangement and method for operating a memory cell arrangement

Info

Publication number: CN111354395A
Application number: CN201911299669.4A
Authority: CN
Inventors: 京特·莱曼; 普拉尚特·乔杜里; 弗雷德里克·格根顿; 古鲁西达帕·那杜威那曼; 斯特芬·舒曼
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2018-12-21
Filing date: 2019-12-17
Publication date: 2020-06-30
Also published as: US20210375330A1; US20200202901A1; US11508417B2; DE102018133392A1; US11139003B2

Abstract

A memory cell arrangement and a method for operating a memory cell arrangement are provided. The memory cell arrangement may have at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch actuation logic arrangement configured to place the first switch in at least one of at least three operating states selectively by activating or deactivating a first subcircuit of the switch actuation logic arrangement: an on-state, an off-state, and a conducting state in which the electrical conductivity is less than in the on-state and higher than in the off-state.

Description

Memory cell arrangement and method for operating a memory cell arrangement

Technical Field

The invention relates to a memory cell arrangement and to a method for operating a memory cell arrangement.

Background

The present invention relates to a memory circuit, and more particularly to a memory circuit providing a low energy mode. The low-energy mode is understood to be a type of operation with low energy consumption. This is also referred to as a low power mode or standby mode in some applications. The term "Memory" (and terms derived therefrom) is also commonly used in german for electronic data storage.

The Memory cell arrangement or associated circuit may be a Memory cell arrangement or associated circuit for volatile data storage, for example an SRAM (Static Random Access Memory) or DRAM (dynamic Random Access Memory) Memory circuit. For data maintenance of the stored data, the memory circuit must be provided with a predetermined holding voltage on its power supply node.

Products with low energy consumption are based on or contain integrated circuits which in turn can operate in a low energy mode.

Wireless products (i.e. electronic devices configured for cordless data exchange, such as mobile phones, laptops or tablets), chip card products (e.g. cards for identification, such as identification cards, insurance cards, such as e.g. medical insurance cards or payment cards, such as e.g. credit cards), products in the automotive field (e.g. engine control devices for engines responsible for vehicle drive (e.g. internal combustion engines or electric motors) and/or engine control devices for other engines, such as e.g. window lifters), or devices for automated driving, and products for energy management are examples of such products, which may provide a low energy mode.

Most integrated circuits have memory circuits for storing data. In order to be able to provide products with a low energy mode, it should accordingly be possible to operate the memory circuit with low energy consumption.

A portion of the power dissipation in the memory circuit is due to leakage currents. In microcontroller products in the automotive field, the number of SRAM memory cells has approximately doubled at the transition from 40nm process to 28nm process. At the same time, the leakage current per bit that occurs in SRAM has increased (e.g., nearly doubled). This means that the leakage current contribution of SRAM memories has increased by approximately a factor of four.

The memory circuit should provide a technique or process for reducing leakage currents and enable a low-energy mode which is robust, settable, advantageously and simply implemented with respect to the required (chip) plane and which here ensures that the stored data is maintained.

Furthermore, high peak currents when switching from the low energy mode to the normal mode (also called active mode, active power mode or active operation mode) are to be avoided.

A plurality of memory cell arrangements known in the prior art are schematically shown in fig. 2A, more precisely in a variant connected to a positive supply voltage VDD (here the PFET transistor is switched on, shown in the column "VDD switching", NFET based) and in a variant connected to a negative supply voltage or ground terminal VSS (here the NFET transistor is switched on, shown in the column "VSS switching", NFET based), respectively.

In a relatively simply constructed

memory cell arrangement

200a, 200b (shown in the first row of fig. 2A, denoted "energy supply off"), the supply voltage VDD or VSS of the memory cell array 100 can be switched on or off by means of a transistor 220 connected between the memory cell array 100 and the voltage supply VSS or VDD. However, this means that in the case of the volatile memory cell array 100, the information stored in the memory cell array 100 is lost in the off state.

The possibility of providing a reduced operating voltage for the memory cell array 100 for the low energy mode can be designed to use diodes.

In the row of fig. 2A, which is denoted by "diode mode",

memory cell arrangements

201a, 201b are shown, wherein a transistor serving as a diode 222 is connected in parallel with a voltage supply VSS or VDD which can be switched on and off by means of a switch (transistor) 220. If the switch 220 is turned off, a reduced operating voltage for the memory cell array 100 is provided via the diode 222 in the low energy mode, whereby leakage current may be reduced.

An example of such a memory cell arrangement 201a, 201B is shown in fig. 2B (middle) from US 7,110,317B 2. An example is described and shown in fig. 3, here in fig. 2B (top) of Koji ni et al in its article "a dynamic/static SRAM power management scheme for DVFS and avs in advanced automatic information SoCs" (Digest of Technical paper-ieee symposium on VLSI Technology,2016 9/21 th), in which a reduced operating voltage can be provided by means of a diode 222 connected in series with a main switch 220.

However, using this configuration of the main switch 220 and the additional diode 222 means that, although chip areas for both components (main switch 220 and diode 222) have to be provided, the diode 222 still makes only a small contribution to the voltage supply of the memory cell array 100 in the active mode (i.e. in normal operation). Furthermore, the voltage (VSSC or VDDC) provided by means of the diode cannot be set in the low energy mode. Furthermore, this configuration has the disadvantage that the voltage supply to the memory cell array 100 is caused via the series circuit of the components, as a result of which an undesirably increased voltage drop is obtained across the series circuit, which in turn can only be compensated by increasing the chip area.

The so-called "sustain mode" is shown in the third row in fig. 2A. Here, the sustain voltage VDDRET (or the raised sustain voltage VSSRET) that is lowered with respect to the operating voltage VDD (or VSS) for normal operation may be turned on via the transistor 224.

However, a separate VDDRET voltage supply (or VSSRET voltage supply) is required on the chip for the "sustain mode," which consumes chip area and increases wiring complexity. In addition, a face of the circuit for generating the VDDRET voltage (or VSSRET voltage) is required.

However, when the circuit for generating the VSSRET voltage or the VSSRET voltage is used together (e.g. a plurality of memory cells), the situation-dependent setting of the VSSRET voltage cannot be provided by means of the configuration.

The relatively complex configuration is shown in fig. 2A in the last row for the

memory circuits

203a, 203b (denoted by "regulator mode"). Here, a control circuit 228 for operating the gate of the main switch 220 is provided.

The control circuit 228 is complex in this configuration, sensitive to changes/fluctuations and consumes chip area and additional energy.

A corresponding configuration example for the memory circuit 203a according to US 2009/0189684 a1 is shown in fig. 2B (lower).

Disclosure of Invention

In various embodiments, a memory cell device is provided having a low energy mode for its storage elements. The memory cell arrangement may have at least one switching element which provides more than two modes, for example on/off/diode.

In contrast, in the prior art, combinations of switching elements are disclosed, wherein each switching element provides only one mode (diode) or two modes (on/off).

Memory cell arrangements are provided in various embodiments. The memory cell arrangement may have at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch actuation logic arrangement configured to selectively place the first switch in one of at least three operating states by activating or deactivating a first subcircuit of the switch actuation logic arrangement: a switch-on state; an off state; and a conductive state in which the conductivity is lower than in the on state and higher than in the off state.

The conduction state can be provided by means of a diode, for example in that: the first switch has a transistor which can be switched on for an on-state and off for an off-state and which is operated in a diode mode for a conducting mode.

Thus, at least three operating states (on state, off state, conducting state) can be realized by means of a single switch, so that chip area can be saved.

In various embodiments, the memory cell arrangement may have a second switch connected between the at least one memory cell and the reference potential, wherein the switch actuation logic arrangement may be further configured to place the second switch in one of at least three operating states, selectively by activating or deactivating the second subcircuit of the switch actuation logic arrangement: a switch-on state; an off state; and a conductive state in which the conductivity is lower than in the on state and higher than in the off state.

Thereby, it can be achieved in different embodiments, for example, that the voltage level of VSSC (or VDDC) is matched to the characteristic properties of the memory cells within the memory array during the low energy mode, for example, in such a way that: only one of the switches is placed in one state while the other switches are placed in the other state.

Furthermore, the occurrence of high peak currents when switching the memory cell arrangement from the low-energy mode into the active ("on") mode can be reduced in different embodiments, for example by: the first switching element is first switched on in turn, before which the further (e.g. second) switching element is switched on.

In different embodiments, all switching elements may contribute to the voltage supply in the active mode ("on mode").

The "off mode" may be implemented as follows: all switching elements are placed in an "off" mode.

In various embodiments, the ground voltage supply may be switchably configured, or the positive voltage supply, or both.

Drawings

Embodiments of the invention are illustrated in the drawings and are described in detail below.

The figures show:

FIG. 1 shows a schematic diagram of a memory cell arrangement according to the prior art;

FIG. 2A shows a summary of various schematically shown storage cell arrangements according to the prior art;

FIG. 2B illustrates an example of a memory cell device according to the prior art;

FIG. 3 shows a schematic diagram of a memory cell arrangement according to various embodiments;

FIG. 4 shows a schematic diagram of a memory cell arrangement according to various embodiments;

FIG. 5 shows a schematic diagram of a memory cell arrangement according to various embodiments;

FIG. 6 shows a schematic diagram of switch states in a memory cell arrangement according to various embodiments; and

FIG. 7 shows a flow diagram of a method for operating a memory cell arrangement according to various embodiments.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as, for example, "upper," "lower," "front," "rear," etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is to be understood that the features of the different exemplary embodiments described herein may be combined with each other as long as they are not specifically stated otherwise. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

In the context of this specification, the terms "connected," "coupled," and "coupled" are used to describe direct and indirect connections, direct or indirect couplings, and direct or indirect couplings. In the drawings, the same or similar elements are provided with the same reference numerals, as long as this is appropriate.

Various embodiments are described herein with respect to a device, and various embodiments are described with respect to a method. It is to be understood that features and characteristics described in connection with the apparatus also apply to the method and vice versa.

Fig. 3 to 5 respectively show schematic diagrams of a memory cell arrangement 300 according to different embodiments. The embodiments of fig. 3, 4 and 5 are distinguished as memory cell arrangements 300a, 300b or 300 c. The general reference numeral 300 is used for a memory cell arrangement as long as it does not relate to the special features of the respective embodiment.

The memory cell arrangement 300 as described herein may be used, for example, in the automotive field, for example, with a 28nm process.

The memory cell arrangement 300 can have at least one memory cell 102, for example in the form of a memory cell array 100 (also referred to as memory array 100). The memory cell 102 may be a conventional memory cell 102, such as a RRAM, MRAM, PC-RAM, ROM or flash memory cell, in particular a conventional volatile memory cell 102, such as a DRAM or SRAM cell. The memory cell array 100 may accordingly be a conventional memory cell array 100, as shown for example in fig. 1 and described in connection therewith, for example a memory cell array 100, for example an SRAM, DRAM, RRAM, MRAM, PC-RAM, ROM or flash memory array.

To operate the memory cell array 100, operating

voltages

108, 110 can be provided at its inputs. This is also represented in fig. 3 to 5 by the operating voltage 108 for positive or much more positive and by the operating voltage 110 for negative or much more negative or ground.

The memory cell arrangement 300 can also represent a positive or much more positive reference potential 106 (also denoted VDD in fig. 3 to 5, according to the usual expression V for positive supply voltages_DD) And a negative or much more negative or ground reference potential 104 (denoted VSS in fig. 3 to 5, according to the usual expression V for a negative supply voltage, usually GND)_SS)。

In the case where a constant reference potential is applied to one of the inputs of the memory cell array 100, the operating

voltage

108 or 110 can be equal to the respective reference potential 104 or 106 (reference potential 106 in fig. 3 to 5).

In various embodiments, the memory cell arrangement 300 can have a first switch S1 and a switch control logic arrangement 330 connected between the at least one memory cell 102 and the

reference potential

104 or 106. The control logic device may be multi-part as shown in fig. 4 and 5 and, for example, have a first part 330_1 for controlling the first switch S1, a second part 330_2 for controlling the second switch S2, etc. In order to improve visibility, in the description of the functionality of the control logic 330, only those parts of the control logic 330 which are relevant to the described functionality are therefore labeled. It is to be understood that, by merely indicating said reference numerals, no conclusions are made as to the function of other parts of the control logic device 330, as far as present (in particular, the state of inactivity, etc.).

The control logic 330_1 can be configured to selectively place the first switch S1 in one of at least three operating states by activating or deactivating the first subcircuit 330_1T (see fig. 5) of the switch control logic 330_ 1. The at least three operating states may have an on-state, an off-state, and a conducting state in which the electrical conductivity is lower than in the on-state and higher than in the off-state.

In this case, the switch activation logic 330_1 can be designed in various embodiments such that, when the sub-circuit 330_1T is activated, the first switch S1 is placed in the conducting state. For example, the first switch S1 may be a (first) transistor, e.g., a (first) field effect transistor, e.g., an NFET, as in fig. 5, or a PEET (not shown). The switch activation logic 330_1 can be designed such that the subcircuit 330_1T, when activated, produces a conductive connection between the controlled output of the first switch S1 and the gate of the first switch S1, so that the first switch S1 (transistor) is connected as a diode, which is also referred to as a diode mode or diode mode state. In the diode mode, the conductivity of the transistor (and thus the first switch S1) is lower than in the fully conductive (closed) state of the transistor and higher than in the insulating (open) state of the transistor.

If the sub-circuit 330_1T is disabled, the first switch S1 may be placed in an off state (e.g., an off state) or in an on state (e.g., an on state). For switching between the conducting state and the off state of the first switch S1, further switches 550, 552 can be provided in the switch control logic 330_1, by means of which the gate of the first switch S1 can be selectively connected to the positive reference potential 106 or to the negative reference potential 104.

The switch activation logic 330_1 can be configured such that, in the on state, the gate is connected to a

reference potential

104 or 106, which closes the first switch S1 or closes the first switch S1, and thus the at least one memory cell 102 is connected to the reference potential 104 or 106 (104 in fig. 3 to 5); in the off state, the gate is connected to a

further reference potential

104 or 106, which opens the first switch S1 or leaves the first switch S1 open and thus prevents the at least one memory cell 102 from being connected to the reference potential 104 or 106 (104 in fig. 3 to 5).

For example, in the on state, the gate of the first transistor (i.e., the first switch S1), also referred to as the first gate, may be connected to the positive voltage supply terminal 106 (positive reference potential, e.g., VDD). In the off-state, the first gate may be connected with the ground terminal 104 (negative reference potential, e.g., VSS), while in the conducting state, the first gate may be connected with the virtual voltage supply terminal 110.

Here, the first field effect transistor may be an NFET transistor, and the virtual voltage supply terminal 110 may be a ground terminal.

To enable switching of the connections of the gate to the positive reference potential 106, the negative reference potential 104 and the virtual voltage supply terminal 110, the switch control logic 330 may have further switches, for example transistors.

For example, the switch steering logic device 330 may have or consist of a gate control circuit. In the embodiment of fig. 5, the gate control circuit for the first switch S1 corresponds to the first portion 330_1 of the switch steering logic device 330. The gate control circuit may have a fourth field effect transistor 550 between the first gate and the positive voltage supply terminal 106. The gate of the fourth field effect transistor may be provided or provided with a first switching voltage conb 1.

The gate control circuit may also have a fifth field effect transistor 552 between the first gate and the ground terminal 104. The gate of the fifth field effect transistor 552 may be supplied or provided with a second switching voltage coff 1.

The gate control circuit may further have a sixth field effect transistor TG1 (or a pair of two field effect transistors TG1) between the first gate and the virtual voltage supply terminal 110. A third switching voltage cdiode1 may be provided or provided on the gate of the sixth field effect transistor TG1 (or on the gates of the two field effect transistors TG1 of the pair). The two field effect transistors of the pair may here comprise an NFET transistor and a PFET transistor, in particular a pair of two field effect transistors connected in parallel.

In various embodiments, a PFET transistor, for example, may be used instead of the NFET transistor for the first switch S1. In this case, the first switch S1 and the switch control logic 330 may be connected between the positive reference potential 106 and the at least one memory cell 102. The negative reference potential 110 (e.g. the ground terminal VSS) may in this case be provided directly as the supply voltage 104 or directly as the supply voltage 104.

The gate control circuit in said not shown case may be configured to connect the first gate with the ground terminal in an on-state, to connect the first gate with the positive voltage supply terminal in an off-state, and to connect the first gate with the virtual voltage supply terminal in a conducting state. The virtual voltage supply terminal may be a positive voltage supply terminal.

The described configuration makes it possible to provide a memory cell arrangement 300 having a low-energy mode, wherein the first switch S1 contributes to the voltage supply of the at least one memory cell 102 in the on-state and in the conducting state, and wherein a device connected in parallel with the switch S1 is dispensed with, which device does not function in one of the switch states. Furthermore, the switch actuation logic 330 can have a simple structural design, is robust and can be dimensioned very small.

In various embodiments, the memory cell arrangement 300, 300b, 300c can also have a second switch S2 connected between the at least one memory cell 102 and the

reference potential

104 or 106.

The switch activation logic 330, 330_2 may be further configured to selectively place the second switch S2 in one of at least three operating states by activating or deactivating the second subcircuit 330_2T of the switch activation logic 330_ 2: a switch-on state; an off state; and a conductive state in which the conductivity is lower than in the on state and higher than in the off state.

In other words, the second switch S2 having a similar function to the first switch S1 may be provided. The configuration of the second switch S2 may be the same as or similar to the configuration of the first switch S1. For example, the second switch S2 may be a (second) transistor, such as a (second) field effect transistor.

The switch actuation logic 330 may have or consist of a second gate control circuit for actuating the gate of the second switch S2. In the embodiment in fig. 5, the control circuit for the second switch S2 corresponds to the second part 330_2 of the switch manipulation logic means 330. The gate control circuit may have a seventh field effect transistor 554, an eighth field effect transistor 556 and a ninth field effect transistor TG2 (or a pair of two field effect transistors TG2) whose functions correspond to the

field effect transistors

550, 552 or TG1 of the first gate control circuit. The respective gates of the seventh, eighth and ninth

field effect transistors

554, 556, TG2 may be supplied or provided with a fourth, fifth or sixth switching voltage conb2, boff2 or cdiode 2. The pair of two field effect transistors TG2 may here comprise an NFET transistor and a PFET transistor, in particular a pair of two field effect transistors connected in parallel.

The first switch S1 and the second switch S2 may be connected in parallel with each other, as shown in fig. 4 and 5.

The memory cell arrangement 300, 300b, 300c can also have further switches (not shown) connected between the at least one memory cell 102 and the

reference potential

104 or 106, which have the same function as the first switch S1 and the second switch S2, and which can be brought into one of at least three operating states (on state; off state; and conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state), in particular by means of the switch actuation logic 330.

In various embodiments, the first switch S1 and the second switch S2 may be configured to be in one of their three operating states, respectively, independently of each other. In other words, the two switches S1, S2 may be in an on state, the two switches S1, S2 may be in an off state, the two switches S1, S2 may be in a conducting state, one of the switches may be in an on state and the other switch may be in an off state, one of the switches may be in an on state and the other switch may be in a conducting state, or one of the switches may be in a conducting state and the other switch may be in an off state.

In the memory cell arrangement 300, in various embodiments, the switch steering logic arrangement 330 may be configured such that the memory cell arrangement 300 is selectively placed in one of at least three power stages by placing the first switch S1 and the second switch S2 in one of its three operating states (on-state, off-state, conducting state), respectively: a fully-on state in which the first switch and the second switch are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first switch and the second switch are in an off state.

The fully open state may be set for normal operation of the memory cell arrangement 300.

The all-off state can be set to a state for completely turning off the memory cell arrangement 300, i.e. a state in which a loss of data stored in the at least one memory cell 102 is tolerated.

The partial power state may be used for standby operation, i.e. for example for the following states: in this state, although no active use of the memory cell 300 takes place, i.e. no normal operation in which, for example, writing into at least one memory cell 102 and/or reading out from at least one memory cell 102 takes place, it is nevertheless desirable to maintain the data stored in at least one memory cell 102, for example in the memory cell array 100.

In various embodiments, the at least three power stages may also have a partially on state in which the first switch S1 is in an on state and the second switch S2 is in an off state.

The partially open state may serve as an intermediate switching phase for the transition from the fully off state or the partially power state to the fully on state, since high peak currents may thereby be reduced or avoided. For example, the individual switches can be switched in turn from an off state into an on state and thereby avoid high peak currents.

In various embodiments, the partially on state and/or the partially power state may be configured such that the value of the voltage dropped across the at least one memory cell 102 is sufficiently high to ensure continued data storage.

All (main) switches S1, S2 … …, i.e. switches S1, S2 … … which are configured to directly connect the supply voltage of at least one memory cell 102, are configured to contribute to the voltage supply of at least one memory cell 102, for example memory cell array 100, in a normal operating mode (in active mode) of memory cell arrangement 300, in which all switches S1, S2 … … are placed in an on-state or in an on-state (i.e. in a fully open state). In this case, a series connection of voltage supply switches, which deteriorate the conductivity, can be dispensed with, as is shown in the prior art from fig. 2B (top).

In various embodiments, the memory cell arrangement 300, 300b, 300c may also have a third switch S3 connected between at least one memory cell 102 and the

reference potential

104 or 106. The switch actuation logic 330 may be configured to selectively place the third switch S3 in one of exactly two operating states, namely in an on state or an off state.

In other words, the third switch S3 can be provided with limited functionality (on/off only) with respect to the first switch S1 (and, if present, with respect to the second switch S2). The third switch S3 may be connected in parallel with the first switch S1 (and possibly with the second switch S2 and possibly further switches), as shown in fig. 4 and 5. The third switch S3 may be formed as a transistor (also referred to as a third transistor), for example as a field effect transistor, for example as an NFET, as shown in fig. 5, or as a PFET (not shown).

The gate of the third switch S3 may be selectively connected to the positive reference potential 106 or to the negative (ground) reference potential 104. For selective connection, e.g. for switching between two connections, a tenth transistor 558 may be provided between the gate and the positive reference potential 106 and an eleventh transistor 560 may be provided between the gate and the negative (ground) reference potential 104. A common seventh switching voltage conb3 may be provided or provided at the gates of the tenth and

eleventh transistors

558, 560.

The third switch S3 may be considered a main energizing switch. Since in addition to the main energy supply switch S3, the first switch S1 and possibly the second switch S2 and possibly further switches also contribute to the energy supply of the at least one storage cell in the normal operating mode, the third switch S3 can be dimensioned smaller.

Similar to the memory cell arrangements 300, 300b described above with the first switch S1 and the second switch S2, the switch actuation logic arrangement 330 of the memory cell arrangement 300c can be configured to selectively place the memory cell arrangement 300c in one of at least three power stages by placing the first switch S1 and the second switch S2 in one of its three operating states and the third switch S3 in one of its two operating states, respectively: a fully-on state in which the first, second and third switches are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first, second and third switches are in an off state.

In the embodiment in fig. 5, the off-state may be achieved, for example, by connecting the respective gates of the first or second or third switches S1, S2 or S3, respectively formed as NFET transistors, to a negative reference potential 104, for example VSS. This may be achieved, for example, as described below.

In various embodiments, the at least three power stages may also have a partially on state in which at least one of the first switch S1, the second switch S2, and the third switch S3 is in an on state and at least one of the other two switches is in an off state.

The use of these power stages may correspond in terms of meaning to what has been described above for the memory cell arrangement 300b with the two switches S1, S2.

The fully-off state may be achieved in different embodiments (as shown, for example, in FIG. 5; where the three switches S1, S2, and S3 are placed in an off state for the fully-off state) by: as a virtual reference potential, i.e. as cdiode1 or cdiode2, a negative (ground) reference potential is provided, a positive reference potential (conb1, conb2 or conb3, e.g. VDD) is provided at the gates of the fourth, seventh and

tenth transistors

550, 554 and 558, respectively, and a positive reference potential (coff1, coff2, e.g. VDD) is likewise provided at the gates of the fifth and

eighth transistors

552 and 556, respectively.

In various embodiments, the first switch S1 may have a higher conductivity in the conductive state than the second switch S2 in the conductive state. This can be realized in a simple form as a technical implementation, for example, by: the first switch S1 is a first field effect transistor and the second switch S2 is a second field effect transistor, wherein the first field effect transistor has a larger transistor width than the second field effect transistor.

In various embodiments, as a further simple implementation of the different conductivities, the first field effect transistor (i.e. the first switch S1) alternatively or additionally has a lower threshold voltage than the second field effect transistor (i.e. the second switch S2).

Thereby, more different configurations/settings can be achieved for the low energy mode (e.g. partial power mode; if necessary also partial on mode can be considered as low energy mode).

For illustration, fig. 6 shows different combinations of operating states for the three switches S1, S2, and S3 of the exemplary embodiment of fig. 5, from which the power levels indicated at the lower edge are derived, which are switched from "active on" to "off" and, as intermediate levels, have three power levels designated as "low energy" (weak/medium/strong), "weak on" and "medium open" (these correspond to the partial separation mode described above).

As can be seen exemplarily from fig. 6, for example, the power stage "low energy in" differs from the power stage "high and low energy" although in both power stages one of the switches S1, S2 is in diode mode and the other switch is off. This difference can be achieved precisely by the different configurations of the switch described above, for example in terms of its conductivity. Currently, the first switch S1 has a higher conductivity than the second switch S2.

The operating

voltage

110 or 108 provided for at least one memory cell 102 in the low-energy mode can accordingly be set finely when using more, for example differently designed switches S1, S2 … … and is matched to the requirements of at least one memory cell 102, for example of the memory array 100.

In various embodiments, during the test phase, it may be determined, for example, what operating voltage is required for data maintenance, the requirement of the at least one memory cell 102, and the combination of the conduction states of the first and/or second switches S1, S2 and/or the power level to be achieved may be configured or configured such that the determined operating voltage may also be ensured in the low-energy mode.

Such flexibility may be advantageous because fluctuations during the fabrication of a semiconductor device may cause memory cells 102 or memory arrays 100 to have different characteristics. In particular, some memory arrays 100 may have different requirements for a higher sustain voltage (VDDC-VSSC) than other memory arrays. For example, one memory array 100 may require 0.6V in order to ensure that the data stored therein is maintained, while another memory array 100 may require only 0.5V.

The sustain voltage for the entire memory array 100, set according to the memory array 100 requiring the highest voltage, may unnecessarily increase power consumption for a portion of the memory array 100 because the memory array 100 actually requiring a smaller voltage operates at an unnecessarily high voltage during the low voltage mode (e.g., may actually operate at 0.5V, but use 0.6V).

In various embodiments, a configurable voltage supply (i.e., VDDC, VSSC, or both) is provided. In this case, for example, configuration can be carried out during manufacturing test, i.e. to maintain the voltage to be matched to fluctuations in the manufacturing process.

The matching or coordination may be done at the wafer level in different embodiments, i.e. such that all chips on the wafer are provided with the same settings, but each wafer gets its own settings.

In different embodiments, matching or coordination may be done at the chip level, i.e., such that all memory arrays 100 of a chip are provided with the same settings, but each chip obtains its own settings.

In various embodiments, the matching or coordination may be performed at the memory level, i.e., such that each memory array 100 of a chip is provided with its own settings.

In various embodiments, the power consumption of the memory cell arrangement 300 is reduced.

The required chip-area reduction and the reduced energy consumption directly or indirectly (for example, wherein the reduced energy consumption leads to cost savings in the chip package, the voltage supply device and/or the cooling device) lead to a cost reduction.

Furthermore, the possibility of setting the sustain voltage relatively finely in harmony after the test can improve the yield in manufacturing.

FIG. 7 illustrates a flow diagram of a method 700 for operating a memory cell arrangement, in accordance with various embodiments.

The method 700 may include: a memory cell arrangement is provided having at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch actuation logic arrangement having a first subcircuit (at 710).

The method 700 may further include: selectively placing the first switch in one of at least three operating states by activating or deactivating the first sub-circuit: a switch-on state; an off state; and a conductive state in which conductivity is less than in the on state and higher than in the off state (in 720).

Some embodiments are generally described below.

Embodiment 1 is a memory cell device. The storage unit device may have: at least one memory cell; a first switch connected between the at least one memory cell and a reference potential; and switch actuation logic configured to place the first switch in one of at least three operating states selectively by activating or deactivating a first sub-circuit of the switch actuation logic: a switch-on state; an off state, and a conducting state in which conductivity is less than in the on state and higher than in the off state.

Embodiment 2 is the memory cell arrangement of embodiment 1, further having a second switch connected between the at least one memory cell and the reference potential; wherein the switch manipulation logic is further configured to place the second switch in one of at least three operating states selectively by activating or deactivating a second sub-circuit of the switch manipulation logic: a switch-on state; an off state; and a conductive state in which conductivity is less than in the on state and higher than in the off state.

Embodiment 3 is the memory cell device of

embodiment

1 or 2, further having: a third switch connected between the at least one memory cell and the reference potential, wherein the switch manipulation logic is further configured to selectively place the third switch in one of exactly two operating states: a switch-on state; and an off state.

Embodiment 4 is the memory cell device of embodiment 2 or 3, wherein the first switch in the conducting state has a higher conductivity than the second switch in the conducting state.

Embodiment 5 is the memory cell device of any one of embodiments 1-4, wherein the first switch has a first field effect transistor.

Embodiment 6 is the memory cell device of embodiment 5, wherein the conduction state of the first field effect transistor is a diode mode state of the first field effect transistor.

Embodiment 7 is the memory cell device of any one of embodiments 2-6, wherein the second switch has a second field effect transistor.

Embodiment 8 is the memory cell device of embodiment 7, wherein the conduction state of the second field effect transistor is a diode mode state of the second field effect transistor.

Embodiment 9 is the memory cell device of embodiment 7 or 8, wherein the first field effect transistor has a larger transistor width than the second field effect transistor.

Embodiment 10 is the memory cell device of any one of embodiments 7-9, wherein the first field effect transistor has a lower threshold voltage than the second field effect transistor.

Embodiment 11 is the memory cell arrangement of any one of embodiments 5-10, wherein the first field effect transistor has a first gate, wherein the switch steering logic arrangement has a first gate control circuit configured to connect the first gate to a positive voltage supply terminal in an on state, to connect the first gate to a ground terminal in an off state, and to connect the first gate to a virtual voltage supply terminal in a conducting state.

Embodiment 12 is the memory cell device of embodiment 11, wherein the first field effect transistor is an NFET transistor; and wherein the virtual voltage supply terminal is a ground terminal.

Embodiment 13 is the memory cell device of any one of embodiments 5-10, wherein the first field effect transistor has a first gate, wherein the switch steering logic device has a first gate control circuit configured to connect the first gate to a ground terminal in an on state, to connect the first gate to a positive voltage supply terminal in an off state, and to connect the first gate to a virtual voltage supply terminal in a conducting state.

Embodiment 14 is the memory cell arrangement of embodiment 13, wherein the first field effect transistor is a PFET transistor; and wherein the virtual voltage supply terminal is a positive voltage supply terminal.

Embodiment 15 is the memory cell device of any one of embodiments 11 to 14, wherein the gate control circuit has a third field effect transistor between the first gate and the positive voltage supply terminal.

Embodiment 16 is the memory cell device of any one of embodiments 11-15, wherein the gate control circuit has a fourth field effect transistor between the first gate and the ground terminal.

Embodiment 17 is the memory cell device of any one of embodiments 11 to 16, wherein the gate control circuit has a fifth field effect transistor between the first gate and the virtual voltage supply terminal.

Embodiment 18 is the memory cell arrangement of embodiment 2, wherein the switch manipulation logic arrangement is configured to selectively place the memory cell arrangement in one of at least three power stages by placing the first switch and the second switch in one of their respective three operating states: a fully-on state in which the first and second switches are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first switch and the second switch are in an off state.

Embodiment 19 is the memory cell arrangement of embodiment 18, wherein the at least three power stages further have a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

Embodiment 20 is the memory cell arrangement of embodiment 3, wherein the switch manipulation logic arrangement is configured to selectively place the memory cell arrangement in one of at least three power stages by placing the first switch and the second switch in one of their three operating states, respectively, and placing the third switch in one of its two operating states: a fully-on state in which the first, second, and third switches are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first switch, the second switch, and the third switch are in an off state.

Embodiment 21 is the memory cell device of embodiment 20, wherein the at least three power stages further have a partially on state in which at least one of the first switch, the second switch, and the third switch is in an on state and at least one of the other two switches is in an off state.

Embodiment 22 is the memory cell arrangement of any one of embodiments 18 to 21, wherein the partial power state and/or the partially on state are configured such that a value of a voltage dropped across the at least one memory cell is sufficiently high to ensure continuous data storage.

Embodiment 23 is the memory cell device of any one of embodiments 1-22, wherein the memory cell device forms a volatile data memory.

Embodiment 24 is the memory cell device of any one of embodiments 1-23, wherein the memory cell device forms an SRAM, DRAM, RRAM, MRAM, PC-RAM, ROM, or flash data memory.

Embodiment 25 is a method for operating a memory cell device, the memory cell device having: at least one memory cell; a first switch connected between the at least one memory cell and a reference potential; and a switch manipulation logic device having a first sub-circuit, the method comprising: selectively placing the first switch in one of at least three operating states by activating or deactivating the first sub-circuit: a switch-on state; an off state, and a conducting state in which conductivity is less than in the on state and higher than in the off state.

Embodiment 26 is the method of embodiment 25, wherein the memory cell arrangement further has a second switch connected between the at least one memory cell and the reference potential, and a second sub-circuit in the switch steering logic arrangement, the method further comprising: selectively placing the second switch in one of at least three operating states by activating or deactivating the second sub-circuit: a switch-on state; an off state; and a conductive state in which conductivity is less than in the on state and higher than in the off state.

Embodiment 27 is the method of embodiment 25 or 26, wherein the memory cell arrangement further has a third switch connected between the at least one memory cell and the reference potential, the method further comprising: selectively placing the third switch in one of exactly two operating states: a switch-on state; and an off state.

Embodiment 28 is the method of embodiment 26, further comprising: placing the first switch and the second switch in one of their three operating states, respectively, to selectively place the memory cell arrangement in one of at least three power stages: a fully-on state in which the first and second switches are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first switch and the second switch are in an off state.

Embodiment 29 is the method of embodiment 28, wherein the at least three power stages further have: a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

Embodiment 30 is the method of embodiment 27, further comprising: placing the first switch and the second switch in one of their three operating states, and placing the third switch in one of its two operating states, respectively, to selectively place the memory cell device in one of at least three power stages: a fully-on state in which the first, second, and third switches are in an on state; a partial power state in which at least one of the first switch and the second switch is in a conducting state; and a fully off state in which the first switch, the second switch, and the third switch are in an off state.

Embodiment 31 is the method of embodiment 30,

wherein the at least three power stages further have: a partially on state in which at least one of the first switch, the second switch, and the third switch is in an on state and at least one of the other two switches is in an off state.

Embodiment 32 is the method of any one of embodiments 28 to 31, further comprising: placing the memory cell arrangement in a fully on state for active operation.

Embodiment 33 is the method of any one of embodiments 28 to 32, further comprising: placing the memory cell arrangement in a partial power state for standby operation.

Embodiment 34 is the method of embodiment 29 or 31, further comprising: in placing the memory cell arrangement from the fully off state into the fully on state, the memory cell arrangement is first placed from the fully off state into the partially on state and then the memory cell arrangement is placed from the partially on state into the fully on state.

Claims

1. A memory cell device, comprising:

at least one memory cell;

a first switch connected between the at least one memory cell and a reference potential;

a switch manipulation logic configured to place the first switch in one of at least three operating states selectively by activating or deactivating a first sub-circuit of the switch manipulation logic:

an on state;

an off state, and

a conducting state in which the electrical conductivity is lower than in the on-state and higher than in the off-state.

2. The memory cell device according to claim 1, further comprising:

a second switch connected between the at least one memory cell and the reference potential;

wherein the switch manipulation logic is further configured to place the second switch in one of at least three operating states selectively by activating or deactivating a second sub-circuit of the switch manipulation logic:

an on state;

an off state; and

3. The memory cell arrangement according to claim 1 or 2,

further comprising:

a third switch connected between the at least one memory cell and the reference potential;

wherein the switch manipulation logic is further configured to selectively place the third switch in one of exactly two operating states:

an on state; and

off state.

4. The memory cell arrangement according to claim 2 or 3,

wherein the first switch in the conducting state has a higher conductivity than the second switch in the conducting state.

5. The memory cell arrangement according to one of claims 1 to 4,

wherein the first switch has a first field effect transistor.

6. The memory cell arrangement according to claim 5,

wherein the conduction state of the first field effect transistor is a diode mode state of the first field effect transistor.

7. The memory cell arrangement according to one of claims 2 to 6,

wherein the second switch has a second field effect transistor.

8. The memory cell arrangement according to claim 7,

wherein the conduction state of the second field effect transistor is a diode mode state of the second field effect transistor.

9. The memory cell arrangement according to claim 7 or 8,

wherein the first field effect transistor has a larger transistor width than the second field effect transistor.

10. The memory cell arrangement according to one of claims 7 to 9,

wherein the first field effect transistor has a lower threshold voltage than the second field effect transistor.

11. The memory cell arrangement according to one of claims 5 to 10,

wherein the first field effect transistor has a first gate,

wherein the switch steering logic device has a first gate control circuit configured to connect the first gate with a positive voltage supply terminal in an on state, to connect the first gate with a ground terminal in an off state, and to connect the first gate with a virtual voltage supply terminal in a conducting state.

12. The memory cell arrangement according to claim 11,

wherein the first field effect transistor is an NFET transistor; and is

Wherein the virtual voltage supply terminal is a ground terminal.

13. The memory cell arrangement according to one of claims 5 to 10,

wherein the first field effect transistor has a first gate,

wherein the switch steering logic device has a gate control circuit configured to connect the first gate with a ground terminal in an on state, to connect the first gate with a positive voltage supply terminal in an off state, and to connect the first gate with a virtual voltage supply terminal in a conducting state.

14. The memory cell arrangement according to claim 13,

wherein the first field effect transistor is a PFET transistor; and is

Wherein the virtual voltage supply terminal is a positive voltage supply terminal.

15. The memory cell arrangement according to any one of claims 11 to 14,

wherein the gate control circuit has a third field effect transistor between the first gate and the positive voltage supply terminal.

16. The memory cell arrangement according to any one of claims 11 to 15,

wherein the gate control circuit has a fourth field effect transistor between the first gate and the ground terminal.

17. The memory cell arrangement according to any one of claims 11 to 16,

wherein the gate control circuit has a fifth field effect transistor between the first gate and the virtual voltage supply terminal.

18. The memory cell arrangement according to claim 2,

wherein the switch steering logic is configured to selectively place the memory cell arrangement in one of at least three power stages by placing the first switch and the second switch in one of their respective three operating states:

a fully open state in which the first and second switches are in an on state;

a partial power state in which at least one of the first switch and the second switch is in a conducting state; and

a fully off state in which the first and second switches are in an off state.

19. The memory cell arrangement according to claim 18,

wherein the at least three power stages further have a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

20. The memory cell arrangement according to claim 3,

wherein the switch actuation logic device is configured to selectively place the memory cell device in one of at least three power stages by placing the first switch and the second switch in one of their three operating states and placing the third switch in one of its two operating states, respectively:

a fully open state in which the first, second and third switches are in an on state;

a fully off state in which the first, second and third switches are in an off state.

21. The memory cell arrangement according to claim 20,

wherein the at least three power stages further have a partially on state in which at least one of the first switch, the second switch, and the third switch is in an on state and at least one of the other two switches is in an off state.

22. The memory cell arrangement according to any one of claims 18 to 21,

wherein the partial power state and/or the partially on state are configured such that the value of the voltage dropped across the at least one memory cell is sufficiently high to ensure continued data storage.

23. The memory cell arrangement according to any one of claims 1 to 22,

wherein the memory cell arrangement forms a volatile data memory.

24. The memory cell arrangement according to any one of claims 1 to 23,

wherein the memory cell arrangement forms an SRAM data memory, a DRAM data memory, an RRAM data memory, an MRAM data memory, a PC-RAM data memory, a ROM data memory or a flash data memory.

25. A method for operating a memory cell arrangement, the memory cell arrangement having: at least one memory cell; a first switch connected between the at least one memory cell and a reference potential; and a switch manipulation logic device having a first sub-circuit, the method comprising:

selectively placing the first switch in one of at least three operating states by activating or deactivating the first sub-circuit:

an on state;

an off state, and

26. Method for operating a memory cell arrangement according to claim 25,

wherein the memory cell arrangement further has a second switch connected between the at least one memory cell and the reference potential and a second subcircuit in the switch steering logic arrangement, the method further comprising:

selectively placing the second switch in one of at least three operating states by activating or deactivating the second sub-circuit:

an on state;

an off state; and

27. Method for operating a memory cell arrangement according to claim 25 or 26, wherein the memory cell arrangement further has a third switch connected between the at least one memory cell and the reference potential, the method further comprising:

selectively placing the third switch in one of exactly two operating states:

an on state; and

off state.

28. The method for operating a memory cell unit of claim 26, the method further comprising:

placing the first switch and the second switch in one of their three operating states, respectively, to selectively place the memory cell device in one of at least three power stages:

a fully open state in which the first and second switches are in an on state;

a fully off state in which the first and second switches are in an off state.

29. Method for operating a memory cell arrangement according to claim 28,

wherein the at least three power stages further have:

a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

30. The method for operating a memory cell device of claim 27, the method further comprising:

placing the first switch and the second switch in one of their three operating states, and placing the third switch in one of its two operating states, respectively, to selectively place the memory cell device in one of at least three power stages:

31. Method for operating a memory cell arrangement according to claim 30,

wherein the at least three power stages further have:

a partially on state in which at least one of the first switch, the second switch and the third switch is in an on state and at least one of the other two switches is in an off state.

32. The method for operating a storage unit arrangement according to any one of claims 28 to 31, the method further comprising:

placing the memory cell arrangement in a fully on state for active operation.

33. The method for operating a storage unit arrangement according to any one of claims 28 to 32, the method further comprising:

placing the memory cell arrangement in a partial power state for standby operation.

34. The method for operating a memory cell arrangement according to claim 29 or 31, the method further comprising: in placing the memory cell arrangement from the fully off state into the fully on state, the memory cell arrangement is first placed from the fully off state into the partially on state and then the memory cell arrangement is placed from the partially on state into the fully on state.