CN111352862A - Key destroying method, system, password card and password machine - Google Patents
Key destroying method, system, password card and password machine Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/45—Structures or tools for the administration of authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2143—Clearing memory, e.g. to prevent the data from being stolen
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Abstract
The application discloses a method and a system for destroying a secret key, a password card and a password machine, wherein an interrupt detection process is configured to detect a level signal of a detection pin of a main control chip; if the interrupt detection process detects that the signal at the detection pin is a low level signal, triggering an interrupt process; and the master control chip executes the interrupt process to erase the key storage area of the master control chip. When the key is required to be destroyed, only the detection pin of the password card is grounded, at this time, the level signal of the detection pin connected with the main control chip is changed from high level to low level, and the low level signal triggers the interrupt process to directly erase the key storage area.
Description
Technical Field
The application relates to the technical field of information security, in particular to a method and a system for destroying a secret key, a password card and a password machine.
Background
Information security is a multi-level, multi-factor and comprehensive dynamic process, the information security requires comprehensive thinking and unified planning on an information system and an organization system, the information security needs to pay attention to the change of internal and external environments of a monitoring system, and the information security is likely to threaten the organization of the whole system due to the security defect in a certain link. Therefore, the information security is a dynamic process with multiple layers, multiple factors and integration, and is a continuous development process which needs a system to guarantee the information security.
The password card is basic core password equipment in the field of information security, and the security of the password card directly influences the security of the whole system. The key point of the password card is the security performance of the password card, but the key destruction which is a very important security element of the password card is ignored. The key destruction refers to a function that the password card starts an internal watching program to destroy the key stored inside after detecting the signal.
In the traditional technology, corresponding key destruction software is generally required to be built in the process of executing key destruction by the password card, and the key destruction software is controlled to be started to execute the key destruction function when the key destruction is required, but the software is started in a starting time, so that the timeliness of key destruction cannot be ensured, and certain risks exist in key protection.
Disclosure of Invention
In order to solve the technical problems, the following technical scheme is provided:
in a first aspect, an embodiment of the present application provides a method for destroying a secret key, where the method includes: configuring an interrupt detection process to detect a level signal of a detection pin of a main control chip; if the interrupt detection process detects that the signal at the detection pin is a low level signal, triggering an interrupt process; and the master control chip executes the interrupt process to erase the key storage area of the master control chip.
By adopting the implementation mode, when the key is required to be destroyed, only the detection pin is grounded, the level signal of the detection pin connected with the main control chip is changed from high level to low level, and the low level signal triggers the interrupt process to directly erase the key storage area.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the performing, by the configuration interrupt detection process, level signal detection on a detection pin of a main control chip includes: the interrupt detection process is configured to be continuously detected when the high level is reached, and the interrupt process is triggered when the low level is reached; and after the configuration of the interrupt detection process is finished, high and low level detection is carried out on the detection pins in real time.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the performing, by the master control chip, the interrupt process to erase the key storage area of the master control chip includes: the interrupt process locates the address of a key storage area from the main control chip; and calling a writing FLASH function to write all the data in the key storage area into 0xFF according to the acquired address of the key storage area.
With reference to the first aspect, in a third possible implementation manner of the first aspect, the main control chip is externally connected to a hardware trigger mechanism, and the hardware trigger mechanism controls a level signal of the detection pin.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the key destruction includes active destruction and passive destruction, and hardware trigger structures corresponding to different types of destruction are different.
In a second aspect, an embodiment of the present application provides a key destruction system, where the system includes: the configuration module is used for configuring an interrupt detection process to detect a level signal of a detection pin of the main control chip; the interrupt triggering module is used for triggering an interrupt process if the interrupt detection process detects that the signal at the detection pin is a low-level signal; and the key destruction module is used for the main control chip to execute the interrupt process to erase the key storage area of the main control chip.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the configuration module includes: the configuration unit is used for configuring the interrupt detection process into continuous detection at a high level and triggering the interrupt process at a low level; and the detection unit is used for entering high and low level detection to detect the detection pin in real time after the configuration of the interrupt detection process is finished.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the key destruction module includes: the address positioning unit is used for positioning the address of the key storage area from the main control chip by the interrupt process; and the data erasing unit is used for calling a writing FLASH function to write all the data in the key storage area into 0xFF according to the acquired address of the key storage area.
In a third aspect, an embodiment of the present application provides a cryptographic card, including: a main control chip; a power supply module; the memory is used for storing the main control chip processing executable instruction; the main control chip executes the key destruction method described in the first aspect or any possible implementation manner of the first aspect, and erases key information in the key storage area of the main control chip.
In a fourth aspect, an embodiment of the present application provides a cryptographic machine, including: a cipher machine shell; the main board is arranged in the cipher machine shell; the main board is provided with the password card of the third aspect.
Drawings
Fig. 1 is a schematic flowchart of a key destruction method according to an embodiment of the present application;
fig. 2 is a schematic diagram of a key destruction system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a cryptographic card according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a cryptographic machine according to an embodiment of the present application.
Detailed Description
The present invention will be described with reference to the accompanying drawings and embodiments.
Fig. 1 is a schematic flow chart of a key destruction method provided in an embodiment of the present application, and referring to fig. 1, the key destruction method in the embodiment includes:
s101, configuring an interrupt detection process to detect a level signal of a detection pin of a main control chip.
The power module provides an uninterrupted power supply for the main control chip, the hardware interruption detection function realized in the main control chip is realized, the interruption detection process is configured to be continuously detected when the high level is high, and the interruption process is triggered when the low level is low. After the configuration of the detection pin and the interrupt service program is completed, the chip automatically enters a high-low level detection working process to detect the detection pin in real time.
S102, if the interrupt detection process detects that the signal at the detection pin is a low level signal, the interrupt process is triggered.
In the embodiment of the application, the process of erasing the key storage area is triggered only when the configured detection pin is at a low level, and other level interrupt service programs are automatically ignored. In the whole detection process, if the detection pin is always at a high level, the detection is continuously carried out until the level signal is switched to a low level, and an interrupt process is triggered.
It should be noted that the low level signal of the detection pin in the embodiment of the present application is triggered by a hardware trigger mechanism, that is, no other software program or system intervention is required. Specifically, the key destruction includes active destruction and passive destruction, and hardware trigger structures corresponding to different types of destruction are different. In this embodiment, when the key is actively destroyed, a legitimate user of the key initiates active destruction for protecting the key, and at this time, a corresponding hardware trigger mechanism is actively destroyed to power off the cryptographic card, so that the interrupt process is triggered when the level detection is low. On the contrary, if the password device is illegally opened, the corresponding hardware triggering mechanism for passive destruction is triggered at the moment of opening to power off the password card, and the interruption process can also be triggered.
Compared with the traditional method of destroying the secret key by adopting a program or a system, the method for destroying the secret key by adopting the hardware triggering mechanism to power off the password card is simple and quick, and the success rate of destroying the secret key is high.
S103, the main control chip executes the interrupt process to erase the key storage area of the main control chip.
If the level is detected as low level in S102, an interrupt process is triggered to perform key destruction. The interrupt process locates the address of the key storage area from the main control chip, calls a FLASH writing function to write all the data of the key storage area into 0xFF according to the obtained address of the key storage area, and achieves the purpose of key destruction.
It can be known from the foregoing embodiments that, in the key destruction method provided in this embodiment, when the key destruction is required, only the detection pin needs to be grounded, at this time, the level signal of the detection pin connected to the main control chip changes from the high level to the low level, and the low level signal triggers the interrupt process to directly erase the key storage area.
Corresponding to the key destruction method provided by the above embodiment, the present application also provides an embodiment of a key destruction system. Referring to fig. 2, the key destruction system 20 includes: a configuration module 201, an interrupt trigger module 202 and a key destruction module 203.
The configuration module 201 is configured to configure an interrupt detection process to perform level signal detection on a detection pin of the main control chip. The interrupt triggering module 202 is configured to trigger an interrupt process if the interrupt detection process detects that the signal at the detection pin is a low-level signal. The key destruction module 203 is configured to the main control chip execute the interrupt process to erase the key storage area of the main control chip.
Further, the configuration module 201 includes: a configuration unit and a detection unit.
The configuration unit is used for configuring the interrupt detection process into continuous detection at a high level and triggering the interrupt process at a low level. And the detection unit is used for entering high and low level detection to detect the detection pin in real time after the configuration of the interrupt detection process is finished.
The key destruction module 203 includes: an address location unit and a data erasure unit.
And the address positioning unit is used for positioning the address of the key storage area from the main control chip by the interrupt process. And the data erasing unit is used for calling a writing FLASH function to write all the data in the key storage area into 0xFF according to the acquired address of the key storage area.
The embodiment of the present application further provides a password card, and referring to fig. 3, the password card 30 includes: a main control chip 301, a memory 302 and a power supply module 303.
In fig. 3, a main control chip 301, a memory 302 and a power module 303 may be connected to each other through a bus; the bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 3, but this does not mean only one bus or one type of bus.
The main control chip 301 generally controls the overall function of the cryptographic card 30, for example, the cryptographic card 30 is started, and after the cryptographic card is started, an interrupt detection process is configured to perform level signal detection on a detection pin of the main control chip; if the interrupt detection process detects that the signal at the detection pin is a low level signal, triggering an interrupt process; and the master control chip executes the interrupt process to erase the key storage area of the master control chip.
The memory 302 is configured to store computer executable instructions to support the operation of the cryptographic card 30 data. The memory 301 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
After the cryptographic card 30 is started, the main control chip 301 and the memory 302 are powered on, and the main control chip 301 reads and executes the computer executable instructions stored in the memory 302 to complete all or part of the steps in the above-described embodiment of the key destruction method.
The power module 303 provides power to the various components of the cryptographic card 30. The power components may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the cryptographic card 30.
In an exemplary embodiment, the cryptographic card 30 provided in the embodiment of the present application further includes a communication interface for the cryptographic card 30 to transmit data, for example, to implement communication with an external chip or device. The communication interface comprises a wired communication interface and can also comprise a wireless communication interface. The wired communication interface comprises a USB interface, a Micro USB interface and an Ethernet interface. The wireless communication interface may be a WLAN interface, a cellular network communication interface, a combination thereof, or the like.
The cryptographic card 30 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. The communication component receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. The communication component also includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the cryptographic card 30 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), or other electronic components.
As shown in fig. 4, in the cipher machine provided in this embodiment, the cipher machine 40 provided in this embodiment includes a cipher machine housing 401 and a main board 402, and the cipher card 30 described in the above embodiment is disposed on the main board 402.
The hardware triggering mechanism is arranged on the cipher machine shell 401 in this embodiment, and the power-off of the cipher card can be actively or passively realized, so that the process of key destruction is triggered, and the security of key destruction is further improved.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Of course, the above description is not limited to the above examples, and technical features that are not described in this application may be implemented by or using the prior art, and are not described herein again; the above embodiments and drawings are only for illustrating the technical solutions of the present application and not for limiting the present application, and the present application is only described in detail with reference to the preferred embodiments instead, it should be understood by those skilled in the art that changes, modifications, additions or substitutions within the spirit and scope of the present application may be made by those skilled in the art without departing from the spirit of the present application, and the scope of the claims of the present application should also be covered.
Claims (10)
1. A method of key destruction, the method comprising:
configuring an interrupt detection process to detect a level signal of a detection pin of a main control chip;
if the interrupt detection process detects that the signal at the detection pin is a low level signal, triggering an interrupt process;
and the master control chip executes the interrupt process to erase the key storage area of the master control chip.
2. The key destruction method according to claim 1, wherein the detecting level signal detection is performed on a detection pin of the main control chip by the configuration interrupt detection process, and the detecting level signal detection comprises:
the interrupt detection process is configured to be continuously detected when the high level is reached, and the interrupt process is triggered when the low level is reached;
and after the configuration of the interrupt detection process is finished, high and low level detection is carried out on the detection pins in real time.
3. The key destruction method according to claim 2, wherein the main control chip executing the interrupt process to erase the key storage area of the main control chip comprises:
the interrupt process locates the address of a key storage area from the main control chip;
and calling a writing FLASH function to write all the data in the key storage area into 0xFF according to the acquired address of the key storage area.
4. The key destruction method according to claim 1, wherein the main control chip is externally connected with a hardware trigger mechanism, and the hardware trigger mechanism controls the level signal of the detection pin.
5. The key destruction method according to claim 4, wherein the key destruction comprises active destruction and passive destruction, and different types of destruction correspond to different hardware triggering structures.
6. A key destruction system, characterized in that the system comprises:
the configuration module is used for configuring an interrupt detection process to detect a level signal of a detection pin of the main control chip;
the interrupt triggering module is used for triggering an interrupt process if the interrupt detection process detects that the signal at the detection pin is a low-level signal;
and the key destruction module is used for the main control chip to execute the interrupt process to erase the key storage area of the main control chip.
7. The key destruction system according to claim 6, wherein the configuration module comprises:
the configuration unit is used for configuring the interrupt detection process into continuous detection at a high level and triggering the interrupt process at a low level;
and the detection unit is used for entering high and low level detection to detect the detection pin in real time after the configuration of the interrupt detection process is finished.
8. The key destruction system according to claim 7, wherein the key destruction module comprises:
the address positioning unit is used for positioning the address of the key storage area from the main control chip by the interrupt process;
and the data erasing unit is used for calling a writing FLASH function to write all the data in the key storage area into 0xFF according to the acquired address of the key storage area.
9. A cryptographic card, comprising:
a main control chip;
a power supply module;
the memory is used for storing the main control chip processing executable instruction;
the main control chip executes the key destruction method according to any one of claims 1 to 5, and erases the key information in the key storage area of the main control chip.
10. A cryptographic engine, comprising:
a cipher machine shell;
the main board is arranged in the cipher machine shell;
the motherboard is provided with the password card of claim 9.
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| CN202010145998.XA CN111352862A (en) | 2020-03-05 | 2020-03-05 | Key destroying method, system, password card and password machine |
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| CN202010145998.XA CN111352862A (en) | 2020-03-05 | 2020-03-05 | Key destroying method, system, password card and password machine |
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Application publication date: 20200630 |