CN111343014A - Data center network topology design method based on combination design - Google Patents
Data center network topology design method based on combination design Download PDFInfo
- Publication number
- CN111343014A CN111343014A CN202010097925.8A CN202010097925A CN111343014A CN 111343014 A CN111343014 A CN 111343014A CN 202010097925 A CN202010097925 A CN 202010097925A CN 111343014 A CN111343014 A CN 111343014A
- Authority
- CN
- China
- Prior art keywords
- switch
- switches
- design
- elements
- super
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013461 design Methods 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 11
- 230000002776 aggregation Effects 0.000 claims abstract description 54
- 238000004220 aggregation Methods 0.000 claims abstract description 54
- 239000008187 granular material Substances 0.000 claims description 9
- 238000012423 maintenance Methods 0.000 abstract description 4
- 239000007787 solid Substances 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/12—Discovery or management of network topologies
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
The invention discloses a data center network topology design method based on combination design, which is used for designing tree topology structures with different performance advantages. For example, a tree topology with a larger number of servers and a tree topology with a stronger fault tolerance capability may be supported. Wherein, the structure of the tree topology is characterized in that: the system consists of a three-layer switch and a one-layer server; the three-layer switches are sequentially called as a core switch, a convergence switch and an edge switch from top to bottom, the core switch is only connected with the convergence switch, and each server is only connected with one edge switch; meanwhile, the aggregation switch and the edge switch are divided into a plurality of racks, and the edge switch is only connected with the aggregation switch in the same rack. It should be noted that the above-mentioned hierarchical and multi-chassis structural features are a key reason for the ease of deployment and maintenance of the tree topology.
Description
Technical Field
The invention relates to a data center network topology design method based on combination design, and belongs to the field of data center network research in computer network research directions.
Background
A data center is an infrastructure that provides cloud computing services. The data center network is a core foundation of a data center architecture, and is connected with a mass server through a switch and a high-speed link between the switches, so that powerful computing resources and storage resources are provided. The topology structure of the data center network refers to the connection relationship between all switches and servers in the data center, and directly influences the performance of the data center network. In recent years, researchers at home and abroad have proposed many design schemes for data center network topologies, such as Fat-Tree, DCell, and BCube. Among the design schemes, a Tree topology represented by Fat-Tree becomes a mainstream topology design scheme of the commercial data center at present due to the characteristic of easy deployment and maintenance.
However, as the traffic patterns and business requirements of data centers are continuously changing and developing, the data centers have more and higher requirements on performance indexes of their topology designs. The existing tree-shaped topological structure has single and fixed performance index, and is difficult to meet the diversified requirements of a data center. For example, the expansion capability of the existing tree topology is strictly limited by the number of ports of the switch, and the existing tree topology cannot be effectively expanded to support more servers; meanwhile, the tree topology structure also has the defects that a communication link is lack of an alternative switch and single point of failure is easy to occur, and the defect that the scale of the data center network is further enlarged is overcome. With the continuous increase of data scale and calculation demand, how to increase the number of supportable servers while maintaining the advantages of the tree topology structure becomes a problem to be solved urgently, and improving the fault tolerance capability also becomes an important consideration in topology design.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a method for designing a data center network topology, so as to design a tree topology with different performance advantages. For example, a tree topology with a larger number of servers and a tree topology with a stronger fault tolerance capability may be supported. Wherein, the structure of the tree topology is characterized in that: the system consists of a three-layer switch and a one-layer server; the three-layer switches are sequentially called as a core switch, a convergence switch and an edge switch from top to bottom, the core switch is only connected with the convergence switch, and each server is only connected with one edge switch; meanwhile, the aggregation switch and the edge switch are divided into a plurality of racks, and the edge switch is only connected with the aggregation switch in the same rack. It should be noted that the above-mentioned hierarchical and multi-chassis structural features are a key reason for the ease of deployment and maintenance of the tree topology.
In order to achieve the purpose, the technical scheme adopted by the invention is a data center network topology design method based on combined design. The method is characterized by comprising the following steps of:
s1: and constructing a connection mode between the edge server and the aggregation server in the rack.
S1.1: the design of balanced block with { v1, b1, r1, k1, λ 1} parameters is constructed.
S1.2: v1 edge switches and b1 aggregation switches are connected into a bipartite graph according to the block design constructed in S1.1.
S1.3: and c1 copies of v1 edge switches, and each edge switch is connected with the original b1 aggregation switches to form a bipartite graph according to the balanced group design constructed in S1.1.
S1.4: such b1 aggregation switches and v1 x (c1+1) edge switches are built into one rack.
S2: and constructing a connection mode between the core switch and the aggregation switch.
S2.1: x aggregation switches are selected from b1 aggregation switches in the rack, so that each edge switch in the same rack is connected with w aggregation switches in the x aggregation switches. Such a collection of x aggregation switches is referred to as a hyperswitch.
S2.2: and repeating the step S2.1, combining the b1 aggregation switches in the rack into l super switches, and numbering the l super switches as 1,2,3, … and l. Each aggregation switch is contained within the same number of super switches.
S2.3: the construction parameter is a cross-sectional design of { n, v, x }.
S2.4: the design of balanced blocks with the construction parameters { v2, b2, l x z, n, λ 2 }.
S2.5: and repeating the step S1 to build v2 racks.
S2.6: and (5) repeating the step S2.2 for each rack, and combining the aggregation switches into a super switch.
S2.7: arrangement b2 v x2The core switch is divided into b2 core switch groups, and each core switch group contains v x2A station core switch.
S2.8: v2 racks and b2 core switch groups are connected into a bipartite graph according to the balanced block design constructed in S2.4.
S2.9: in the S2.8 connected bipartite graph, for each core switch group and its connected chassis, the core switches in the core switch group and the super switches in the chassis are connected according to steps S2.9.1-S2.9.2.
S2.9.1: and selecting the super switches connected with the core switch group according to the numbering sequence from small to large for each rack. And if the super switches numbered from 1 to i-1 are connected with the z core switch groups and the super switch numbered i is not connected with the z core switch groups, selecting the super switch numbered i.
S2.9.2: combining selected hyperswitches and vx in n racks2The core switches are connected into bipartite graphs according to the cross-sectional design constructed in S2.3.
S2.10: c2 copies of v2 machine frames, and the connection mode of the aggregation switch and the core switch in each machine frame is the same as that of the original machine frame.
S3: each edge switch is connected to s servers.
Compared with the prior art, the invention has at least the following beneficial effects:
1. the topological structure constructed by the invention meets the structural characteristics of layering and multi-frame, and the characteristic is that the tree-shaped topological structure has the characteristic of easy deployment and maintenance and becomes the key reason of the mainstream topological structure of the commercial data center. Meanwhile, the existing routing protocol and fault-tolerant protocol in the commercial data center can be easily migrated to the topological structure constructed by the invention for use.
2. The performance of the topological structure constructed by the invention can flexibly and dynamically meet various requirements. In particular, the topology may support an s v1 v2 (1+ c1) server; at least lambda 1 paths are arranged between servers in the same rack; at least lambda 2 x v x between servers in different racks2A strip path; failure of at least w switches in a super switch can destroy different racksInter-server communication. The performance of the topology is determined by the parameters in the construction step, which the data center designer can adjust to meet their performance requirements for the topology. For example, when a switch with a port number of 36 is used, the existing Fat-Tree architecture can support 11664 servers, whereas embodiments 1 and 2 given below can support 12240 and 198288 servers, respectively; in the existing Fat-Tree architecture, the failure of 1 switch in the aggregation switch can cause the overall failure of the route between servers in different racks, and embodiment 3 given below can keep the overall routing function operating well as long as 1 aggregation switch maintains normal operation.
3. According to the invention, related tools in the combined design are applied to the design process of the data center network topology, so that more theoretical bases are provided for solving the problem of the data center network topology design.
Drawings
FIG. 1 is a schematic diagram of bipartite graphs connected by a balanced block design with parameters {4,6,3,2,1 };
FIG. 2 is a schematic diagram of bipartite graphs connected according to a cross-sectional design with the parameter {3,2,2 };
fig. 3 is a schematic diagram of embodiment 1, in which the number of switch ports is 4;
fig. 4 is a schematic diagram of embodiment 2, in which the number of switch ports is 4;
fig. 5 is a schematic diagram of embodiment 3, in which the number of switch ports is 6.
Detailed Description
For a more complete description of the present invention, reference is now made to the following detailed description taken in conjunction with the accompanying drawings.
To better explain the aspects of the present invention, the following explanations will be made with respect to the terms involved in the present invention. "combinatorial design" is the theory of how to arrange elements in a finite set into different schemes to meet specific properties. The invention mainly relates to two design schemes in a combined design theory, namely a balanced block design and a cross section design.
"balanced granule design" includes balanced incomplete granule design (BIBD) and complete granule design (completblockdesign), which may be defined by one doublet (X, B) and five parameters { v, B, r, k, λ }. Wherein X is a finite set comprising v elements, B is a finite set comprising B elements, and the elements in the set B are subsets of the set X; the elements in each X set are contained in the elements in r B sets, and the elements in each B set contain the elements in k X sets; the elements of each pair of X sets are collectively contained in the elements of the λ B sets. If the elements in each B set do not contain the elements in all the X sets, namely k < v, the balanced granule design is a balanced incomplete granule design; otherwise, the design is complete block set. For example, a balanced incomplete block design (X, B) with a parameter {4,6,3,2,1} may be expressed as X { {1,2,3,4}, B { {1,2}, {3,4}, {1,3}, {2,4}, {1,4}, {2,3} }; a full granule design with parameters {2,3,3,2,3} may be denoted as X { {1,2}, B { {1,2}, {1,2}, {1,2} }.
A "cross-sectional design" may be defined by one triplet (X, G, B) and three parameters { n, v, X }. Wherein X is a finite set comprising n X elements, G is a partition of the set X into n groups, and each group comprises X elements, B is a finite set comprising v X2 elements, and the elements in the set B are subsets of the set X; the elements in each X set are contained in the elements in X B sets, the elements in each B set contain the elements in n X sets, and the n elements are distributed in different groups in G; for each pair of elements in the X set, if they belong to different groups in G, the pair of elements are commonly contained in the elements in the v B sets. For example, a cross-sectional design with a parameter {3,2,2} may be expressed as X { {1,2,3,4,5,6}, G { [1,2], [3,4], [5, 6}, B { {1,3,5}, {1,4,6}, {2,3,6}, {2,4,5}, {1,3,5}, {1,4,6}, {2,3,6}, and {2,4,5} }.
In the steps of the present invention, S1.1, S2.3 and S2.4 relate to the construction of balanced block design and cross-sectional design, and the construction methods of these designs are discussed in the literature in a large amount and are not described herein again.
A "bipartite graph" is a special graph model in graph theory, whose set of vertices can be divided into two mutually disjoint subsets, such that the two endpoints of all edges are contained in the two subsets, respectively.
In the steps of the present invention, S1.2 and S1.3 involve connecting v1 edge switches and b1 aggregation switches into bipartite graphs in a balanced group design with parameters { v1, b1, r1, k1, λ 1 }. The method specifically comprises the steps that v1 edge switches are in one-to-one correspondence with v1 elements of an X set in a balanced group design, B1 aggregation switches are in one-to-one correspondence with B1 elements of a B set in the balanced group design, and if the elements in the X set are contained in the elements in the B set, the corresponding edge switches and the aggregation switches are connected.
S2.8 involves connecting v2 racks and b2 core switch groups into bipartite graphs in a balanced block design with parameters { v2, b2, r2, k2, λ 2 }. The specific method is that v2 racks are in one-to-one correspondence with v2 elements of an X set in a balanced group design, B2 core switch groups are in one-to-one correspondence with B2 elements of a B set in the balanced group design, and if the elements in the X set are contained in the elements in the B set, the corresponding racks are connected with the core switch groups.
Fig. 1 shows a bipartite graph of 4 edge switches/racks and 6 aggregation switches/core switch groups connected according to a balanced block design with parameters {4,6,3,2,1 }. Where circles represent edge switches/racks and rounded rectangles represent aggregation switches/core switch groups. Numbers 1,2,3,4 in the circles represent the corresponding elements 1,2,3,4 in the set of balanced granule designs X, and numbers 12,34,13,24,14,23 in the rounded rectangles represent the corresponding elements {1,2}, {3,4}, {1,3}, {2,4}, {1,4}, and {2,3} in the set of balanced granule designs B, respectively.
S2.9.2 relates to combining selected hyperswitches and vx within n racks2The core switches of the station are connected into bipartite graphs according to a cross-sectional design with parameters n, v, x. The specific method is that all n X aggregation switches contained in selected super switches in n racks are in one-to-one correspondence with n X elements in X set in cross-sectional design, and the selected super switches in n racksStage switch is in one-to-one correspondence with n groups in G in cross-section design, vx2Vx in B set in platform core switch and cross-section design2The elements are in one-to-one correspondence, and if the elements in the X set are contained in the elements in the B set, the corresponding aggregation switch is connected with the core switch.
Fig. 2 shows a bipartite graph of selected hyperswitches in 3 racks connected to 4 core switches according to a cross-sectional design with a parameter of {3,2,2 }. The round corner rectangle represents a rack, the oval represents a super switch, the small circle inside the oval represents a convergence switch forming the super switch, and the large circle outside the oval represents a core switch. Numbers 1,2,3,4,5,6 in the small circles represent corresponding elements 1,2,3,4,5,6 in the X set in the cross-sectional design, respectively, and numbers 135,146,236,245,135,146,236,245 in the large circles represent corresponding elements {1,3,5}, {1,4,6}, {2,3,6}, {2,4,5}, {1,3,5}, {1,4,6}, {2,3,6}, and {2,4,5} in the B set in the cross-sectional design, respectively.
The invention is described in detail below with reference to 3 specific examples.
Example 1
Example 1 a network topology is built using a switch with a port number of 2q, q being a positive integer greater than 1. Fig. 3 is a graph of example 1 when q is 2.
The set up rack of example 1 is shown as 301 in fig. 3, where rounded rectangles represent racks, solid circles represent edge switches, and dashed circles represent aggregation switches. In S1.1, the parameters for the balanced block design constructed in example 1 are { q-1, q, q, q-1, q }. In S1.2, embodiment 1 connects q-1 edge switches and q aggregation switches into a bipartite graph. In S1.3, embodiment 1 duplicates 0 edge switches, i.e., c1 ═ 0.
In S2.1, embodiment 1 selects a single aggregation switch as the super switch, i.e., x is 1; each edge switch in the same rack is connected to the aggregation switch, i.e., w is equal to 1. In S2.2, step S2.1 is repeated q times, q super switches are combined from q aggregation switches, i.e. l equals q.
In S2.3, the cross-sectional design parameters for the configuration of example 1 are { q,1, 1 }. At S2.9.2, example 1 connects selected ones of the q racks and 1 core switch into a bipartite graph in accordance with the cross-sectional design constructed at S2.3, as shown at 302 in fig. 3, with the rounded rectangles representing the racks, the dashed circles inside the rounded rectangles representing the aggregation switches, and the dashed circles outside the rounded rectangles representing the core switches.
In S2.4, the parameters of the balanced block design constructed in example 1 were { q +2, (q +1) × (q +2), q × (q +1), q, q × (q-1) }. In S2.8, example 1 connects q +2 racks and (q +1) × (q +2) core switch groups, each consisting of 1 core switch, into a bipartite graph. As shown at 303 in fig. 3, the chassis are represented by solid rounded rectangles and the core switches are represented by dashed circles. In S2.10, example 1 replicates a rack by 1, i.e., c2 equals 1. The replicated frame is indicated by a dashed rounded rectangle 303 in fig. 3.
In S3, in embodiment 1, q servers are connected to each edge switch, i.e., S ═ q. Example 1 the topology was constructed as shown at 304 in fig. 3, with striped rounded rectangles representing servers.
Example 2
Embodiment 2 a network topology is built using a switch with a port number of 2q, q being a prime power, i.e. a positive integer power of the prime. Fig. 4 is a graph of example 2 when q is 2.
The set up rack of example 2 is shown as 401 in fig. 4, where rounded rectangles represent racks, solid circles represent edge switches, and dashed circles represent aggregation switches. In S1.1, the parameters for the balanced block design constructed in example 2 are { q }2Q (q +1), q +1, q,1 }. In S1.2, example 2q2The station edge switches and q x (q +1) station aggregation switches are connected into a bipartite graph. In S1.3, embodiment 2 duplicates 0 edge switches, i.e., c1 ═ 0.
In S2.1, embodiment 2 selects q aggregation switches as the super switch, i.e., x ═ q; each edge switch in the same rack is connected to the aggregation switch in the super switch, i.e., w is 1. In S2.2, step S2.1 is repeated q +1 times, combining q +1 super switches from q × q (q +1) aggregation switches, i.e., l ═ q + 1.
It should be noted that the choice of hyperswitch here depends on the parameter q2Resolvability of balanced block design of q (q +1), q +1, q,1 }. For a parameter q2Q (q +1), q +1, q,1}, resolvability means that q (q +1) elements of set B can be decomposed into (q +1) groups, and each group of elements in B contains exactly the elements in each set X. One hyperswitch corresponds to a group of elements in B.
In S2.3, the cross-sectional design parameters for the example 2 configuration are { q,1, q }. At S2.9.2, example 2 combines q selected hyperswitches in racks and q2The core switches are connected into bipartite graphs according to the cross-sectional design constructed in S2.3, as shown at 402 in fig. 4, with rounded rectangles representing racks, oval rectangles representing core switch groups, dashed circles within the rounded rectangles representing aggregation switches, and dashed circles within the oval rectangles representing core switches.
In S2.4, the parameters for the balanced block design constructed in example 2 are { q, q +1, q +1, q, q +1 }. In S2.8, example 2 connects q chassis and q +1 core switch groups, each consisting of q core switch groups, into a bipartite graph2A core switch. As shown at 403 in fig. 4, the chassis are represented by solid rounded rectangles and the core switches are represented by dashed circles. In S2.10, example 2 replicates a rack by 1, i.e., c2 equals 1. The replicated frame is indicated by a dashed rounded rectangle 303 in fig. 3.
In S3, embodiment 2 connects q-1 servers for each edge switch, i.e., S-q-1. Example 2 the topology was constructed as shown at 404 in figure 4 with striped rounded rectangles representing servers.
Example 3
Embodiment 3 a network topology is built using a switch with a port number of 2q, q being a positive integer greater than 1. Fig. 3 is a graph of example 3 when q is 3.
The set up rack of example 3 is shown at 501 in fig. 5, where rounded rectangles represent racks, solid circles represent edge switches, and dashed circles represent aggregation switches. In S1.1, the parameters for the balanced block design constructed in example 3 are { q, q, q, q, q }. In S1.2, embodiment 3 connects q edge switches and q aggregation switches into a bipartite graph. In S1.3, embodiment 3 replicates 0 edge switch, i.e., c1 ═ 0.
In S2.1, embodiment 3 selects all q aggregation switches as the hyperswitches, i.e., x ═ q; each edge switch in the same rack is connected to all the aggregation switches in the super switch, i.e., w ═ q. In S2.2, step S2.1 is repeated 1 time, and 1 super switch is combined from q aggregation switches, i.e., l is 1.
In S2.3, the cross-sectional design parameters for the example 3 configuration are { m,1, q }, where m is a factor of 2 q. At S2.9.2, embodiment 3 combines selected hyperswitches and q within m racks2The core switches are connected into bipartite graphs according to the cross-sectional design constructed in S2.3. In fig. 5, example 3 selects m-3. As shown at 502 in fig. 5, the rounded rectangles represent racks, the oval rectangles represent core switch groups, the dashed circles within the rounded rectangles represent aggregation switches, and the dashed circles within the oval rectangles represent core switches.
In S2.4, the parameters for the balanced block design constructed in example 3 are { m,1,1, m,1 }. In S2.8, example 3 connects q racks and 1 core switch group, each consisting of q, into a bipartite graph2A core switch. As indicated at 503 in fig. 5, the chassis are represented by solid rounded rectangles and the core switches are represented by dashed circles. In S2.10, example 3 replicated (2q/m-1) parts of the rack, i.e., c2 ═ 2 q/m-1. The replicated frame is indicated by a dashed rounded rectangle at 503 in fig. 5.
In S3, in example 3, q servers are connected to each edge switch, i.e., S-q. Example 3 the topology was constructed as shown at 504 in figure 5 with striped rounded rectangles representing servers.
It should be noted that any specific examples described above are only for better illustration and understanding of the present invention, but the embodiments of the present invention are not limited by the examples, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be regarded as equivalent substitutions and are included within the scope of the present invention.
Claims (1)
1. A data center network topology design method based on combined design is characterized by comprising the following steps of:
s1: constructing a connection mode between the edge server and the convergence server in the rack;
s1.1: constructing a balanced block design with the parameters of { v1, b1, r1, k1, lambda 1 }; in this balanced block design, v1 represents the number of elements, b1 represents the number of element sets, r1 represents the number of elements each contained in an element set, k1 represents the number of elements each containing in an element set, λ 1 represents the number of elements each pair contained in a common element set;
s1.2: connecting v1 edge switches and b1 convergence switches into a bipartite graph according to the block design constructed in S1.1;
s1.3: c1 copies v1 edge switches, and each edge switch is connected with the original b1 convergence switches to form a bipartite graph according to the design of the balance block set constructed in S1.1;
s1.4: b1 aggregation switches and v1 × c1+ v1 edge switches are built into a rack;
s2: constructing a connection mode between a core switch and a convergence switch;
s2.1: selecting x aggregation switches from b1 aggregation switches in the rack, so that each edge switch in the same rack is connected with w aggregation switches in the x aggregation switches; the collection of the x aggregation switches is called a super switch;
s2.2: repeating the step S2.1, combining the b1 aggregation switches in the rack into l super switches, and numbering the l super switches as 1,2,3, …, l; each aggregation switch is contained in the same number of super switches;
s2.3: constructing a cross-sectional design with the parameters of { n, v, x }; in this cross-sectional design, n represents the number of element groups, x represents the number of elements each element group contains, and v represents the number of elements in each different pair of element groups contained in a common set of elements;
s2.4: constructing a balanced block design with the parameters of { v2, b2, l x z, n, lambda 2 }; in this balanced granule design, v2 represents the number of elements, b2 represents the number of element sets, λ 2 represents the number of elements that are contained in a common element set per pair; further, each element is contained in an integral multiple of l element sets, z represents a multiple, and each element set contains the number of elements n as the number of element groups in the cross-sectional design constructed in S2.3;
s2.5: repeating the step S1 to build v2 racks;
s2.6: repeating the step S2.2 for each rack, and combining the aggregation switches into a super switch; s2.7: arrangement b2 v x2The core switch is divided into b2 core switch groups, and each core switch group contains v x2A station core switch;
s2.8: connecting v2 racks and b2 core switch groups into a bipartite graph according to a balance block group design constructed in S2.4;
s2.9: in the bipartite graph connected in S2.8, for each core switch group and the connected rack thereof, connecting the core switches in the core switch group and the super switches in the racks according to steps S2.9.1-S2.9.2;
s2.9.1: for each rack, selecting a super switch connected with a core switch group according to a numbering sequence from small to large; if the super exchangers with the numbers from 1 to i-1 are connected with the z core switch groups and the super exchanger with the number i is not connected with the z core switch groups, selecting the super exchanger with the number i;
s2.9.2: combining selected hyperswitches and vx in n racks2The core switches are connected into bipartite graphs according to the cross-sectional design constructed in S2.3;
s2.10: c2 parts of v2 machine frames are copied, and the connection mode of a convergence switch and a core switch in each part of machine frame is the same as that of the original machine frame;
s3: each edge switch is connected to s servers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010097925.8A CN111343014B (en) | 2020-02-17 | 2020-02-17 | Data center network topology design method based on combination design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010097925.8A CN111343014B (en) | 2020-02-17 | 2020-02-17 | Data center network topology design method based on combination design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111343014A true CN111343014A (en) | 2020-06-26 |
| CN111343014B CN111343014B (en) | 2022-12-02 |
Family
ID=71186943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010097925.8A Active CN111343014B (en) | 2020-02-17 | 2020-02-17 | Data center network topology design method based on combination design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111343014B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2157319A1 (en) * | 1994-08-31 | 1996-03-01 | Eiji Oki | Communication network design method and communication equipment |
| CN102394782A (en) * | 2011-11-15 | 2012-03-28 | 西安电子科技大学 | Data center network topology system based on module expansion |
| CN104504189A (en) * | 2014-12-17 | 2015-04-08 | 西北工业大学 | Large-scale structural design method under random excitation |
| CN107026859A (en) * | 2017-03-31 | 2017-08-08 | 西安电子科技大学 | A kind of safe transmission method of privacy cloud medical data |
| JP2018182648A (en) * | 2017-04-20 | 2018-11-15 | 日本電信電話株式会社 | Network designing apparatus and network designing method |
| CN109861863A (en) * | 2019-02-11 | 2019-06-07 | 南方科技大学 | Method and device for determining connection fault of data center, electronic equipment and medium |
-
2020
- 2020-02-17 CN CN202010097925.8A patent/CN111343014B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2157319A1 (en) * | 1994-08-31 | 1996-03-01 | Eiji Oki | Communication network design method and communication equipment |
| CN102394782A (en) * | 2011-11-15 | 2012-03-28 | 西安电子科技大学 | Data center network topology system based on module expansion |
| CN104504189A (en) * | 2014-12-17 | 2015-04-08 | 西北工业大学 | Large-scale structural design method under random excitation |
| CN107026859A (en) * | 2017-03-31 | 2017-08-08 | 西安电子科技大学 | A kind of safe transmission method of privacy cloud medical data |
| JP2018182648A (en) * | 2017-04-20 | 2018-11-15 | 日本電信電話株式会社 | Network designing apparatus and network designing method |
| CN109861863A (en) * | 2019-02-11 | 2019-06-07 | 南方科技大学 | Method and device for determining connection fault of data center, electronic equipment and medium |
Non-Patent Citations (2)
| Title |
|---|
| XIANGYU WANG; JIANFENG MA; YINBIN MIAO; RUIKANG YANG; YIJIA CHAN: "EPSMD: An Efficient Privacy-Preserving Sensor Data Monitoring and Online Diagnosis System", 《IEEE》, 11 October 2018 (2018-10-11), pages 819 - 827 * |
| 杨林等: "组间平衡区组设计的性质及应用", 《数学的实践与认识》, 31 December 2017 (2017-12-31), pages 139 - 148 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111343014B (en) | 2022-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6374202B1 (en) | Processing data signals | |
| CN102693209B (en) | Information processing system | |
| JP3357636B2 (en) | Improved PNNI topology abstraction | |
| Gerstel et al. | The layout of virtual paths in ATM networks | |
| CN107612746A (en) | A kind of method, Torus networks and the routing algorithm of structure Torus networks | |
| Hou et al. | Multi-controller deployment algorithm in hierarchical architecture for SDWAN | |
| JP2003533106A (en) | Communication network | |
| KR102171890B1 (en) | Computing system framework with unified storage, processing, and network switching fabrics incorporating network switches and method for making and using the same | |
| CN105141512A (en) | Unified network configuration and control method supporting packet/circuit mixed exchange network | |
| CN102752207B (en) | Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof | |
| CN111343014B (en) | Data center network topology design method based on combination design | |
| EP0984655A1 (en) | Method for generating the optimal PNNI complex node representations for restrictive costs | |
| CN108768864B (en) | Data center network topology system easy to expand and high in fault tolerance | |
| CN107592218A (en) | A kind of data center network structure of high fault tolerance and strong autgmentability | |
| CN108536555B (en) | Data access method based on BCube (n, b) data center | |
| CN110213162A (en) | Fault-tolerant routing method for large-scale computer system | |
| CN112001141B (en) | Brain network inspired middle-large scale on-die interconnection system comprehensive method | |
| Parhami et al. | Incomplete k-ary n-cube and its derivatives | |
| CN110535791B (en) | Data center network based on prism structure | |
| Zhao et al. | G-update: A group-based update scheme for heterogenous erasure-coded storage systems | |
| CN108768588B (en) | Based on the distributed network coding method and system for merging request | |
| CN111245655A (en) | Intra-network topology structure, construction method and system | |
| Wang et al. | Hybrid-TF: A New Hybrid Interconnection Network Topology for High Performance Computing | |
| Vassoler et al. | Twin datacenter interconnection topology | |
| CN108092807A (en) | A kind of three-dimensional multi-path data central site network topological structure and construction method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |