CN111341262A - Circuit and method for suppressing noise, time sequence control board and display device - Google Patents
Circuit and method for suppressing noise, time sequence control board and display device Download PDFInfo
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- CN111341262A CN111341262A CN202010322642.9A CN202010322642A CN111341262A CN 111341262 A CN111341262 A CN 111341262A CN 202010322642 A CN202010322642 A CN 202010322642A CN 111341262 A CN111341262 A CN 111341262A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Liquid Crystal Display Device Control (AREA)
Abstract
Disclosed herein are a circuit, a method, a timing control board and a display device for suppressing noise. The circuit of suppression noise is connected with power management module's power signal output end, includes: the system comprises a switch control module, a switch module, a load module and a time sequence control module; the input end of the switch control module is connected with the power supply signal output end of the power supply management module, the control end of the switch control module is connected with the control signal output end of the time sequence control module, and the output end of the switch control module is connected with the control end of the switch module and used for outputting a first level signal in a load compensation period under the control of the time sequence control module and outputting a second level signal at other times except the load compensation period; the input end of the switch module is connected with the power signal output end of the power management module, and the output end of the switch module is connected with the load module; and the control module is used for connecting or disconnecting a loop between the power supply signal output end of the power supply management module and the load module under the control of the switch control module. The present document can suppress capacitive noise on a timing control board.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a circuit and a method for suppressing noise, a timing control board, and a display device.
Background
The entire driving circuit of the display panel includes a timing control circuit (TCON _ IC), a gray scale voltage (gamma correction) generation circuit, a DC-DC conversion circuit (Power Management IC, PMIC for short), a source driving (column driving) circuit, a gate driving (row driving) circuit, and the like. Among them, the TCON _ IC, PMIC and gray scale voltage generation circuit are usually fabricated on a separate circuit board, which is called TCON board.
The PMIC passes a 5V or 12V power supply signal through a DC-DC conversion circuit to generate various voltage signals required by a logic driving circuit, such as: DVDD, AVDD, VGL, VCH, and the like. The TCON _ IC converts a Low Voltage Differential Signaling (LVDS) Signal supplied from a front end into a Mini-LVDS or RSDS (Reduced Swing Differential Signal) Signal for a data driving circuit (source driving circuit), and various timing control signals (e.g., STV, CKV, STH, CKH, POL, etc.). The gray scale voltage generating circuit generates a series of pre-distortion voltages with disproportionate amplitude change, and outputs the pre-distortion voltages to the data driving circuit, thereby completing gamma correction of image display.
At present, a ceramic capacitor is commonly used on a timing control board to filter each power supply voltage output by the PMIC. A chip-type Multi-layer Ceramic capacitor (MLCC for short) is a commonly used Ceramic capacitor at present, and is formed by overlapping Ceramic dielectric films printed with electrodes (inner electrodes) in a staggered mode, forming a Ceramic chip through one-time high-temperature sintering, and sealing metal layers (outer electrodes) at two ends of the chip to form a structure body similar to a monolithic body, so that the chip is also called a monolithic capacitor.
However, the ceramic capacitor has an inverse piezoelectric effect, and when a voltage across the ceramic capacitor fluctuates, the ceramic capacitor causes mechanical deformation of the capacitor to generate vibration, and the vibration is transmitted to a Printed Circuit Board (PCB) to form resonance noise.
As the size of the display panel becomes larger, noise generated by vibration of the ceramic capacitor becomes more noticeable.
Disclosure of Invention
The embodiment of the application provides a circuit and a method for suppressing noise, a time sequence control board and a display device, which can suppress capacitance noise on the time sequence control board.
In a first aspect, the present application provides a circuit for suppressing noise, where the circuit for suppressing noise is connected to a power signal output terminal of a power management module, and the circuit includes: the system comprises a switch control module, a switch module, a load module and a time sequence control module; the switch control module includes: the input end, the control end, the output end and the voltage regulating unit; the switch module comprises an input end, a control end, an output end and a switch element; the load module comprises a load; the time sequence control module comprises a control signal output end;
the input end of the switch control module is connected with the power signal output end of the power management module, the control end of the switch control module is connected with the output end of the time sequence control module, the output end of the switch control module is connected with the control end of the switch module, and the voltage regulating unit is used for controlling the output end of the switch control module to output a first level signal in a load compensation period and output a second level signal at other time except the load compensation period under the control of the time sequence control module;
the input end of the switch module is connected with the power signal output end of the power management module, the control end of the switch module is connected with the output end of the switch control module, and the output end of the switch module is connected with the load module; the switch element is used for connecting or disconnecting a loop between a power supply signal output end of the power supply management module and the load module under the control of the switch control module.
In a second aspect, the present application provides a method of suppressing noise, comprising:
the switch control module outputs a first level signal in a load compensation period and outputs a second level signal at other time except the load compensation period under the control of the time sequence control module;
the first level signal can control the switch module to be communicated with a loop between a power supply signal output end of the power supply management module and the load module; the second level signal can control the switch module to disconnect a loop between the power supply signal output end of the power supply management module and the load module.
In a third aspect, the present application provides a timing control board including the above-described circuit for suppressing noise.
In a fourth aspect, the present application provides a display device including the above timing control board.
The embodiment of the application provides a circuit and a method for suppressing noise, a time sequence control board and a display device.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a schematic diagram illustrating the fluctuation of an AVDD power signal outputted from a PMIC in a blanking period according to the related art;
fig. 2 is a schematic structural diagram of a circuit for suppressing noise according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a switch control module according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a switch module according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a load module according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a circuit for suppressing noise according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating the fluctuation of the AVDD power signal outputted from the PMIC during the blanking period after the noise suppression circuit is adopted in the embodiment of the present application.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Unless otherwise defined, technical or scientific terms used throughout the disclosure of the embodiments of the present application shall have the ordinary meaning as understood by those having ordinary skill in the art to which the present application belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The load of the TCON board is a driving element (e.g., transistor, resistor, capacitor, etc.) of all pixels on the display panel. When one frame of image is normally displayed, the TCON panel needs to drive all pixels on the panel to emit light, so that the load is large. However, in the BLANKING period (BLANKING) in which the next frame of image has not yet started after the refresh of one frame of image, the TCON board does not need to drive all the pixels on the panel to emit light, that is, all the pixels on the display panel do not emit light, so that the load of the TCON board jumps and changes from large to small.
As shown in fig. 1, the voltage waveform of the analog power supply signal AVDD (power supply required by the analog circuit part of the driving circuit) output by the power management chip PMIC spikes during the blanking period due to the load jump. The voltage fluctuation of the AVDD causes the inverse piezoelectric effect of each filter capacitor (ceramic capacitor) on the TCON board, and the capacitor generates vibration due to mechanical deformation, and the vibration is transmitted to the printed circuit board to form resonance noise. The larger the display panel size, the more serious the noise caused by the capacitive vibration.
In order to eliminate the capacitance noise of the time sequence control board, the load balancing circuit is added at the power supply signal output end of the power supply management chip PMIC, and the load balancing circuit can compensate the load of the TCON board in the blanking period, so that the load is prevented from jumping, and the noise generated by capacitance vibration is restrained.
The embodiment of the present application provides a circuit for suppressing noise, and fig. 2 is a schematic structural diagram of the circuit for suppressing noise provided in the embodiment of the present application, and as shown in fig. 2, the circuit for suppressing noise provided in the embodiment of the present application is connected to a power signal output terminal of a power management module, and includes: the system comprises a switch control module 1, a switch module 2, a load module 3 and a time sequence control module 4; the switch control module 1 includes: the input end, the control end, the output end and the voltage regulating unit; the switch module 2 comprises an input end, a control end, an output end and a switch element; the load module 3 includes a load; the time sequence control module 4 comprises a control signal output end;
the input end of the switch control module 1 is connected with the power signal output end of the power management module, the control end of the switch control module 1 is connected with the control signal output end of the time sequence control module, the output end of the switch control module 1 is connected with the control end of the switch module 2, and the voltage regulating unit is used for controlling the output end of the switch control module 1 to output a first level signal in a load compensation period and output a second level signal at other times except the load compensation period under the control of the time sequence control module 4;
the input end of the switch module 2 is connected with the power signal output end of the power management module, the control end of the switch module 2 is connected with the output end of the switch control module 1, and the output end of the switch module 2 is connected with the load module 3; the switch element is used for connecting or disconnecting a loop between a power supply signal output end of the power supply management module and the load module 3 under the control of the switch control module 1;
in the above embodiment, load compensation can be performed when a load of the timing control board jumps due to cooperation of the timing control module, the switch module and the load module, so that voltage fluctuation of a power supply signal output by the power supply management module is reduced, and generation of noise by a ceramic capacitor on the timing control board is suppressed.
In an exemplary embodiment, the power signal output of the power management module includes: an analog power supply signal AVDD output terminal, a half-analog power supply signal HAVDD output terminal or a reference voltage power supply signal VCOM output terminal; the power supply signals output by the analog power supply signal AVDD output end and the half-analog power supply signal HAVDD output end can provide power supply for the analog circuit parts of the source electrode driving (column driving) circuit and the gray scale voltage generating circuit; the power supply signal output from the output terminal of the reference voltage power supply signal VCOM can supply power to the analog circuit portion of the gray-scale voltage generation circuit.
In an exemplary embodiment, the timing control module is a timing control chip, and the control signal Output terminal of the timing control module is a General Purpose Input Output (GPIO) port of the timing control chip;
in an exemplary embodiment, the load compensation period is a blanking period. That is, the timing control module controls to connect the loop between the power signal output end of the power management module and the load module 3 in the blanking period, and controls to disconnect the loop between the power signal output end of the power management module and the load module 3 at other times except the blanking period.
In an exemplary implementation manner, fig. 3 is a schematic structural diagram of a switch control module provided in an embodiment of the present application, and as shown in fig. 3, the switch control module provided in the embodiment of the present application includes: the input end, the control end, the output end and the voltage regulating unit; the voltage regulating unit includes: a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1;
the input end of the switch control module 1 is connected with the power supply signal output end of the power supply management module, the control end of the switch control module 1 is connected with the control signal output end of the time sequence control module, and the output end of the switch control module 1 is connected with the control end of the switch module 2;
a first end of the first resistor R1 is connected with an input end of the switch control module, and a second end of the first resistor R1 is connected with an output end of the switch control module;
a first end of the second resistor R2 is connected with an output end of the switch control module, and a second end of the second resistor R2 is connected with a first pole of the first transistor Q1;
a first end of the third resistor R3 is connected with a control end of the switch control module, and a second end of the third resistor R1 is grounded;
a control electrode of the first transistor Q1 is connected with a control end of the switch control module, a first electrode of the first transistor Q1 is connected with a second end of the second resistor, and a second electrode of the first transistor Q1 is grounded;
in an exemplary embodiment, the first transistor is a switching element; the first transistor may be an N-type transistor or a P-type transistor. The first pole of the first transistor is a source electrode, and the second pole of the first transistor is a drain electrode; or, the first pole of the first transistor is a drain, and the second pole of the first transistor is a source.
When the effective trigger level triggering the conduction of the first transistor is at a high level, if the control signal output by the control signal output end of the time sequence control module is a high level signal, the first transistor is driven to be conducted, and if the control signal output by the control signal output end of the time sequence control module is a low level signal, the first transistor is driven to be cut off. When the effective trigger level triggering the first transistor to be conducted is a low level, if the control signal output by the control signal output end of the time sequence control module is a low level signal, the first transistor is driven to be conducted, and if the control signal output by the control signal output end of the time sequence control module is a high level signal, the first transistor is driven to be cut off.
Suppose the voltage of the power signal output by the power signal output end of the power management module is U1。
When the first transistor is conducted, the voltage U of the signal output by the output end of the switch control moduleo1Comprises the following steps:
when the first transistor is cut off, the voltage of the signal output by the output end of the switch control moduleUo1Comprises the following steps:
therefore, the voltage adjusting unit can adjust the signal voltage at the output end of the switch control module under the control of the time sequence control module, and the output end of the switch control module can output a pulse signal with high and low levels changing alternately;
in an exemplary implementation manner, fig. 4 is a schematic structural diagram of a switch module provided in an embodiment of the present application, and as shown in fig. 4, the switch module provided in the embodiment of the present application includes: an input terminal, a control terminal, an output terminal and a switching element; the switching element includes: a second transistor Q2;
the input end of the switch module 2 is connected with the power signal output end of the power management module, the control end of the switch module 2 is connected with the output end of the switch control module 1, and the output end of the switch module 2 is connected with the load module 3;
the gate of the second transistor Q2 is connected to the control terminal of the switch module, the first pole of the second transistor Q2 is connected to the input terminal of the switch module, and the second pole of the second transistor Q2 is connected to the output terminal of the switch module.
In an exemplary embodiment, the second transistor may be an N-type transistor or a P-type transistor. The first pole of the second transistor is a source electrode, and the second pole of the second transistor is a drain electrode; or the first pole of the second transistor is a drain electrode, and the second pole of the second transistor is a source electrode.
When the effective trigger level for triggering the conduction of the second transistor is a high level, if the signal output by the output end of the switch control module is a high level signal, the second transistor is driven to be conducted, and if the signal output by the output end of the switch control module is a low level signal, the second transistor is driven to be cut off. When the effective trigger level for triggering the conduction of the second transistor is a low level, if the signal output by the output end of the switch control module is a low level signal, the second transistor is driven to be conducted, and if the signal output by the output end of the switch control module is a high level signal, the second transistor is driven to be cut off.
When the switching element (the second transistor) in the switching module is turned on, the loop between the power signal output end of the power management module and the load module 3 is connected, and when the switching element (the second transistor) in the switching module is turned off, the loop between the power signal output end of the power management module and the load module 3 is disconnected.
In an exemplary implementation manner, fig. 5 is a schematic structural diagram of a load module provided in an embodiment of the present application, and as shown in fig. 5, the load module provided in the embodiment of the present application includes: a fourth resistor R4; the first end of the fourth resistor R4 is connected with the output end of the switch module, and the second end of the fourth resistor R4 is grounded.
Fig. 6 is a schematic structural diagram of the noise suppression provided in the embodiment of the present application, and as shown in fig. 6, the noise suppression provided in the embodiment of the present application, where the noise suppression circuit is connected to a power signal output end of a power management module, includes: the system comprises a switch control module 1, a switch module 2, a load module 3 and a time sequence control module 4; the switch control module 1 includes: the circuit comprises an input end, a control end, an output end, a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1; the switch module 2 comprises an input end, a control end, an output end and a second transistor Q2; the load module 3 comprises a fourth resistor R4; the time sequence control module 4 comprises a control signal output end;
the input end of the switch control module 1 is connected with the power supply signal output end of the power supply management module, the control end of the switch control module 1 is connected with the control signal output end of the time sequence control module, and the output end of the switch control module 1 is connected with the control end of the switch module 2; a first end of the first resistor R1 is connected with an input end of the switch control module, and a second end of the first resistor R1 is connected with an output end of the switch control module; a first end of the second resistor R2 is connected with an output end of the switch control module, and a second end of the second resistor R2 is connected with a first pole of the first transistor Q1; a first end of the third resistor R3 is connected with a control end of the switch control module, and a second end of the third resistor R1 is grounded; a control electrode of the first transistor Q1 is connected with a control end of the switch control module, a first electrode of the first transistor Q1 is connected with a second end of the second resistor, and a second electrode of the first transistor Q1 is grounded;
the input end of the switch module 2 is connected with the power signal output end of the power management module, the control end of the switch module 2 is connected with the output end of the switch control module 1, and the output end of the switch module 2 is connected with the load module 3; the grid electrode of the second transistor Q2 is connected with the control end of the switch module, the first pole of the second transistor Q2 is connected with the input end of the switch module, and the second pole of the second transistor Q2 is connected with the output end of the switch module;
the first end of the fourth resistor R4 is connected with the output end of the switch module, and the second end of the fourth resistor R4 is grounded.
The power signal output end of the power management module is taken as an AVDD signal output end of the analog power supply as an example, the AVDD signal output end is connected with the circuit for suppressing the noise, the time sequence control module outputs a control signal in a blanking period to drive the switch module to be connected with a loop between the AVDD signal and the load module, so that load compensation is realized, the time sequence control module outputs the control signal in other time except the blanking period to drive the switch module to be disconnected with the loop between the AVDD signal and the load module, and the load of the TCON board is the same as that in the prior art, and the normal display of the display panel is not influenced. As shown in fig. 7, after the circuit for suppressing noise is used, the load of the TCON board is compensated in the blanking period, the fluctuation of the AVDD signal in the blanking period is greatly reduced, and the noise of the ceramic capacitor is suppressed.
The embodiment of the application provides a method for suppressing noise, which comprises the following steps:
the switch control module outputs a first level signal in a load compensation period and outputs a second level signal at other time except the load compensation period under the control of the time sequence control module;
the first level signal can control the switch module to be communicated with a loop between a power supply signal output end of the power supply management module and the load module; the second level signal can control the switch module to disconnect a loop between the power supply signal output end of the power supply management module and the load module.
In an exemplary embodiment, the load compensation period is a blanking period.
In an exemplary embodiment, the power signal output of the power management module includes: an analog power supply signal AVDD output terminal, a half-analog power supply signal HAVDD output terminal or a reference voltage power supply signal VCOM output terminal.
According to the method for suppressing the noise, the load compensation can be carried out in the blanking period through the cooperation of the time sequence control module, the switch module and the load module, the voltage fluctuation of a power supply signal output by the power supply management module is reduced, and therefore the noise generated by a ceramic capacitor on the time sequence control board is suppressed.
The embodiment of the application also provides a time sequence control board which comprises the circuit for suppressing the noise.
In an exemplary embodiment, the timing control board includes one or more circuits to suppress noise;
when the time sequence control board comprises a plurality of circuits for suppressing noise, the circuits for suppressing noise are respectively connected with different power signal output ends of the power management module, and the circuits for suppressing noise are all connected with the same control signal output end of the time sequence control module.
In another embodiment, if there is a margin in the output interface of the timing control module, the noise suppression circuits may be connected to different control signal output terminals of the timing control module.
The time sequence control board has the main function of converting an externally input power supply or signal into a working voltage, a signal and a time sequence required by the integrated circuit so as to drive the display panel.
The embodiment of the application also provides a display device which comprises the time sequence control plate.
The display device may be an organic light emitting display device, or may also be a liquid crystal display device, which is not limited herein. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A circuit for suppressing noise coupled to a power signal output of a power management module, comprising: the system comprises a switch control module, a switch module, a load module and a time sequence control module; the switch control module includes: the input end, the control end, the output end and the voltage regulating unit; the switch module comprises an input end, a control end, an output end and a switch element; the load module comprises a load; the time sequence control module comprises a control signal output end;
the input end of the switch control module is connected with the power signal output end of the power management module, the control end of the switch control module is connected with the output end of the time sequence control module, the output end of the switch control module is connected with the control end of the switch module, and the voltage regulating unit is used for controlling the output end of the switch control module to output a first level signal in a load compensation period and output a second level signal at other time except the load compensation period under the control of the time sequence control module;
the input end of the switch module is connected with the power signal output end of the power management module, the control end of the switch module is connected with the output end of the switch control module, and the output end of the switch module is connected with the load module; the switch element is used for connecting or disconnecting a loop between a power supply signal output end of the power supply management module and the load module under the control of the switch control module.
2. The circuit for suppressing noise of claim 1, wherein:
the power supply signal output end of the power supply management module comprises: an analog power signal output terminal, a half-analog power signal output terminal or a reference voltage power signal output terminal.
3. The circuit for suppressing noise of claim 1, wherein:
the load compensation period is a blanking period.
4. The circuit for suppressing noise of claim 1, wherein:
the voltage regulating unit includes: the circuit comprises a first resistor, a second resistor, a third resistor and a first transistor;
the first end of the first resistor is connected with the input end of the switch control module, and the second end of the first resistor is connected with the output end of the switch control module;
the first end of the second resistor is connected with the output end of the switch control module, and the second end of the second resistor is connected with the first pole of the first transistor;
the first end of the third resistor is connected with the control end of the switch control module, and the second end of the third resistor is grounded;
the control electrode of the first transistor is connected with the control end of the switch control module, the first electrode of the first transistor is connected with the second end of the second resistor, and the second electrode of the first transistor is grounded.
5. The circuit for suppressing noise of claim 1, wherein:
the switching element includes: a second transistor;
the grid electrode of the second transistor is connected with the control end of the switch module, the first pole of the second transistor is connected with the input end of the switch module, and the second pole of the second transistor is connected with the output end of the switch module.
6. The circuit for suppressing noise of claim 1, wherein:
the load includes: a fourth resistor;
the first end of the fourth resistor is connected with the output end of the switch module, and the second end of the fourth resistor is grounded.
7. A method of suppressing noise using the noise suppressing circuit of any of claims 1-6, comprising:
the switch control module outputs a first level signal in a load compensation period and outputs a second level signal at other time except the load compensation period under the control of the time sequence control module;
the first level signal can control the switch module to be communicated with a loop between a power supply signal output end of the power supply management module and the load module; the second level signal can control the switch module to disconnect a loop between the power supply signal output end of the power supply management module and the load module.
8. A timing control board, comprising: the circuit for suppressing noise of any of claims 1-6.
9. The timing control board of claim 8, wherein:
the time sequence control board comprises one or more circuits for suppressing noise;
when the time sequence control board comprises a plurality of circuits for suppressing noise, the circuits for suppressing noise are respectively connected with different power signal output ends of the power management module, and the circuits for suppressing noise are all connected with the same control signal output end of the time sequence control module.
10. A display device, comprising: the timing control board of claim 8 or 9.
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