CN111341247A

CN111341247A - Drive chip, LED lamp and LED display screen

Info

Publication number: CN111341247A
Application number: CN201910700232.0A
Authority: CN
Inventors: 尤金; 林谊
Original assignee: GWS Technology Co Ltd
Current assignee: GWS Technology Co Ltd
Priority date: 2019-07-31
Filing date: 2019-07-31
Publication date: 2020-06-26
Also published as: CN114898700A; CN114898700B; CN114664239A

Abstract

In order to solve the problem that the LED display screen in the prior art is complex in wiring or the LED lamps between adjacent rows have color difference, the invention provides a driving chip, an LED lamp and an LED display screen. The invention provides an LED lamp, which further comprises a data direction judging and switching module arranged in the driving chip or outside the driving chip and connected with the driving module; according to the LED lamp provided by the invention, the two signal ports can input and output data signals without distinguishing data directions. The data direction of the first signal end and the data signal direction of the second signal end are judged through the data direction judging and switching module, the input port and the output port of the data signals are automatically switched, and the wiring complexity is greatly reduced. The LED lamps between adjacent rows or columns do not produce color differences.

Description

Drive chip, LED lamp and LED display screen

Technical Field

The application belongs to the LED field, and particularly relates to an LED lamp with a built-in drive IC.

Background

LED display panels are known, which are formed by arranging LED lamps in an array, and a more advanced way in the market is to use LED lamps with built-in driving ICs to make the LED display panels. As shown in fig. 1, the LED lamp 100 ' includes a driver IC 2 ', where the driver IC 2 ' is provided with a plurality of signal ports and a power port; the power supply port comprises an anode port and a cathode port, and is connected with an external power supply to form a power supply loop for supplying power to the drive IC 2' and the light-emitting chip; the signal port comprises a signal input end and a signal output end; the control signal enters the signal input end from the control module of the LED display screen or the upper LED lamp 100 ', and the control signal is transmitted to the next LED lamp 100' from the signal output end. Control ports (not marked in the figure) are arranged in the LED chip and are respectively connected to three light-emitting chips 1 '(a blue light-emitting chip, a green light-emitting chip and a red light-emitting chip), and the three light-emitting chips 1' are shared by an anode (or a cathode).

When the LED lamp 100 'is arranged in an array to form the LED display screen 1000', the signal port thereof has a signal input end and a signal output end; the control signal is required to always enter from the signal input end and output from the signal output end; as shown in fig. 2, if the beads of all the LED lamps 100 ' are arranged in the same manner, taking the control signal as transverse conduction (or column longitudinal conduction) as an example, the signal lines of the LED lamps 100 ' in the same row are sequentially conducted, and the LED lamps 100 ' in adjacent rows are connected end to end through the signal lines. Specifically, the LED lamps 100 'in each row are connected in series from left to right, and when the last LED lamp in each row is reached, the signal output terminal of the last LED lamp 100' is connected in series with the signal input terminal of the next row through a signal line, and conduction is resumed. The disadvantage of this method is that the signal wires connected end to end between adjacent rows of LED lamps 100' need to be wound for a long distance, which increases the complexity of wiring. In particular, in the field of transparent LED display 1000', the wiring design requirements are very simple, routing wires from the beginning adds complexity to the wiring design and makes placement of other functions, such as conductive traces, difficult.

To make wiring simpler, applicants installed the LED lamps 100' in adjacent rows rotated 180 degrees in reverse, and made the rows in front-to-back or in back-to-back. For example, odd rows are installed in the forward direction, and even rows are installed in the reverse direction; the signal input end of the odd number row is on the left, the signal output end is on the right, and the control signal is transmitted from left to right; on the contrary, in the even rows, the signal input end is on the right, the signal output end is on the left, and the control signal is transmitted from right to left; however, this method has a problem that the arrangement directions of the three light emitting chips in the adjacent rows of LED lamps 100 ' are opposite, which causes a difference in the left and right viewing angles of the adjacent rows of LED lamps 100 ' after the LED display panel 1000 ' is imaged.

Disclosure of Invention

In order to solve the problem that the LED display screen in the prior art is complex in wiring or the LED lamps between adjacent rows have color difference, the invention provides a driving chip, an LED lamp and an LED display screen.

The first aspect of the invention provides a driving chip, wherein a driving module is arranged in the driving chip, and the driving chip is connected with a signal port and a power port; the power supply port is used for providing power supply for the driving chip; the signal port is used for inputting and outputting data signals;

the driving chip also comprises a data direction judging and switching module connected with the driving module;

the signal ports comprise a first signal port and a second signal port;

the data direction judging and switching module is connected with the first signal port and the second signal port and used for judging the data signal input direction of the first signal port and the second signal port, automatically switching the signal port of the data signal input and the signal port of the data signal output, leading in the data signal from the input signal port, transmitting the data signal to the driving module, receiving the data signal returned from the driving module, and outputting the data signal from the signal port of the data output.

According to the driving chip provided by the invention, the connected signal ports can input and output data signals without distinguishing data directions. The data direction judging and switching module judges the data signal direction of the first signal end and the second signal end, identifies the input port and the output port of the data signal, inputs the data signal from the input port of the data, outputs the data signal to the driving module, receives the data signal returned from the driving module, and outputs the data signal from the output port of the data. When the LED lamp wiring device is used in LED display screens and other equipment, the arrangement or wiring of each LED lamp is not required to be specially designed, and the head parts of the LED lamps in adjacent rows (or adjacent columns) are connected in series or the tail parts of the LED lamps in adjacent rows (or adjacent columns) are connected in series under the condition that the arrangement direction of the LED lamps is not required to be changed between the rows (or between the columns), so that the mode that the original wiring needs to be connected end to end for winding and layout is avoided, and the wiring complexity is greatly reduced. The LED lamps between adjacent rows or columns do not produce color differences.

Further, the driving module comprises a data input port and a data output port;

the data direction judging and switching module comprises a data input circuit, a data output circuit and a watchdog;

the data input circuit comprises two input branches connected to the data input port, and the two input branches are respectively connected to the first signal terminal and the second signal terminal;

the data output circuit comprises two output branches connected to the data output port, and the two output branches are respectively connected to the first signal end and the second signal end;

the watchdog is used for judging the data signal input direction in the first signal terminal and the second signal terminal, and controlling the selection of the input branch circuit from the data input circuit and the selection of the output branch circuit from the data output circuit, so that the data signal is always input from one signal port and output from the other signal port.

Further, the data input circuit includes a data direction selector; the data direction selector is respectively connected with the first signal end, the second signal end, the watchdog and a data input port of the driving module; the data direction selector is connected with the first signal end and the second signal end to form two input branches, and the two input branches are used for switching and connecting signal ports of data signal input according to a control signal sent by the watchdog, selecting the input branches and outputting the data signal from the data direction selector to a data input port of the driving module;

the data output circuit is connected to a data output port of the driving module, and comprises two output branches provided with switching devices, the two output branches are respectively connected to the first signal port and the second signal port, and the two switching devices always work in an inverted state;

the watchdog is directly or indirectly connected with the data input port, the data output port, the data direction selector and the switching device on the data output circuit, and is used for acquiring signals of the data input port and the data output port, and identifying a signal port for data signal input and a signal port for data signal output; and sending a control signal to the data direction selector and two switching devices on the data output circuit, wherein one of the lines between the two switching devices and the watchdog is provided with an inverter.

Furthermore, the data direction selector comprises a first signal port, a second signal port, a data output port and a selection port;

the first signal end is connected with the first signal port through a first diode, and the second signal end is connected with the second signal port through a second diode; the data output port is connected to the data input port of the driving module;

a data output port of the driving module is connected to the first signal end through a first switching device and connected to the second signal end through a second switching device;

the watchdog comprises an input signal acquisition port, an output signal acquisition port and a control port;

the input signal acquisition port is connected to a first signal port of the data direction selector; the output signal acquisition port is connected to a data output port of the driving module; the control port is respectively connected to the selection port of the data direction selector and the control ends of the first switching device and the second switching device, and a phase inverter is arranged on the control port and the control end of the second switching device; alternatively, the first and second electrodes may be,

the input signal acquisition port is connected to a second signal port of the data direction selector; the output signal acquisition port is connected to a data output port of the driving module; the control port is respectively connected to the selection port of the data direction selector, the control ends of the first switch device and the second switch device, and a phase inverter is arranged on the control port and the control end of the first switch device.

Further, the watchdog comprises a signal monitoring module and a counter;

the signal monitoring module is connected with the input signal acquisition port and the output signal acquisition port and is provided with a monitoring output port; the logic judgment is carried out according to the signals collected by the input signal collection port and the output signal collection port, and monitoring signals are output from the monitoring output port; if the specific logic is compounded, outputting a monitoring signal to the counter to be low level 0, and resetting the counter; otherwise, outputting a monitoring signal to the counter to be a high level 1, and enabling the counter to count;

the counter is used for counting within a preset time, if the counting reaches or exceeds a certain preset value, the output control signal is judged to be a high level 1, and otherwise, the output control signal is a low level 0.

Further, the logic judgment rule of the signal monitoring module is as follows: when the signals collected by the input signal collection port and the output signal collection port are not equal, the signal collected by the input signal collection port is low level 0, and the signal collected by the output signal collection port is high level 1, the monitoring output port outputs a monitoring signal which is low level 0; and the other monitoring output port outputs a monitoring signal with a high level 1.

Further, the frequency of the signal collected by the signal monitoring module is far greater than the frequency of the data signal;

the data signals are input and output from the driving module by adopting a first-in first-out rule; the preset time is longer than the time for inputting and outputting the data signal from the driving module.

Further, the driving module comprises a logic circuit module and an analog circuit module;

the logic circuit module is used for receiving data signals input by the data input port, extracting control signals from the data signals, transmitting the control signals to the analog circuit module, and outputting the data signals from the data output port;

the analog circuit module is used for generating a plurality of driving signals corresponding to the number of the light-emitting chips according to the data signals and driving the corresponding light-emitting chips.

Further, the data input circuit comprises a first AND gate, a second AND gate and an OR gate; the first signal end is connected to one input end of the first AND gate through a fourth diode to form a first input branch; the second signal end is connected to one input end of the second AND gate through a fifth diode to form a second input branch; the output ends of the first AND gate and the second AND gate are connected to the input end of an OR gate, and the output end of the OR gate is connected to the data input port;

the data output circuit comprises a first output branch and a second output branch, and the first output branch is connected between a first signal end and a data output port through the third switching device; the second output branch is connected between the second signal end and the data output port through the fourth switching device;

the watchdog comprises a control input port and a control output port, the control input port is connected to the output end of a third AND gate, one input end of the third AND gate is connected to the data output port, and the other input end of the third AND gate is connected to the first signal end through a second NOT gate; the control output port is connected to the other input end of the second AND gate and the control end of the third switching device, and is connected to the other input end of the first AND gate and the control end of the fourth switching device through the first NOT gate.

The invention provides an LED lamp in a second aspect, which comprises a driving chip, a light-emitting wafer, a signal port and a power port, wherein a driving module is arranged in the driving chip; the power supply port is used for providing power supply for the circuit in the LED lamp; the signal port is used for inputting and outputting data signals; the light-emitting wafer is connected to the driving chip and driven by the driving module;

the signal port comprises a first signal end and a second signal end;

the LED lamp also comprises a data direction judging and switching module which is arranged in the driving chip or outside the driving chip and is connected with the driving module;

the data direction judging and switching module is connected with the first signal end and the second signal end and used for judging the data signal input direction of the first signal end and the second signal end, starting to switch a signal port for inputting and outputting the data signal, leading in the data signal from the input signal port and transmitting the data signal to the driving module, receiving the data signal returned from the driving module, and outputting the data signal from the signal port for outputting the data.

According to the LED lamp provided by the invention, the two signal ports can input and output data signals without distinguishing data directions. The data direction judging and switching module judges the data signal direction of the first signal end and the second signal end, identifies the input port and the output port of the data signal, inputs the data signal from the input port of the data, outputs the data signal to the driving module, receives the data signal returned from the driving module, and outputs the data signal from the output port of the data. When the LED lamp wiring device is used in LED display screens and other equipment, the arrangement or wiring of each LED lamp is not required to be specially designed, and the head parts of the LED lamps in adjacent rows (or adjacent columns) are connected in series or the tail parts of the LED lamps in adjacent rows (or adjacent columns) are connected in series under the condition that the arrangement direction of the LED lamps is not required to be changed between the rows (or between the columns), so that the mode that the original wiring needs to be connected end to end for winding and layout is avoided, and the wiring complexity is greatly reduced. The LED lamps between adjacent rows or columns do not produce color differences.

Further, the data direction judging and switching module is arranged in the driving chip.

Further, the driving module comprises a data input port and a data output port;

Further, the watchdog comprises a signal monitoring module and a counter;

The invention provides an LED display screen and the LED lamp.

According to the LED display screen provided by the invention, the LED lamps which are improved and innovated by the application are arranged in the LED display screen in an array mode, so that the arrangement or wiring of the LED lamps is not required to be specially designed, and the head part or the tail part of the LED lamps are connected in series between adjacent rows (or adjacent columns) under the condition that the arrangement direction of the LED lamps is not required to be changed between the rows (or between the columns), so that the mode that the original wiring needs to be connected end to end for winding and layout is avoided, and the wiring complexity is greatly reduced. The LED lamps between adjacent rows or columns do not produce color differences.

Further, the LED lamps form an LED array, and the LED arrays are arranged in an array mode in the same direction.

Further, the system also comprises a data control module;

the data control module is provided with a plurality of first data ports and second data ports; and part of the LED light string of the LED array is connected between the first data port and the second data port.

Furthermore, the array formed by the LED lamps connected in series between the first data port and the second data port is divided into a plurality of rows or a plurality of columns to be connected in series, and the head parts or the tail parts of the LED lamps between the adjacent rows or the adjacent columns are connected.

Furthermore, the data control module comprises two physical network ports, an FPGA and a memory;

the FPGA comprises a data acquisition and transmission module, a first output module, a second output module and a broken circuit monitoring module;

the data acquisition and transmission module is connected with the two physical network ports and the memory and is used for acquiring data packets, sending the data packets, acquiring data signals from the data packets and storing the data signals into the memory;

the first output module is used for calling the data signals stored in the memory and sending the data signals to the corresponding LED lamps connected in series through the first data port;

the second output module is used for reversely calling the data signals stored in the memory as backup signals and sending the backup signals to the corresponding LED lamps connected in series through the second data port;

a backup switch device is arranged between the second output module and the second data port and used for controlling the second output module to send a backup signal to the outside;

the circuit break monitoring module is connected to the control end of the backup switch device and the second data port through a third diode, and is used for collecting data of the second data port and outputting a backup control signal to the control end of the backup switch device.

The first output module, the second output module and the open circuit detection module are arranged in the FPGA in the data control module, so that data signals can be input to the lamp groups in series connection of the corresponding LED lamps in the forward direction through the first output module, and when the LED lamps in the lamp groups in series connection break circuit due to faults, the open circuit monitoring module can monitor the state of the second data port and judge that no data signal is received; at this time, the backup switching device can be controlled to be turned on, so that the backup switching device sends a reverse backup signal to the outside through the second output module. And the LED lamps behind the failed LED lamp can still work normally.

Drawings

FIG. 1 is a schematic diagram of a circuit framework of an LED lamp provided in the prior art;

FIG. 2 is a schematic diagram of a circuit frame of an LED display screen provided in the prior art;

FIG. 3 is a schematic diagram of another prior art LED display circuit frame;

fig. 4 is a schematic view of a package structure of an LED lamp according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an LED lamp circuit framework provided in an embodiment of the present invention;

FIG. 6a is a schematic diagram of a further refined LED lamp circuit framework provided in an embodiment of the present invention;

FIG. 6b is a schematic diagram of another further refined LED lamp circuit framework provided in an embodiment of the present invention;

FIG. 7 is a waveform diagram of the absence of a signal in both signal terminals;

FIG. 8 is a schematic diagram showing signal waveforms when signals are input to two signal terminals;

FIG. 9 is a schematic diagram of the acquisition clocks of two signal acquisition ports in a watchdog;

FIG. 10 is a schematic diagram of the internal circuit framework of the watchdog;

FIG. 11 is a truth table for a signal monitoring module in a watchdog;

FIG. 12 is a schematic illustration of a counter counting in a watchdog;

FIG. 13 is a schematic diagram of a watchdog in which the counter count exceeds a set value;

FIG. 14 is a schematic diagram of a circuit frame of an LED display screen according to an embodiment of the present invention;

fig. 15 is a schematic diagram of a control signal output by a watchdog when an LED display screen provided in an embodiment of the present invention is initially powered on for less than 200 microseconds;

FIG. 16 is a schematic diagram of control signals output by the watchdog in each LED lamp after the LED display screen is powered on for more than a predetermined time (200 microseconds) in accordance with an embodiment of the present invention;

fig. 17 is a schematic diagram of control signals output by the watchdog in each LED lamp after the LED display screen starts inputting data from the left side of the first row according to the embodiment of the present invention;

FIG. 18 is a schematic control diagram of an LED display screen provided in accordance with an embodiment of the present invention;

FIG. 19 is a detailed schematic diagram of the data control module provided in FIG. 18.

Wherein, the reference numbers in the background art are as follows:

1', a light emitting wafer; 2', a drive IC; 100', LED lamps; 1000', an LED display screen;

the reference numerals in the detailed description of the invention are as follows:

1000. an LED display screen;

100. an LED lamp; 100a, a first signal terminal; 100b, a second signal terminal; 100c, a first power supply terminal; 100d, a second power supply terminal;

1. a light emitting chip; 2. a driving chip;

21. a drive module; 20. a data direction judging and switching module;

210. a logic circuit module; 211. an analog circuit module;

200. a watchdog; 201. a control port; 202. an output signal acquisition port; 203. inputting a signal acquisition port; 204. an inverter; 205. a data direction selector; 206. a first diode; 207. a first switching device; 208. a second diode; 209. a second switching device; DI. A data input port; DO, data output port;

2001. a signal monitoring module; 2002. a counter; 2003. monitoring an output port;

300. a data control module; 300a, a first data port; 300b, a second data port; 301. an FPGA; 302. SDRAM; 303. a first physical network port; 304. a second physical network port; 3011. a first output module; 3012. a second output module; 3013. a data acquisition and transmission module; 3014. a backup switching device; 3015. An open circuit monitoring module; 3016. a third diode;

401. a fourth diode; 402. a third switching device; 403. a first AND gate; 404. an OR gate; 405. a second AND gate; 406. a first not gate; 407. a second not gate; 408. a third AND gate; 409. a fifth diode; 410. a fourth switching device; 222. a control output port; 333. and a control input port.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1

This example will specifically explain the modification of the LED lamp 100 and the driving chip 2 disclosed in the present invention. The driving chip 2 may be protected as a separate protection body, which is specifically explained in conjunction with the LED lamp 100 herein, but it is not meant to protect only the LED lamp 100 and not the driving chip 2. The description in this example is also sufficient to support the technical solution of the driver chip.

The mechanical structure of the LED lamp 100 disclosed in this embodiment is shown in fig. 4, and includes a Driving chip 2(Driving IC), a light emitting chip 1, a signal port, and a power port; usually, if the lamp beads are prepared, the lamp beads are usually packaged by a support, but in the present embodiment, the lamp beads do not necessarily need to be packaged in practical application, and the lamp beads can be directly used in the LED display 1000 by COB (Chip On board, chinese name) or COG (Chip On Glass, chinese name) manner, so that the inventive concept of the present application can be realized only by the core component driving Chip 2, the light emitting Chip 1, and the improved and innovative data direction determining and switching module 20 of the present application. The LED lamp 100 need not be packaged in the form of a bead in the present application. The basic structure of the LED lamp 100 is known, and therefore, the details of the basic structure in the LED lamp 100 are not described, but only how to add a new data direction determining and switching module 20 in the driving chip 2 (or outside the driving chip 2 in the LED lamp 100) in the present application is described.

The power supply port is used for supplying power to the circuit in the LED lamp 100, namely supplying power to the driving chip 2 and the light-emitting wafer 1; the signal port is used for inputting and outputting data signals; the signal port in this example includes a first signal terminal 100a and a second signal terminal 100 b; the power supply ports include a first power supply terminal 100c and a second power supply terminal 100 d; in this example, for convenience of illustration, the first signal terminal 100a is disposed on the left side, and the second signal terminal 100b is disposed on the right side; a data signal can be input from the first signal terminal 100a and output from the second signal terminal 100b, wherein the first signal terminal 100a is used as a signal port for inputting the data signal, and the second signal terminal 100b is used as a signal port for outputting the data signal. Of course, the data signal may be input from the second signal terminal 100b and output from the first signal terminal 100a, in which case the second signal terminal 100b is used as the signal port for inputting the data signal, and the first signal terminal 100a is used as the signal port for outputting the data signal. In this example, the first power terminal 100c is a negative (or ground) terminal VSS, and the second power terminal 100d is a positive (VDD) terminal.

As shown in fig. 5, a Driving Module 21(Driving Module, DM for short) is disposed in the Driving chip 2; the light emitting wafer 1 is connected to the driving chip 2 and driven by the driving module 21; in this example, the LED lamp 100 further includes a data direction determining and switching module 20 disposed in the driving chip 2 and connected to the driving module 21; alternatively, it is also conceivable to arrange the data direction determination and switching module 20 outside the driver chip 2. Of course, as a preferable mode, the data direction determination and switching module 20 connected to the driving module 21 is integrated in the driving chip 2 to further reduce the size of the LED lamp 100, which is more preferable. If the data direction judging and switching module 20 is arranged outside the driving chip 2, the function of the driving chip 2 is realized through the analog circuit, which has the advantages that the driving chip 2 does not need to be changed, but the driving chip 100 has new requirements, and the analog circuit is arranged outside the driving chip 2 to realize the function, so that the structure is more complicated, and the size of the LED lamp 100 can be increased.

The Data Direction determining and switching Module 20(Data Direction Module & Switch Module, DDJSM for short) is connected to the first signal terminal 100a and the second signal terminal 100b, and is configured to determine a Data input Direction of the first signal terminal 100a and the second signal terminal 100b, automatically Switch a signal port to which the Data signal is input and a signal port to which the Data signal is output, introduce the Data signal from the input signal port and transmit the Data signal to the driving Module 21, receive the Data signal returned from the driving Module 21, and output the Data signal from the signal port to which the Data signal is output.

The specific implementation form of the data direction determining and switching module 20 is not particularly limited. It is sufficient that the data input direction can be determined, the signal port from which the data signal is input is identified, the data signal is input from the identified signal port from which the data is input, and the data signal is output from the data output port in the data direction determining and switching module 20 after passing through the driving module 21.

As a preferred mode, this example shows a preferred implementation manner of the LED lamp 100 data direction judging and switching Module 20 and the driving Module 21, as shown in fig. 6a, wherein the driving Module 21 includes a data input port di (datainput) and a data output port do (data output), and includes a Logic Circuit Module 210(Logic Circuit Module) and an Analog Circuit Module 211(Analog Circuit Module) inside; the logic circuit module 210 is configured to receive a data signal input from the data input port DI, extract a control signal from the data signal, transmit the control signal to the analog circuit module 211, and output the data signal from the data output port; the analog circuit module 211 is configured to generate a plurality of driving currents corresponding to the number of the light emitting chips 1 according to the data signal, so as to drive the corresponding light emitting chips 1, and the three light emitting chips 1 are connected to the common cathode.

The light emitting chip 1 in this example includes 3 chips, i.e., a blue light emitting chip (B), a green light emitting chip (G), and a red light emitting chip (R).

In this example, the data direction determining and switching module 20 includes a data input circuit, a data output circuit, and a watchdog 200(Watching Dog, abbreviated as WD);

the data input circuit comprises two input branches connected to the data input port DI, and the two input branches are respectively connected to the first signal terminal 100a and the second signal terminal 100 b;

the data output circuit comprises two output branches connected to the data output port, and the two output branches are respectively connected to the first signal terminal 100a and the second signal terminal 100 b;

the watchdog 200 is configured to determine an input direction of a data signal in the first signal terminal 100a and the second signal terminal 100b, and control selection of an input branch from the data input circuit and selection of an output branch from the data output circuit, so that the data signal is always input from one signal port and output from the other signal port.

The logic of the above-mentioned switching device is that when the control terminal or the enable terminal inputs 0, the signal is not allowed to pass, for example, when the control terminal or the enable terminal inputs 1, the signal is allowed to pass (some switching devices may also be set to allow the signal to pass when 0 is input, and the signal is not allowed to pass when 1 is input). For example, the switching device may be a Three-state gate (tri-state gate). Tri-state means that its output can be either a normal high level (logic 1) or low level (logic 0) of a typical binary logic circuit, but also can remain in a characteristic high impedance state (Hi-Z). When the circuit is in a high impedance state, the output resistance is very large, which is equivalent to an open circuit and has no logic control function. The tri-state gates have a control enable terminal (in this example, a control terminal for short) to control the on/off of the gate circuit. A device that can have these three states is called a tristate gate (or tristateable device). When the control terminal input is effective, the tri-state gate presents the normal output of '0' or '1'; when the control terminal input is invalid, the tri-state gate gives a high-impedance output.

Specifically, the data input circuit includes a data direction selector 205, and the data direction selector 205 is respectively connected to the first signal terminal 100a, the second signal terminal 100b, the watchdog 200, and the data input port DI of the driving module 21 to form two input branches connected to the data input port DI of the driving module 21, and is configured to switch the data signal input port according to a control signal sent by the watchdog 200, and output a data signal from the selector to the data input port DI of the driving module 21. Specifically, for the sake of distinction, the input branch connecting the first signal terminal 100a and the data direction selector 205 is referred to as a first input branch; the output branch connecting the second signal terminal 100b and the data direction selector 205 is referred to as a second output branch;

the data output circuit is connected to the data output port DO of the driving module 21, and includes two output branches provided with switching devices, which are respectively connected to the first signal terminal 100a and the second signal terminal 100b, and for the sake of distinction, the output branch connected to the first signal terminal 100a is referred to as a first output branch; the output branch connected with the second signal terminal 100b is called a second output branch; the two switching devices always work in an inverted state; the two switching devices in this example are designated as a first switching device 207 and a second switching device 209, respectively. The switching device connected to the first signal terminal 100a is a first switching device 207, and the switching device connected to the second signal terminal 100b is a second switching device 209. Because the two switching devices always work in the reverse phase state, the two output branches always select one to output.

The watchdog 200 is connected to the data input port DI, the data output port DO, the data direction selector 205 and the switching device on the data output circuit, and is used for collecting signals of the data input port DI and the data output port DO, and identifying a port for inputting and outputting a data signal; and sends control signals to the data direction selector 205 and the two switching devices on the data output circuit; an inverter 204 is alternatively provided in the line between the two switching devices and the watchdog 200.

The input branches and the output branches are always arranged so that a data signal is input from the input branch to which one port is connected and output from the output branch to which the other port is connected. That is, if a data signal is input to the data input port DI of the driving module 21 from the first input branch connected to the first signal terminal 100a, the data signal is output from the data output port DO of the driving module 21 from the second output branch connected to the second signal terminal 100 b. On the contrary, if a data signal is input into the data input port DI of the driver module 21 from the second input branch connected to the second signal terminal 100b, the data signal output from the data output port DO of the driver module 21 is output from the first output branch connected to the first signal terminal 100 a.

Further, the data direction selector 205 includes a first signal port, a second signal port, a data output port DO and a selection port;

the first signal terminal 100a is connected to the first signal port through a first diode 206, that is, the first input branch is provided with the first diode 206, and the second signal terminal 100b is connected to the second signal port through a second diode 208, that is, the second input branch is provided with the second diode 208; the data output port DO is connected to the data input port DI of the driving module 21;

the data output port of the driving module 21 is connected to the first signal terminal 100a through a first switching device 207, and is connected to the second signal terminal 100b through a second switching device 209; that is, the first output branch is provided with a first switching device 207; a second switching device 209 is arranged on the second output branch;

the watchdog 200 comprises an input signal acquisition port 203, an output signal acquisition port 202 and a control port 201;

the input signal acquisition port 203 is connected to a first signal port of the data direction selector 205; the output signal acquisition port 202 is connected to a data output port of the driving module 21; the control port 201 is connected to the selection port of the data direction selector 205, the control terminals of the first switching device 207 and the second switching device 209, respectively, and an inverter 204 is disposed on the control terminals of the control port 201 and the second switching device 209.

The above inverter 204 is provided on the second switching device 209 because the input signal collecting port 203 is connected on the first input branch, and if the input signal collecting port 203 is connected on the second input branch, it is conceivable to provide the inverter 204 on the first switching device 207. That is, the input signal collection port 203 is connected to the second signal port of the data direction selector 205; the output signal acquisition port 202 is connected to a data output port of the driving module 21; the control port 201 is connected to the selection port of the data direction selector 205, the control terminals of the first switching device 207 and the second switching device 209, respectively, and an inverter 204 is disposed on the control ports 201 and the control terminals of the first switching device 207.

The design is designed to make the input and output of the data signal conform to the following result: when the data signal is input from the first input branch, the data signal is output from the second output branch; or when the data signal is input from the second input branch, the data signal is output from the first output branch.

To explain the working principle of the watchdog 200 in the present application, the data signal and the principle of data acquisition by the watchdog in the present application are explained first.

As shown in fig. 7, it shows a waveform diagram of the first signal terminal 100a and the second signal terminal 100b if no signal is inputted; since pull-up resistors (not shown) are provided in the first signal terminal 100a and the second signal terminal 100b, the signals of the first signal terminal 100a and the second signal terminal 100b are always output to a high level 1 when no signal is input.

As shown in fig. 8, this figure shows waveforms when data signals are input or output in the first signal terminal 100a and the second signal terminal 100b, if any. In the field of LED display, it is common to use a data signal with a frequency of 1.6 mhz (Hz), that is, a signal period of T625 ns (chinese name: nanosecond; english name: nanosecond). In the waveform diagram, the duty ratio from the high level to the low level in one period is 70% (about 438ns), if the example is in one signal period), it indicates that the signal characterized in one signal period is high level 1, i.e. the data of the data bit is 1. If the duty cycle in a signal period is 30% (about 187ns), it indicates that the signal characterized in a signal period is low level 0, i.e. the data of the data bit is 0. The data signal is shifted into the data Input port DI of the driving module 21 in a First-in First-out queue (FIFO for short; First Input First Output for full), and is shifted and Output from the data Output port DO.

However, when the watchdog 200 performs signal acquisition, the clock for acquiring signals is set as shown in fig. 8, the acquisition frequency is set to be much higher than the frequency of the data signal, the acquisition frequency is 100MHz, which is much higher than the frequency of the data signal, and the clock period for signal acquisition is T0-10 ns, which is 62.5T 0. That is, the watchdog 200 will collect 62.5 times in a signal period of a data signal, and if there is no signal transmission in the first signal terminal 100a or the second signal terminal 100b, the data collected by the watchdog 200 will always be high level 1. If there is a data signal beginning to flow, the watchdog 200 must collect a part of the high level 1 and a part of the low level 0 in the collected signal within one signal period. Because the input signal acquisition port 203 and the output signal acquisition port 202 respectively acquire input data signals and output data signals, and because of the first-in first-out queuing mode adopted during data transmission, the input signal acquisition port 203 and the output signal acquisition port 202 are not necessarily equal. In this way, as long as the low level 0 is acquired from the input signal acquisition port 203, it indicates that data has started to be input.

Specifically, as shown in fig. 10, an embodiment of the watchdog 200 is explained below, where the watchdog 200 includes a Signal Detection Module 2001(Signal Detection Module) and a Counter 2002 (Counter);

the signal monitoring module 2001 is connected with the input signal acquisition port 203 and the output signal acquisition port 202 and is provided with a monitoring output port 2003; it carries on logic judgment according to the signal collected by the input signal collection port 203 and the output signal collection port 202, and outputs the monitoring signal from the monitoring output port 2003; if the specific logic is combined, the monitoring signal is output to the counter 2002 as low level 0, so that the counter 2002 is reset; otherwise, outputting the monitoring signal to the counter 2002 as high level 1, so that the counter 2002 counts;

the counter 2002 is configured to count within a preset time, and if the count reaches or exceeds a preset value, it is determined that the output control signal is at a high level 1, otherwise, the output control signal is at a low level 0.

The watchdog 200 during operation keeps incrementing the counter 2002, for example, when the default setting preset time is 200 μ S (microseconds), the counter 2002 increments to a preset value "a", when the cumulative count of the counter 2002 reaches a, the cumulative count continues to be a, and the control signal output of the watchdog 200 is at high level 1, but when the value of the counter 2002 is less than a, the control signal output of the watchdog 200(WD) is at low level 0.

As shown in the table of fig. 11, the logic determination rule of the signal monitoring module 2001 is as follows: the logic judgment rule of the signal monitoring module 2001 is as follows: when the signals acquired by the input signal acquisition port 203 and the output signal acquisition port 202 are not equal, the signal acquired by the input signal acquisition port 203 is at a low level 0, and the signal acquired by the output signal acquisition port 202 is at a high level 1, the monitoring output port 2003 outputs a monitoring signal at a low level 0; otherwise, the monitor output port 2003 outputs a monitor signal of high level 1.

That is, when the input signal acquisition port 203 is 0 and the output signal acquisition port 202 outputs 1, the monitoring output port 2003 outputs a low level of 0; when the input signal acquisition port 203 is 1 and the output signal acquisition port 202 outputs 1, the monitoring output port 2003 outputs a low level 1; when the input signal acquisition port 203 is 0 and the output signal acquisition port 202 outputs 0, the monitoring output port 2003 outputs a low level 1; when the input signal acquisition port 203 is 1 and the output signal acquisition port 202 outputs 0, the monitor output port 2003 outputs a low level 1.

As shown in fig. 12, the counter 2002 always counts within a preset time, which is longer than the time of inputting and outputting the data signal from the driving module 21, i.e. the number of bits of the data signal, in this example, the data signal includes 48 bits, i.e. the time from inputting to outputting in the driving module 21 is 30 microseconds (μ s), in this example, the preset time is set to 200 μ s, which is far longer than the length of the data signal. As can be seen from the figure, as long as the situation that the output of the input signal acquisition port 203 is 0 and the output of the output signal acquisition port 202 is 1 occurs, the monitoring output port 2003 outputs a low level 0 to the counter 2002, so that the counter 2002 is reset and counts again, and the control port 201 outputs a low level 0, at this time, the selection port of the data direction selector 205 receives the control signal 0, gates the first input branch, closes the second input branch, and allows the data signal to be input from the first signal terminal 100 a; because the control port 201 outputs a low level to the control terminal of the first switching device 207, the first switching device 207 is turned off, and the first output branch is turned off; because the low level output by the control port 201 is inverted by the inverter 204 and then changed into high level to be output to the second switching device 209, the second switching device 209 is turned on, and the second output branch is turned on; the data signal is output from the second signal terminal 100 b. That is, the data signal is input from the first signal terminal 100a on the left side and output from the second signal terminal 100b on the right side.

As shown in fig. 13, only when the input signal acquisition port 203 is not 0 and the output signal acquisition port 202 is 1 within 200 microseconds of the preset time, the monitoring output port 2003 continues to output 1, so that the counter 2002 continues to count, and when the preset value a is reached or exceeded, the control port 201 outputs a high level 1. That is, the select port of the data direction selector 205 receives the control signal 1, gates the second input branch, and closes the first input branch, so that the data signal is input from the second signal terminal 100 b; as the control port 201 outputs a high level to the control terminal of the first switching device 207, the first switching device 207 is turned on, and the first output branch is turned on; because the high level output by the control port 201 is inverted by the inverter 204 and then changed into low level to be output to the second switching device 209, the second switching device 209 is closed, and the second output branch is closed; the data signal is output from the first signal terminal 100 a. Meanwhile, since the data signal output from the data output port passes through the first switching device 207 and then passes through the first diode 206 and is collected by the input signal collection port 203, at this time, the signals collected by the input signal collection port 203 and the output signal collection port 202 are always equal to each other, and therefore, the control port 201 is maintained to output the high level 1. So that the data signal is input from the second signal terminal 100b on the right side and output from the first signal terminal 100a on the left side.

As another way, another implementation manner of the LED lamp 100 data direction determining and switching module 20 and the driving module 21 is given in this example, as shown in fig. 6b, the data direction determining and switching module 20 also includes a data input circuit, a data output circuit, and a watchdog 200(Watching Dog, abbreviated as WD);

The data input circuit comprises a first AND gate 403, a second AND gate 405 and an OR gate 404; the first signal terminal 100a is connected to an input terminal of the first and gate 403 through the fourth diode 401, forming a first input branch; the second signal terminal 100b is connected to an input terminal of the second and gate 405 through a fifth diode 409 to form a second input branch; the outputs of the first and-gate 403 and the second and-gate 405 are connected to the inputs of an or-gate 404, the output of said or-gate 404 being connected to said data input DI.

The data output circuit comprises a first output branch and a second output branch, the first output branch is connected between the first signal terminal 100a and the data output port DO through the third switching device 402; the second output branch is connected between the second signal terminal 100b and the data output port DO via said fourth switching device 410.

The watchdog 200 comprises a control input 333 and a control output 222, the control input 333 being connected to the output of a third and gate 408, one input of the third and gate 408 being connected to the data output DO, the other input being connected to the first signal terminal 100a via a second not gate 407; the control output 222 is connected to another input of the second and-gate 405 and to a control terminal of the third switching device 402, to another input of the first and-gate 403 and to a control terminal of the fourth switching device 410 via the first not-gate 406.

The data direction determining and switching module 20 also makes the input and output of the data signal meet the following results: when the data signal is input from the first input branch, the data signal is output from the second output branch; or when the data signal is input from the second input branch, the data signal is output from the first output branch.

The working process is described as follows: the system is configured such that when the control input port 333 of the watchdog 200 receives an input signal of 1, the counter inside the watchdog 200 is reset to zero, and before the counter does not reach the set value a (if the counter does not count continuously, 200 microseconds will reach the set value a), the output of the control signal 222 is 0, and when the control input port 333 receives an input signal of 0, the counter inside the watchdog 200 continues to count, and until the counter reaches the value a (i.e., after 200 microseconds), the output of the control output port 222 is 1.

After power-on, before no data signal, the counter in the watchdog 200 starts counting, and within 200 microseconds, before the counter does not reach the set value a, the watchdog 200 controls the output value of the output port 222 to be 0, and after passing through the first not gate 406, the output value is 1. At this time, if a data signal is input from the first signal terminal 100a, the data signal must include 0 and 1 level signals, so that the signal level after passing through the first and gate 403 always keeps the same as the signal level input from the first signal terminal 100b (because the level from the first not gate 406 is 1), and then passes through the or gate 404. The or gate 404 receives the signal from the second and gate 405 at the same time, the signal from the fifth diode 409 of the second and gate 405 is at a high level 1, the signal from the control output port 222 is at 0, the signal output to the or gate 404 through the second and gate 405 must be 0, the signal through the or gate 404 is input to the data input port DI as it is, and then output from the data output port DO, and at this time, the control signal of the third switch 402 is at a 0 level (from the control output port 222), and therefore is not output from the third switch device 402, but is output only from the fourth switch device 410 (the control signal of the fourth switch device 410 is 1 after passing through the reverse level of the first not gate 406).

If the signal is continuously inputted from the first signal terminal 100a, the level after passing through the fourth diode 401 always includes the level signal 0, the level signal 0 becomes the level signal 1 after passing through the second not gate 407, and the third and gate 408 also receives a data signal from the data output port DO, the data signal, whether signal 1 or signal 0, contains at least 30% of a high signal, under the 100MHz clock condition, 62.5 times per signal 625ns, then there is enough time to detect a simultaneous 1 input signal in 200 microseconds, the third and gate 408 will output a level signal 1 to the control input 333 such that the clock internal to the watchdog 200 is constantly reset within 200 microseconds, always letting the control output 222 output a control signal 0, thereby ensuring that data is input from the first signal terminal 100a and output from the second signal terminal 100 b.

If no signal is input from the first signal terminal 100a, the output signal of the fourth diode 401 is 1, after passing through the second not gate 407, it becomes 0, the level signal input to the control input port 333 after passing through the third and gate 408 is 0, the counter of the watchdog 200 keeps counting until reaching the value a, the control output port 222 controls the signal output to be 1, the signal output to the first and gate 403 and the fourth switching device 410 after passing through the first not gate 406 is 0, the first and gate 403 always outputs the signal 0 to the or gate 404, at this time, if a signal is input from the second signal terminal 100b, after passing through the fifth diode 409, it is input to the second and gate 405, because the signal to the second and gate 405 through the control output port 222 is 1, the signal from the fifth diode 409 is consistent after passing through the second and gate 405, and the signal after passing through the or gate 404 is also consistent, the control signal of the fourth switching device 410 is 0, and therefore, the control signal is not output from the fourth switching device 410, but output to the first signal terminal 100b through the third switching device 402, and at the same time, the signal through the third switching device 402 is returned from the fourth diode 401 to the second not gate 407 and then output to the third and gate 408, and the signal received by the third and gate 408 is always in the state of the inverse of 0 and 1, and the signal received by the control input port 333 is always 0. Therefore, the control output port 222 always keeps outputting the 1 signal, and the sustain signal is conducted from the second signal terminal 100b to the first signal terminal 100a for output.

The LED lamp 100 provided in this example can input and output data signals through its two signal ports without distinguishing the data direction. The data direction judging and switching module 20 judges the data signal direction of the first signal terminal 100a and the second signal terminal 100b, automatically switches the input port and the output port of the data signal, inputs the data signal from the signal port of the data input, outputs the data signal to the driving module 21, receives the data signal returned from the driving module 21, and outputs the data signal from the signal port of the data output. When the LED lamp 100 is used in the LED display screen 1000 and other devices, the arrangement or wiring of each LED lamp 100 is not required to be specially designed, and the head or tail of the LED lamp 100 between adjacent rows (or adjacent columns) is connected in series under the condition that the arrangement direction of the LED lamps 100 between the rows (or between the columns) is not required to be changed, so that the mode that the original wiring needs to be connected end to end for wiring layout is avoided, and the wiring complexity is greatly reduced. The LED lamp 100 between adjacent rows or columns does not generate a color difference.

Example 2

This example will specifically explain the LED display 1000 of the present disclosure. In this example, an LED display screen 1000 is manufactured by taking the LED lamp shown in fig. 6a as an example.

As shown in fig. 14, there is provided an LED display screen 1000 including an LED array including the LED lamps 100 arranged in an array in the same direction as described in embodiment 1.

As shown in fig. 18, the LED display screen 1000 further includes a Data control module 300(Data control module, DCM for short); the data control module 300 is provided with a plurality of first data ports 300a and second data ports 300 b; the LED lamps 100 of the LED array are connected in series between the first data port 300a and the second data port 300 b. The data signal is transmitted from the first data port 300a to the LED lamp 100 and transmitted to the second data port 300 b.

The array group formed by the LED lamps 100 connected in series between the first data port 300a and the second data port 300b is divided into a plurality of rows or a plurality of columns to be connected in series, and the LED lamps 100 between adjacent rows or adjacent columns are connected in the head or tail.

In this example, the LED display screen 1000 with array display, all the LED lamps 100 in one display screen may be all connected in series to form a lamp group, or may be divided into a plurality of LED lamp groups connected in series. In the serial connection, the lines (or the rows) may be connected in series in sequence, for example, the lines are connected in series, and the head or the tail of the lines between adjacent lines is preferably connected in series.

Specifically, the head concatenation or tail concatenation refers to: the LED lamps 100 in each row are connected in series, and the LED lamp 100 at the tail of the row is connected to the LED lamp 100 at the tail of the adjacent row, or the LED lamp 100 at the head of the row is connected to the LED lamp 100 at the head of the adjacent row, so that the LED lamps 100 in each row connected in series form a snake shape with the head connected in series and the tail connected in series. For example, as shown in fig. 14, a certain lamp group in the LED display screen 1000 includes 4 rows of LED lamps 100; the LED lamps 100 in the lamp group are placed in the same direction, so that the left signal ports are all the first signal ends 100a, and the right signal ports are all the second signal ends 100 b; it can be seen that, except for the head and the tail in each row, the first signal terminal 100a of each LED lamp 100 adjacent to each other in each row is connected to the second signal terminal 100b of the previous LED lamp 100. The head and the tail of each row are connected in series by a head or a tail, that is, a first signal terminal 100a of a first LED lamp 100 (or a head LED lamp) in a first row is connected to a first data port 300a of the data control module 300, the LED lamp 100 at the tail of the first row is connected to the LED lamp 100 at the tail of a second row, and the LED lamp 100 at the head of the second row is connected to the LED lamp 100 at the head of a third row; the LED lamp 100 at the tail of the third row is connected with the LED lamp 100 at the tail of the fourth row; the LED lamp 100 of the fourth row header is connected to the second data interface.

The working process is described as follows:

as shown in fig. 15, when the system is powered on, neither the first signal terminal 100a nor the second signal terminal 100b has data signals input, the first signal terminal 100a and the second signal terminal 100b are pulled high after being powered on due to pull-up resistors, and output of a high level is continued by default, the counter 2002 of the watchdog 200 starts to operate, and when the time has not reached 200 microseconds, the control signal output by the control port 201 of the watchdog 200 is 0.

As shown in fig. 16, if the LED display panel is powered on for more than 200 microseconds without data signal input, then 1 of the control signal output from the control port 201 of the watchdog 200 of each LED lamp. The data signal is allowed to enter the second input branch from the second signal terminal 100b, and the data signal is input to the data input port DI of the driving module 21 through the data direction selector 205, then output from the data output port of the driving module 21, and output from the first signal terminal 100a through the first output branch. However, no data signal is input at this time.

As shown in fig. 17, if the system starts to transmit a data signal from the left, in a state where the signal is input from the left, the input signal of the input signal acquisition port 203 must include a low level 0 signal within 200 microseconds, the data signal of the output signal acquisition port 202 must also include a high level 1 signal, the counter 2002 of the watchdog 200 is kept in a reset state within 200 microseconds, the control signal output by the control port 201 of the watchdog 200 to the data direction selector 205 is kept at a low level 0, and the signal is always ensured to be conducted from the first signal terminal 100a on the left side to the second signal terminal 100b on the right side. When the data direction selector 205 receives the signal 0, the first switching device 207 is turned off, and the second switching device 209 is turned on, so that the first input branch and the second output branch form a path, the data signal input from the first signal terminal 100a is input to the data input port DI of the driving module 21 through the data direction selector 205, and then is output from the data output port of the driving module 21, and is output to the second signal terminal 100b through the second switching device 209 to the next LED lamp.

For the rightmost LED lamp 100 in the second row, the signal is from the rightmost LED lamp 100 in the first row, and the data signal is transmitted from the second signal terminal 100b to the first signal terminal 100a, so that no signal is input from the first signal terminal 100a within 200 microseconds, the watchdog 200 keeps counting within 200 microseconds, and after 200 microseconds, the counter 2002 of the watchdog 200 reaches the set value, the control signal 201 output by the control port 201 is 1, and at this time, the data direction selector 205 receives a high level 1 to gate the path of the second input; at the same time, the first switching device 207 is turned on, the second switching device 209 is turned off, and the first output branch is gated; the data signal is transmitted from the second signal terminal 100b to the data input port DI of the driving module 21 through the second input path via the data direction selector 205, and then is output from the data output port DO and transmitted to the first signal terminal 100a through the first output branch. At this time, the output signal of the data output port DO is input to the output signal acquisition port 202, and is also transmitted back to the input signal acquisition port 203 through the first switching device 207 and the first diode 206, so that the acquisition signals of the input signal acquisition port 203 and the output signal acquisition port 202 always keep the

same input signal

0 or 1, at this time, the watchdog 200 does not perform any action, and the control port 201 keeps outputting the high level 1. Therefore, as long as the signal of the second signal terminal 100b continues continuously, the signal can be transmitted to the first signal terminal 100 a.

For the third row of LED lamps 100, the signal is input from the left, wherein the data signal for the leftmost LED lamp 100 is from the leftmost LED lamp 100 of the second row. The data signals of the LED lamps 100 in the third row are input from the first signal terminal 100a and output from the second signal terminal 100 b. The input signal of the input signal acquisition port 203 must contain a low level 0 signal within 200 microseconds, the data signal of the output signal acquisition port 202 must also contain a high level 1 signal, the counter 2002 of the watchdog 200 keeps a reset state within 200 microseconds, and the control signal output by the control port 201 of the watchdog 200 to the data direction selector 205 is kept at a low level 0 continuously, so that the signal is ensured to be conducted from the first signal terminal 100a on the left side to the second signal terminal 100b on the right side. When the data direction selector 205 receives the signal 0, the first switching device 207 is turned off, and the second switching device 209 is turned on, so that the first input branch and the second output branch form a path, the data signal input from the first signal terminal 100a is input to the data input port DI of the driving module 21 through the data direction selector 205, and then is output from the data output port of the driving module 21, and is output to the second signal terminal 100b through the second switching device 209 to the next LED lamp.

The signal data transmission direction and control logic of the LED lamp 100 in the fourth row are the same as those in the second row, and are not described again.

In the LED display screen 1000 provided in this embodiment, since the LED lamps 100 after the improvement and innovation of the present application are arranged in the array, there is no need to specially design the arrangement or wiring of the LED lamps 100, and the head or tail of the adjacent rows (or adjacent columns) is connected in series without changing the arrangement direction of the LED lamps 100 between the rows (or between the columns), thereby avoiding the way of performing the winding layout by connecting the head and the tail of the original wiring, and greatly reducing the complexity of the wiring. The LED lamp 100 between adjacent rows or columns does not generate a color difference.

Example 3

In the research and development process of the applicant, the signal data of the existing LED display screen 1000 is always transmitted in a single direction, and a data signal is required to always enter from a signal input end and output from a signal output end; at this time, when a fault signal is interrupted in any one of the LED lamps, the data signal cannot be further transmitted downward, and the faulty LED lamp 100 and the subsequent normal LED lamp 100 cannot work normally.

As shown in fig. 18, even if the LED display screen 1000 of embodiment 2 modified in this application adopts a unidirectional transmission manner, if some LED lamps 100 fail, the data signal cannot be transmitted continuously. For example, if one LED lamp in the middle of the second row is damaged in the way, the conducted data signal is interrupted at the position of the LED lamp, and all the remaining LED lamps 100 connected in series at the left side of the LED lamp will be interrupted. Resulting in display failure.

As an improvement, the applicant improves the data control module 300, as shown in fig. 19, the data control module 300 includes two physical network ports (PHY1, PHY2), an FPGA301 and a memory; the Memory in this example is SDRAM (Chinese name: Synchronous Dynamic Random-Access Memory, English name: Synchronous Dynamic Random-Access Memory) 302.

The FPGA301 includes a Data Collection and transmission Module 3013(Data Collection & transmit Module), a First Output Module 3011(First Output Module), a Second Output Module 3012(Second Output Module), and a Break-off Monitoring Module 3015(Break-off Monitoring Module);

the data acquisition and transmission module 3013 is connected to the two physical network ports and the memory, and is configured to acquire a data packet, send the data packet, acquire a data signal from the data packet, and store the data signal in the memory; specifically, the two physical ports include a first physical port 303(PHY1) and a second physical port 304(PHY 2); the data collection and transmission module 3013 receives a data packet from the first physical port 303 and sends the data packet through the second physical port 304. And acquires a data signal for the data control module 300 to control the corresponding LED array from the acquired data packet.

The first output module 3011 is configured to call Data signals (marked as Data1 and Data2 … … in fig. 18 and 19) stored in the memory, and send the Data signals to a lamp group formed by corresponding LED lamps 100 connected in series through the first Data port 300 a; the data signal is transmitted from the first to the last of the series of LED lamps 100. Each LED lamp 100 obtains its corresponding driving signal from the LED lamp 100, and drives the light emitting chip 1 in each LED lamp 100 to emit light.

The second output module 3012 is configured to call an inverse signal of the Data signal stored in the memory as a backup signal (marked as Data1 'and Data 2' … … in fig. 18 and 19), and send the backup signal to the lamp group formed by the corresponding series-connected LED lamps 100 through the second Data port 300 b; that is, the backup signal is transmitted from the last LED lamp 100 to the first LED lamp 100 in the reverse direction.

A backup switch device 3014 is disposed between the second output module 3012 and the second data port 300b, where the backup switch device 3014 is used to control the second output module 3012 to switch on and off of a backup signal sent out;

the open circuit monitoring module 3015 is respectively connected to the control terminal of the backup switch device 3014 and the second data port 300b through a third diode 3016, and is configured to collect data of the second data port 300b and output a backup control signal to the control terminal of the backup switch device 3014.

The working process is described as follows:

taking the data direction determining and switching module 20 in fig. 6a as an example, during normal operation, the first output module 3011 calls the data signal stored in the memory, and sends the data signal to the LED lamp 100 connected in series between the first data port 300a and the second data port 300b from the LED lamp 100 on the left side of the first row through the first data port 300a, when the LED lamp 100 in the second row fails. All the LED lamps 100 starting at the left side of the failed LED lamp are interrupted by the data signal, and the signals collected by the input signal collecting port 203 and the output signal collecting port 202 of the watchdog 200 of the LED lamp 100 after the failed LED lamp 100 are all 1. After the situation lasts 200 microseconds, the open circuit monitoring module 3015 of the Data control module 300 monitors that the Data signal input from the third diode 3016 on the second Data port 300b is interrupted for more than 200 microseconds, at this time, the open circuit monitoring module 3015 sends out a control signal to turn on the backup switch device 3014, so that the backup signal Data1 ' of the Data control module 300 is sent out, and therefore, the leftmost LED lamp in the last row receives the backup signal Data1 ', and the Data sequence of the backup signal Data1 ' and the Data signal Data1 is in an inverse relationship, so that the signal can be transmitted to the LED lamp on the left of the damaged LED lamp in the second row from the leftmost LED lamp in the last row, and it is ensured that the image is consistent with the original image. So that the entire LED matrix can function normally except for a damaged LED lamp.

Meanwhile, another one or more LED lamp groups can be driven in the same mode, and different LED lamp group images are spliced into a complete image.

By arranging the first output module 3011, the second output module 3012 and the disconnection detection module in the FPGA301 of the data control module 300, the first output module 3011 can forward input a data signal to the lamp group in series connected with the corresponding LED lamp 100, and when a fault occurs in an LED lamp 100 in the lamp group in series to cause disconnection, the disconnection monitoring module 3015 can monitor the state of the second data port 300b and determine that no data signal is received; at this time, it may control the backup switch device 3014 to be turned on, so that it sends out a reverse backup signal through the second output module 3012. Ensuring that the LED lamp 100 behind the failed LED lamp 100 can still operate properly.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A driving chip is provided with a driving module, and is connected with a signal port and a power port; the power supply port is used for providing power supply for the driving chip; the signal port is used for inputting and outputting data signals;

wherein the signal ports comprise a first signal port and a second signal port;

the driving chip also comprises a data direction judging and switching module connected with the driving module; the data direction judging and switching module is connected with the first signal port and the second signal port and used for judging the data signal input direction of the first signal port and the second signal port, automatically switching the signal port of the data signal input and the signal port of the data signal output, leading in the data signal from the input signal port, transmitting the data signal to the driving module, receiving the data signal returned from the driving module, and outputting the data signal from the signal port of the data output.

2. The driver chip of claim 1, wherein the driver module comprises a data input port and a data output port;

3. The driver chip of claim 2, wherein the data input circuit comprises a data direction selector; the data direction selector is respectively connected with the first signal end, the second signal end, the watchdog and a data input port of the driving module; the data direction selector is connected with the first signal end and the second signal end to form two input branches, and the two input branches are used for switching and connecting signal ports of data signal input according to a control signal sent by the watchdog, selecting the input branches and outputting the data signal from the data direction selector to a data input port of the driving module;

4. The driver chip of claim 3, wherein the data direction selector comprises a first signal port, a second signal port, a data output port, and a selection port;

5. The driver chip of claim 4, wherein the watchdog comprises a signal monitoring module and a counter;

6. The driver chip of claim 5, wherein the signal monitoring module logic determines the rule as follows: when the signals collected by the input signal collection port and the output signal collection port are not equal, the signal collected by the input signal collection port is low level 0, and the signal collected by the output signal collection port is high level 1, the monitoring output port outputs a monitoring signal which is low level 0; and the other monitoring output port outputs a monitoring signal with a high level 1.

7. The driving chip of claim 6, wherein the frequency of the signal collected by the signal monitoring module is much greater than the frequency of the data signal;

8. The driver chip according to claim 1, wherein the driver module comprises a logic circuit module and an analog circuit module;

9. The driver chip of claim 2, wherein the data input circuit comprises a first and gate, a second and gate, and an or gate; the first signal end is connected to one input end of the first AND gate through a fourth diode to form a first input branch; the second signal end is connected to one input end of the second AND gate through a fifth diode to form a second input branch; the output ends of the first AND gate and the second AND gate are connected to the input end of an OR gate, and the output end of the OR gate is connected to the data input port;

10. An LED lamp comprises a driving chip, a light-emitting wafer, a signal port and a power port, wherein a driving module is arranged in the driving chip; the power supply port is used for providing power supply for the circuit in the LED lamp; the signal port is used for inputting and outputting data signals; the light-emitting wafer is connected to the driving chip and driven by the driving module;

wherein the signal ports comprise a first signal port and a second signal port;

11. The LED lamp of claim 10, wherein the data direction determination and switching module is disposed within the driver chip.

12. The LED lamp of claim 11, wherein the driver module includes a data input port and a data output port;

13. The LED lamp of claim 12, wherein the data input circuit comprises a data direction selector; the data direction selector is respectively connected with the first signal end, the second signal end, the watchdog and a data input port of the driving module; the data direction selector is connected with the first signal end and the second signal end to form two input branches, and the two input branches are used for switching and connecting signal ports of data signal input according to a control signal sent by the watchdog, selecting the input branches and outputting the data signal from the data direction selector to a data input port of the driving module;

14. The LED lamp of claim 13, wherein the data direction selector comprises a first signal port, a second signal port, a data output port, and a selection port;

15. The LED lamp of claim 14, wherein the watchdog comprises a signal monitoring module and a counter;

16. The LED lamp of claim 15, wherein the signal monitoring module logic determines the rule as follows: when the signals collected by the input signal collection port and the output signal collection port are not equal, the signal collected by the input signal collection port is low level 0, and the signal collected by the output signal collection port is high level 1, the monitoring output port outputs a monitoring signal which is low level 0; and the other monitoring output port outputs a monitoring signal with a high level 1.

17. The LED lamp of claim 16, wherein the signal monitoring module collects a signal at a frequency substantially greater than the data signal;

18. The LED lamp of claim 10, wherein the driver module includes a logic circuit module and an analog circuit module;

19. The LED lamp of claim 12, wherein the data input circuit comprises a first and gate, a second and gate, and an or gate; the first signal end is connected to one input end of the first AND gate through a fourth diode to form a first input branch; the second signal end is connected to one input end of the second AND gate through a fifth diode to form a second input branch; the output ends of the first AND gate and the second AND gate are connected to the input end of an OR gate, and the output end of the OR gate is connected to the data input port;

20. An LED display screen, characterized by comprising the LED lamp of any one of claims 10-19.

21. The LED display screen of claim 20, wherein the LED lamps form an LED array, and the LED array is arranged in an array in the same direction.

22. The LED display screen of claim 21, further comprising a data control module;

23. The LED display screen of claim 22, wherein the array of LED lamps connected in series between the first data port and the second data port is divided into a plurality of rows or columns connected in series, and the LED lamps between adjacent rows or adjacent columns are connected in series at the head or the tail.

24. The LED display screen of claim 23, wherein the data control module comprises two physical ports, an FPGA and a memory;