CN111338998A - FLASH access processing method and device based on AMP system - Google Patents

FLASH access processing method and device based on AMP system Download PDF

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Publication number
CN111338998A
CN111338998A CN202010104682.6A CN202010104682A CN111338998A CN 111338998 A CN111338998 A CN 111338998A CN 202010104682 A CN202010104682 A CN 202010104682A CN 111338998 A CN111338998 A CN 111338998A
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core
flash
memory
dma
data
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CN111338998B (en
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秦金昆
吴闽华
孟庆晓
刘文清
杨超
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Shenzhen Genew Technologies Co Ltd
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Shenzhen Genew Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

The application relates to a FLASH access processing method and device based on an AMP system, wherein the method comprises the following steps: when reading data, the slave core sends the FLASH reading parameters to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core; when writing data, the slave core writes the physical address of the memory where the data to be written is located into the target FLASH write-in parameter and transmits the parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface. The invention can improve the access speed and avoid the problem that the master core and the slave core are locked.

Description

FLASH access processing method and device based on AMP system
Technical Field
The present application relates to the field of embedded system technologies, and in particular, to a FLASH access processing method and apparatus based on an AMP system, a computer device, and a readable storage medium.
Background
In the field of embedded Multi-core systems, there are two technologies, one is AMP (Asymmetric Multi-Processing) Asymmetric multiprocessing, and the other is smp (symmetric Multi-Processing) symmetric multiprocessing. Each CPU on the SMP system shares all the resources of the system, including the serial ports, and the SMP system is only required to be provided with one console. And the AMP has independent running codes for each CPU, the task scheduling is independent, the access to the whole system resource is mutually exclusive, and the Operating Systems (OS) running on each CPU are even different.
Two kernels on a hardware CPU run their own operating system and application software, respectively. However, the peripheral modules and the drivers are all shared on an embedded single board, such as a network port, a serial port, a flash, a CPLD and the like. Taking NOR FLASH as an example, an AMP system is operated on an embedded board of a dual-core CPU. It becomes less simple if both CPU cores are to access norstack. If one CPU inner core writes FLASH and the other one reads FLASH, the inside of the FLASH chip will be in error, and the FLASH cannot be accessed. In brief summary, NOR FLASH can only be accessed by two CPU cores with mutual exclusion.
In the prior art, in order to solve the problem of accessing the same NOR FLASH by two CPU cores under AMP, several common methods are generally used. The method in the prior art comprises the following steps: the master core can directly read and write the NOR FLASH, the slave core can only indirectly access through the master core, and the access result is fed back to the slave core through master-slave information. This method requires copying memory many times, and has poor performance. As shown in fig. 1, in this method, the master core and the slave core need to copy once to transmit the data to be written by the slave core to the master core and write the data into FLASH, or the master core reads the FLASH data and copies the data to the shared memory of the master core and the slave core and copies the data from the shared memory to the application program. There is also a significant problem that the size of the memory shared by the master and slave cores is very limited, and if the slave core needs to read and write FLASH data of tens of MB, the data can be divided into blocks for completion.
In the second method in the prior art, both the dual cores can access the FLASH, and a mutual exclusion lock of the master core and the slave core is created at the same time, so that mutual exclusion restriction is performed on the access of the master core and the slave core to the FLASH interface. The great disadvantage of this approach is that if the mutex lock is taken up by one core for a long time, even if the core enters a dead loop, then another core will take a long time or will not be able to access FLASH. As shown in fig. 2, the master core obtains the mutual exclusion lock on the left side, the master core can directly access the FLASH, and the slave core is blocked from accessing the FLASH. The right side is that the main core obtains the mutual exclusion lock, the slave core can directly access the FLASH, and the access of the main core to the FLASH is blocked.
If the current lock is occupied by the master core for a long time, the slave core will have a long time or cannot access FLASH.
Therefore, the prior art is in need of improvement.
Disclosure of Invention
The invention provides a FLASH access processing method and device based on an AMP system, computer equipment and a readable storage medium aiming at the technical problems in the prior art, and the invention can improve the access speed and avoid the problem that a master core and a slave core are deadlocked.
The technical scheme of the invention is as follows:
a FLASH access processing method based on AMP system, wherein the method comprises:
connecting a master core with a slave core, connecting a FLASH memory with the master core through a DMA channel, then connecting the FLASH memory with the slave core, setting read-write data to be transmitted by adopting DMA, and controlling the DMA channel by the master core;
when reading data, the slave core sends the FLASH reading parameters to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located into the target FLASH write-in parameter and transmits the parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
The method for processing FLASH access based on AMP system comprises the following steps of connecting a master core with a slave core, connecting a FLASH memory with the master core through a DMA channel, and then connecting the FLASH memory with the slave core, setting read-write data to be transmitted by DMA, wherein the master core controls the DMA channel and further comprises:
an inter-core communication message structure for accessing FLASH from a core is predefined.
According to the FLASH access processing method based on the AMP system, when data is read, the secondary core sends FLASH reading parameters to the primary core by means of inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the step that the DMA controller directly copies the FLASH data to the specified memory of the slave core comprises the following steps:
DMA direct memory access transmission is adopted, the main core controls a DMA channel, and the slave core transmits FLASH reading parameters to the main core by using inter-core communication;
and after receiving the request of the slave core, the master core sets the DMA channel parameters and starts one-time DMA transmission. The DMA controller then copies the FLASH data directly to the specified memory of the slave core.
The method for accessing and processing the FLASH based on the AMP system comprises the following steps that the slave core sends parameters for reading the FLASH to a FLASH in the master core by using inter-core communication:
FLASH address, memory physical address for storing FLASH data, reading length and reading command.
The FLASH access processing method based on the AMP system comprises the following steps that the main core sets DMA parameters in the DMA parameters:
the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length.
According to the FLASH access processing method based on the AMP system, when data is written, a slave core writes target FLASH write-in parameters into a memory physical address where the data to be written is located, and the target FLASH write-in parameters are transmitted to a master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the secondary core, the destination address is the memory of the main core through DMA, and then the step of writing in FLASH through a FLASH writing interface comprises:
when writing data, the slave core writes a physical memory address where the data to be written is located, a target FLASH address and length, and four parameters of a write command, and transmits the four parameters to the master core through inter-core communication;
when the main core sets DMA parameters, the source address is a physical address of the memory of the slave core, the destination address is not a FLASH address directly, but is DMA-written into the memory of the main core first, and then FLASH is written into the memory through a FLASH writing interface.
A FLASH access processing apparatus based on an AMP system, wherein the apparatus comprises:
the device comprises a setting module, a master core and a slave core, wherein the setting module is used for connecting the master core with the slave core, connecting a FLASH memory with the master core through a DMA channel and then connecting the FLASH memory with the slave core, and setting read-write data to be transmitted by adopting DMA, and controlling the DMA channel by the master core;
the data reading control module is used for controlling the slave core to send the parameters for reading the FLASH to the master core by using inter-core communication when data is read; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
the data writing control module is used for writing a target FLASH writing parameter into a memory physical address where data to be written are located by the slave core and transmitting the target FLASH writing parameter to the master core through inter-core communication when data is written; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
The device for accessing and processing the FLASH based on the AMP system, wherein the parameters of reading the FLASH by the slave core are sent to the FLASH in the master core by using the inter-core communication, and the parameters comprise: FLASH address, memory physical address for storing FLASH data, reading length and reading command;
the setting of the DMA parameters in the DMA parameters by the main core comprises the following steps: the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length.
A computer device comprising a memory storing a computer program and a processor, wherein the processor when executing the computer program implements the steps of any one of the AMP system based FLASH access processing methods.
A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of any of the AMP system based FLASH access processing methods.
Compared with the prior art, the embodiment of the invention has the following advantages:
the invention provides a FLASH access processing method and device based on an AMP system, a computer device and a readable storage medium. After receiving the request of the slave core, the master core sets DMA channel parameters (the source address is the FLASH physical address to be read, the destination address is the memory physical address for storing FLASH data, and the read length), and starts one DMA transmission. Then, the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located, the target FLASH address and length, and four parameters of the write command, and transmits the parameters to the master core through inter-core communication. When the main core sets DMA parameters, the source address is a physical address of the slave core memory, the destination address is not a FLASH address directly, but is DMA-written into the main core memory, and then FLASH is written into the main core memory through a FLASH writing interface; and the realization is simple, and the reliability is high.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 and fig. 2 are schematic diagrams of a connection structure of a master core and a slave core in the prior art.
Fig. 3 is a flowchart illustrating a FLASH access processing method based on an AMP system according to embodiment 1 of the present invention.
Fig. 4 is a schematic view of a read data principle of a FLASH access processing method based on an AMP system according to embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of a data writing principle of a FLASH access processing method based on an AMP system according to embodiment 1 of the present invention.
Fig. 6 is a schematic view of a read data flow of a FLASH access processing method based on an AMP system in embodiment 2 of the present invention.
Fig. 7 is a schematic flowchart of a master-slave FLASH access processing method based on an AMP system according to embodiment 2 after receiving a slave-core write FLASH request command.
Fig. 8 is a schematic flow chart of writing FLASH from the core of a FLASH access processing method based on an AMP system in embodiment 2 of the present invention.
Fig. 9 is a schematic flowchart of a master-slave write FLASH request command of a FLASH access processing method based on an AMP system according to embodiment 2 of the present invention, and then write to FLASH.
Fig. 10 is a schematic structural diagram of a FLASH access processing device based on an AMP system in an embodiment of the present invention.
Fig. 11 is an internal structural diagram of a computer device in an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The inventor has found that, in the prior art, to solve the problem of accessing the same NOR FLASH by two CPU cores under AMP, several common methods are generally used. The method in the prior art comprises the following steps: the master core can directly read and write the NOR FLASH, the slave core can only indirectly access through the master core, and the access result is fed back to the slave core through master-slave information. This method requires copying memory many times, and has poor performance. As shown in fig. 1, in this method, the master core and the slave core need to copy once to transmit the data to be written by the slave core to the master core and write the data into FLASH, or the master core reads the FLASH data and copies the data to the shared memory of the master core and the slave core and copies the data from the shared memory to the application program. There is also a significant problem that the size of the memory shared by the master and slave cores is very limited, and if the slave core needs to read and write FLASH data of tens of MB, the data can be divided into blocks for completion. In the second method in the prior art, both the dual cores can access the FLASH, and a mutual exclusion lock of the master core and the slave core is created at the same time, so that mutual exclusion restriction is performed on the access of the master core and the slave core to the FLASH interface. The great disadvantage of this approach is that if the mutex lock is taken up by one core for a long time, even if the core enters a dead loop, then another core will take a long time or will not be able to access FLASH. As shown in fig. 2, the master core obtains the mutual exclusion lock on the left side, the master core can directly access the FLASH, and the slave core is blocked from accessing the FLASH. The right side is that the main core obtains the mutual exclusion lock, the slave core can directly access the FLASH, and the access of the main core to the FLASH is blocked. If the current lock is occupied by the master core for a long time, the slave core will have a long time or cannot access the FLASH.
In order to solve the above problem, in the embodiment of the present invention, when reading data, the slave core sends the parameter of reading FLASH to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core; when writing data, the slave core writes the physical address of the memory where the data to be written is located into the target FLASH write-in parameter and transmits the parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface. The invention provides a brand new method, solves the problems of the two methods, can improve the access speed, can avoid the problem that a master core and a slave core are locked, and has simple realization and high reliability.
Various non-limiting embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 3, fig. 3 shows a FLASH access processing method based on an AMP system according to an embodiment of the present invention, where the method includes the following steps:
step S1, connecting the main core with the slave core, connecting the FLASH memory with the main core through a DMA channel, then connecting the FLASH memory with the slave core, setting read-write data to be transmitted by DMA, and controlling the DMA channel by the main core;
in the invention, as shown in fig. 4, a master core is connected with a slave core, a FLASH memory is connected with the master core through a DMA channel and then connected with the slave core, read-write data is set to be transmitted by DMA, and the master core controls the DMA channel.
Step S2, when reading data, the slave core sends the parameters of reading FLASH to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
in the embodiment of the present invention, the sending, by the slave core, the parameter for reading the FLASH to the FLASH in the master core by using inter-core communication includes: FLASH address, memory physical address for storing FLASH data, reading length and reading command.
The setting of the DMA parameters in the DMA parameters by the main core comprises the following steps: the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length.
The present invention employs DMA (direct memory access) transfers to copy data from one address space to another. When the CPU initiates the transmission action, the transmission action is carried out and completed by the DMA controller, and the CPU does not participate in the data transmission, thereby greatly reducing the load of the CPU.
For example, as shown in fig. 4, when reading data, the master core controls the DMA channel, and the slave core sends parameters for reading FLASH (four parameters, i.e., FLASH address, physical memory address for storing FLASH data, read length, and read command) to the master core by using inter-core communication. After receiving the request of the slave core, the master core sets DMA channel parameters (the source address is the FLASH physical address to be read, the destination address is the memory physical address for storing FLASH data, and the read length), and starts one DMA transmission. Subsequently, the DMA controller directly copies the FLASH data to the designated memory of the slave core.
Step S3, when writing data, the slave core writes the target FLASH write-in parameter into the memory physical address where the data to be written is located, and transmits the target FLASH write-in parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
In the embodiment of the invention, when data is written, a slave core writes a physical memory address of data to be written in, a target FLASH address and length, and four parameters of a write command are transmitted to a master core through inter-core communication; when the main core sets DMA parameters, the source address is a physical address of the memory of the slave core, the destination address is not a FLASH address directly, but is DMA-written into the memory of the main core first, and then FLASH is written into the memory through a FLASH writing interface.
For example, as shown in fig. 5, when writing FLASH from the core, because FLASH does not support direct writing, a series of commands are required to write data. The slave core writes the physical address of the memory where the data to be written is located, writes the target FLASH address and length, writes four parameters of the command, and transmits the four parameters to the master core through inter-core communication. When the main core sets DMA parameters, the source address is a physical address of the memory of the slave core, the destination address is not a FLASH address directly, but is DMA-written into the memory of the main core first, and then FLASH is written into the memory through a FLASH writing interface.
Therefore, the method of the invention can not only improve the access speed, but also avoid the problem that the master core and the slave core are trapped in deadlock.
The invention is further illustrated in detail by the following specific application examples:
1) defining an inter-core communication message structure body for accessing FLASH from a core:
typedef struct
{
vollatile ulong ulFlashAddr; // flash address to read/write
volatile ulong ulRamAddr; // to store or write to a physical memory address
volatile ulong ulLength; // length to read and write once, number of bytes
A volatile ulong ul Command; read/write commands read 0 and write 1
}FLASH_OP_CMD；
2) Setting the size of FLASH to 64MB, the starting physical address of the slave kernel memory to 512-1024 MB, and the FLASH BASE address FLASH _ BASE;
3) and FIG. 6 shows that the slave core reads FLASH, first sends a FLASH reading request to the master core, and then waits for the execution result of the master core.
In FIG. 6, the FLASH read function; defining FLASH _ OP _ CMD; assigning values to the cmd structure, respectively filling FLASH addresses, storing the memory physical addresses of the data, reading the length of the FLASH, and setting the command code to be 0; sending the structure cmd to a main core by utilizing inter-core communication; waiting for the main core to return a command execution result; and returning success or failure of the execution result.
4) And FIG. 7 is a flow chart of the master-slave after receiving a slave core write FLASH request command. As shown in figure 7 of the drawings,
step 10, reading a FLASH function FLASH _ OP _ CMD CMD, and entering step 11;
step 11, if uIlength is less than 64M, namely, whether the length exceeds the size of FLASH by 64M is judged, if yes, the step 12 is carried out, and if not, the step 18 is carried out;
step 12, 512M < ulRamAddr < 1024M; if yes, go to step 13, if no, go to step 18;
judging whether the physical address of the slave core memory is 512-1024M;
step 13, 0M < ulFlashAddr <64M, if yes, step 14 is entered, and if no, step 18 is entered;
step 14, ul command? If yes, entering step 15, and if no, entering step 18;
i.e. finally whether it is read command 0.
Step 15, setting the DMA channel parameter source address of ulFlashAddr + FLASHI _ BASE and the destination address of ulRamAddr, and entering step 16;
step 16, starting a DMA channel, and entering step 17;
step 17, returning the result of DMA channel transmission, and sending the result to the slave core if the result is successful or failed;
setting DMA channel parameters, starting DMA, waiting for DMA transmission success or failure, and returning the result;
and step 18, returning the failure to the slave core.
Namely, if the judgment fails, the failure is directly returned.
5) Writing FLASH by the slave core, firstly sending a FLASH writing request to the master core, and then waiting for the execution result of the master core;
in FIG. 8, the FLASH read function; defining FLASH _ OP _ CMD; assigning values to the cmd structure, respectively filling FLASH addresses, storing the memory physical addresses of the data, reading the length of the FLASH, and setting the command code to be 1; sending the structure cmd to a main core by utilizing inter-core communication; waiting for the main core to return a command execution result; and returning success or failure of the execution result.
6) After receiving the FLASH write command from the slave core, the master core transmits the data to be written by the slave core to its own memory space through the DMA channel, and then writes the data into FLASH through the write driver function, and finally sends the result to the slave core, as shown in fig. 9;
step 20, reading a FLASH function FLASH _ OP _ CMD CMD, and entering step 21;
step 21, if uIlength is less than 64M, namely, whether the length exceeds the size of FLASH by 64M is judged, if yes, the step 22 is carried out, and if not, the step 29 is carried out;
step 22, 512M < ulRamAddr < 1024M; if yes, go to step 23, if no, go to step 29;
judging whether the physical address of the slave core memory is 512-1024M;
step 23, 0M < ulFlashAddr <64M, if yes, step 24 is entered, and if no, step 29 is entered;
step 24, ul command? If yes, go to step 25, if no, go to step 29;
i.e. whether it is read command 0.
Step 25, applying for temporary buffer buf [ ulLength ], setting DMA channel parameters: entering step 26 for the corresponding physical address with source address ulRamAddr and destination address but;
step 26, starting a DMA channel, and entering step 27;
step 27, judging whether the transmission of the returned DMA channel is successful, if so, entering step 28, and if not, entering step 29;
setting DMA channel parameters, starting DMA, waiting for DMA transmission success or failure, and returning the result;
and step 28, sending the execution result of the flash _ write (but, ulFlashAddr, ulLength) to the slave core.
And step 29, returning the failure to the slave core.
It can be seen from the above that, the present invention provides a FLASH access processing method based on an AMP system, which adopts DMA (direct memory access) transmission, the master core controls a DMA channel, and the slave core sends parameters (FLASH address, memory physical address for storing FLASH data, read length, and read command) for reading FLASH to the master core by using inter-core communication. After receiving the request of the slave core, the master core sets DMA channel parameters (the source address is the FLASH physical address to be read, the destination address is the memory physical address for storing FLASH data, and the read length), and starts one DMA transmission. Then, the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located, the target FLASH address and length, and four parameters of the write command, and transmits the parameters to the master core through inter-core communication. When the main core sets DMA parameters, the source address is a physical address of the slave core memory, the destination address is not a FLASH address directly, but is DMA-written into the main core memory, and then FLASH is written into the main core memory through a FLASH writing interface; and the realization is simple, and the reliability is high.
In one embodiment, the present invention provides a FLASH access processing apparatus based on an AMP system, as shown in fig. 10, the apparatus including:
the setting module 41 is used for connecting the master core with the slave core, connecting the FLASH memory with the master core through a DMA channel and then connecting the FLASH memory with the slave core, and setting read-write data to be transmitted by adopting DMA, wherein the master core controls the DMA channel;
the read data control module 42 is used for controlling the slave core to send the parameters for reading the FLASH to the master core by using inter-core communication when reading data; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
the data writing control module 43 is configured to, when writing data, write a target FLASH write parameter into a physical memory address where data to be written is located in the slave core, and transmit the target FLASH write parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
The parameters of the FLASH read by the slave core are sent to the parameters of the FLASH in the master core by using inter-core communication, wherein the parameters comprise: FLASH address, memory physical address for storing FLASH data, reading length and reading command;
the setting of the DMA parameters in the DMA parameters by the main core comprises the following steps: the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length; as described above.
In one embodiment, the present invention provides a computer device, which may be a terminal, having an internal structure as shown in fig. 11. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of generating a natural language model. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that fig. 11 is a block diagram of only a portion of the structure associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
The embodiment of the invention provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to realize the following steps:
connecting a master core with a slave core, connecting a FLASH memory with the master core through a DMA channel, then connecting the FLASH memory with the slave core, setting read-write data to be transmitted by adopting DMA, and controlling the DMA channel by the master core;
when reading data, the slave core sends the FLASH reading parameters to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located into the target FLASH write-in parameter and transmits the parameter to the master core through inter-core communication; setting DMA parameters by a main core, wherein a source address is a physical address of a slave core memory, and a destination address is a memory of the main core through DMA and then written into FLASH through a FLASH writing interface; as described above.
In summary, compared with the prior art, the embodiment of the invention has the following advantages:
the invention provides a FLASH access processing method and device based on an AMP system, a computer device and a readable storage medium. After receiving the request of the slave core, the master core sets DMA channel parameters (the source address is the FLASH physical address to be read, the destination address is the memory physical address for storing FLASH data, and the read length), and starts one DMA transmission. Then, the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located, the target FLASH address and length, and four parameters of the write command, and transmits the parameters to the master core through inter-core communication. When the main core sets DMA parameters, the source address is a physical address of the slave core memory, the destination address is not a FLASH address directly, but is DMA-written into the main core memory, and then FLASH is written into the main core memory through a FLASH writing interface; and the realization is simple, and the reliability is high.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A FLASH access processing method based on AMP system is characterized in that the method comprises the following steps:
connecting a master core with a slave core, connecting a FLASH memory with the master core through a DMA channel, then connecting the FLASH memory with the slave core, setting read-write data to be transmitted by adopting DMA, and controlling the DMA channel by the master core;
when reading data, the slave core sends the FLASH reading parameters to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
when writing data, the slave core writes the physical address of the memory where the data to be written is located into the target FLASH write-in parameter and transmits the parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
2. The method for accessing and processing the FLASH based on the AMP system according to claim 1, wherein the connecting the master core with the slave core, connecting the FLASH memory with the master core through the DMA channel, and then connecting the FLASH memory with the slave core, and setting the read-write data to be transmitted by the DMA, the step of the master core controlling the DMA channel further comprises:
an inter-core communication message structure for accessing FLASH from a core is predefined.
3. The AMP system-based FLASH access processing method of claim 1, wherein during reading data, the slave core transmits FLASH reading parameters to the master core by using inter-core communication; after receiving the request of the slave core, the master core starts DMA transmission; the step that the DMA controller directly copies the FLASH data to the specified memory of the slave core comprises the following steps:
DMA direct memory access transmission is adopted, the main core controls a DMA channel, and the slave core transmits FLASH reading parameters to the main core by using inter-core communication;
and after receiving the request of the slave core, the master core sets the DMA channel parameters and starts one-time DMA transmission. The DMA controller then copies the FLASH data directly to the specified memory of the slave core.
4. The AMP system-based FLASH access processing method of claim 1, wherein the sending the FLASH read parameters from the slave core to the FLASH parameters in the master core by using inter-core communication comprises:
FLASH address, memory physical address for storing FLASH data, reading length and reading command.
5. The AMP system-based FLASH access processing method of claim 1, wherein the setting of the DMA parameters by the master core comprises:
the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length.
6. The AMP system-based FLASH access processing method of claim 1, wherein during data writing, the slave core writes a target FLASH write parameter into a memory physical address where data to be written is located, and transmits the target FLASH write parameter to the master core through inter-core communication; the main core sets DMA parameters, the source address is the physical address of the memory of the secondary core, the destination address is the memory of the main core through DMA, and then the step of writing in FLASH through a FLASH writing interface comprises:
when writing data, the slave core writes a physical memory address where the data to be written is located, a target FLASH address and length, and four parameters of a write command, and transmits the four parameters to the master core through inter-core communication;
when the main core sets DMA parameters, the source address is a physical address of the memory of the slave core, the destination address is not a FLASH address directly, but is DMA-written into the memory of the main core first, and then FLASH is written into the memory through a FLASH writing interface.
7. A FLASH access processing apparatus based on an AMP system, the apparatus comprising:
the device comprises a setting module, a master core and a slave core, wherein the setting module is used for connecting the master core with the slave core, connecting a FLASH memory with the master core through a DMA channel and then connecting the FLASH memory with the slave core, and setting read-write data to be transmitted by adopting DMA, and controlling the DMA channel by the master core;
the data reading control module is used for controlling the slave core to send the parameters for reading the FLASH to the master core by using inter-core communication when data is read; after receiving the request of the slave core, the master core starts DMA transmission; the DMA controller directly copies the FLASH data to a specified memory of the slave core;
the data writing control module is used for writing a target FLASH writing parameter into a memory physical address where data to be written are located by the slave core and transmitting the target FLASH writing parameter to the master core through inter-core communication when data is written; the main core sets DMA parameters, the source address is the physical address of the memory of the slave core, the destination address is the memory of the main core through DMA, and then the FLASH is written in through a FLASH writing interface.
8. The AMP system-based FLASH access processing apparatus of claim 7, wherein the slave core transmitting the parameters for reading FLASH to the parameters for FLASH in the master core using inter-core communication comprises: FLASH address, memory physical address for storing FLASH data, reading length and reading command;
the setting of the DMA parameters in the DMA parameters by the main core comprises the following steps: the source address is the FLASH physical address to be read, and the destination address is the memory physical address for storing FLASH data and the read length.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor when executing the computer program implements the steps of the AMP system based FLASH access processing method of any one of claims 1 to 6.
10. A computer readable storage medium, having stored thereon a computer program, characterized in that the computer program, when being executed by a processor, realizes the steps of the AMP system based FLASH access processing method of any one of claims 1 to 6.
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