CN111324572A

CN111324572A - Chip adopting heterogeneous system

Info

Publication number: CN111324572A
Application number: CN201811535913.8A
Authority: CN
Inventors: 薛长花
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2018-12-14
Filing date: 2018-12-14
Publication date: 2020-06-23

Abstract

The application discloses a chip adopting a heterogeneous system. The chip includes: a CPU; the first input/output interface is connected with a special chip of a narrowband Internet of things NB-IoT protocol; the second input/output interface is connected with the special chip of the grade CATM protocol; a data channel processing DSP chip which is connected with the first input/output interface, the second input/output interface and the CPU and processes the channel from the first input/output interface or the second input/output interface according to a control instruction sent by the CPU; at least one of the capacity size of the data close coupling memory, the capacity size of the instruction close coupling memory and the capacity size of the first-level buffer in the DSP chip are configured according to the hardware requirement of the DSP chip.

Description

Chip adopting heterogeneous system

Technical Field

The present application relates to the field of information processing, and more particularly, to a chip using heterogeneous systems.

Background

With the development of communication and network technologies, the use of new process technologies and integrated multi-core processor methods has been widely used to improve the computational performance of processors. However, as the manufacturing process approaches the physical limit, the development cost of each chip increases gradually, and the effect of obtaining the computational performance by the conventional method of continuously squeezing the process and integrating the multi-core processor is gradually weakened, in this case, people begin to hope to obtain the maximum performance of the current processor architecture as much as possible by changing the design and focusing on the optimization efficiency.

The most primitive SOC architecture is to use a single CPU or CPU cluster to process all traffic, which is a homogeneous computation, using the same type of instruction set and architecture to process all tasks. But isomorphic calculations have limitations. The micro-architecture of the CPU determines that the speciality of the CPU is to process control services such as branch prediction, out-of-order execution, storage access and the like. Because the number of internal computing units of the CPU is small, parallel computation, multiply-accumulate computation and the like of a large amount of data can be realized only by increasing the running frequency of the CPU or increasing the number of the CPU. However, these two methods have high process requirements, and thus, both the power consumption and the cost of the CPU increase. In order to solve the problem, heterogeneous computation is introduced, namely a parallel processing mode is realized by using different types of instruction sets and computing units of an architecture. Heterogeneous computing systems are as follows:

a heterogeneous system of CPU + GPU. The heterogeneous system fully utilizes the control service capability of the CPU and the parallel processing capability of the GPU to improve the computing performance of the whole system. Typical AMDs are heterogeneous systems using CPU + GPU. However, because the GPU has less algorithm relevance, if the algorithm used is not serial, the GPU cannot exert parallel computing power well.

And 2, a CPU + FPGA heterogeneous system. The FPGA not only supports data parallelism, but also supports pipeline parallelism, and the parallel calculation solves the problems of the GPU. The heterogeneous system architecture is realized by embedding an FPGA in a typical CPU of Intel. However, the price of a single FPGA is expensive, the cost increases in mass production, and the feasibility of using a CPU + FPGA chip is not great for small companies in the market.

To balance the shortcomings of the two typical architectures above, ASICs will be a trend for heterogeneous computing.

The Internet of Things (IoT) was originally mentioned in 1999, that is, a network for intelligently identifying, locating, tracking, monitoring and managing any object by connecting any object with the Internet through information sensing devices such as radio frequency identification (RFID, RFID + Internet), infrared sensor, global positioning system, laser scanner, gas sensor, etc. according to a predetermined protocol, and exchanging and communicating information. Simply, the internet of things is the internet with which things are connected.

The CAT-M1 (category) and NB-IoT (narrowband Internet of things) standards established by 3GPPR13 are the two most hot standards in the technology of the Internet of things at present. CAT-M1 and NB-IoT are considered as the most potential technologies of the Internet of things, and the two technologies are suitable for different application scenarios, but most people generally consider NB-IoT to be more advantageous than CAT-M1 in terms of coverage, cost and power consumption, and the Internet of things chips appearing in the chip market are based on the NB-IoT standard. However, there is data showing that CAT-M1 is actually better than NB-IoT in coverage and power consumption, and that CATM-M1 is faster. Therefore, the internet of things chip based on the CAT-M1 standard appears in the near future.

The internet of things chip we have successfully completed at present is based on NB-IoT standards and is pre-investigating and evaluating the internet of things chip of CATM. In the era of internet of things, along with digital transformation, it needs to be connected more swiftly and also needs to process data more effectively.

Disclosure of Invention

In order to solve the technical problem, the application provides a chip adopting a heterogeneous system, which can reduce the hardware cost of the chip on the premise of ensuring the performance.

To achieve the objective of the present application, the present application provides a chip using a heterogeneous system, including:

CPU；

a first input/output interface connected with the dedicated chip of the NB-IoT protocol;

the second input/output interface is connected with the special chip of the CATM protocol;

a data channel processing DSP chip which is connected with the first input/output interface, the second input/output interface and the CPU and processes the channel from the first input/output interface or the second input/output interface according to a control instruction sent by the CPU;

at least one of the capacity size of the data close coupling memory, the capacity size of the instruction close coupling memory and the capacity size of the first-level buffer in the DSP chip are configured according to the hardware requirement of the DSP chip.

In one exemplary embodiment, the number of the data close coupled memories and/or the instruction close coupled memories is at least two;

when a special chip of an NB-IoT protocol is operated, one part of the data close coupling memory and/or the instruction close coupling memory is in an operating state, and the rest part of the data close coupling memory and/or the instruction close coupling memory is in a closing state; when the special chip of the CATM protocol is operated, all the data close coupling memory and/or the instruction close coupling memory are in working state.

In one exemplary embodiment, the primary buffer is in a closed state while running a dedicated chip of NB-IoT protocol; the second buffer is in a working state.

In one exemplary embodiment, the signal frequency of the DSP includes a first frequency and a second frequency; wherein the first frequency is within a preset low frequency range and the second frequency is within a preset high frequency range;

when running a dedicated chip of an NB-IoT protocol, the DSP adopts a first frequency to process the data received by the first input/output interface; and when the special chip of the CATM protocol is operated, the DSP adopts a second frequency to process the data input by the second input/output interface.

In one exemplary embodiment, the chip further includes:

and the controller controls one of the special chip of the NB-IoT protocol and the special chip of the CATM protocol to be in a working state.

In an exemplary embodiment, the CPU, the DSP and the peripheral system-on-chip form a first chip, and are connected to the NB-IoT protocol dedicated chip through a reserved first input/output interface, and are connected to the CATM protocol dedicated chip through a reserved second input/output interface.

In one exemplary embodiment, the first chip further includes:

a memory storing configuration information of the dedicated chip of the NB-IoT protocol and/or the dedicated chip of the CATM protocol;

the CPU utilizes the configuration information in the memory to configure the special chip of the NB-IoT protocol and/or the special chip of the CATM protocol.

In one exemplary embodiment, the first chip, the NB-IoT protocol specific chip, the CATM protocol specific chip are packaged together.

In one exemplary embodiment, the first chip further includes:

one or at least two input/output interfaces, wherein each input/output interface is connected with a special chip corresponding to a standard or an algorithm;

and the CPU controls the connection state of the special chip corresponding to the standard or algorithm and the corresponding input/output interface.

In one exemplary embodiment, the first chip further includes:

the memory is used for storing the configuration information of the special chip corresponding to the standard or the algorithm;

and the CPU configures the special chip corresponding to the standard or the algorithm by using the configuration information in the memory.

The embodiment that this application provided, through the special chip of two input interface connection NB-IoT agreements and the special chip of CATM agreement, realize realizing the purpose that realizes the required function of two agreements on a chip, realize that two special chips use the purpose of same group CPU and DSP, saved the hardware cost, in addition, through the adjustment to the capacity of hardware in the DSP, effectively guaranteed the performance when CATM agreement moves, realize under the prerequisite of the hardware performance of guaranteeing the chip, reduced the hardware cost of chip.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.

FIG. 1 is a block diagram of a chip using a heterogeneous system according to the present invention;

fig. 2 is a schematic diagram of an NB-IoT standard-based internet-of-things heterogeneous system in the related art;

FIG. 3 is a schematic diagram of a heterogeneous system of the Internet of things of the CATM standard provided herein;

FIG. 4 is a schematic diagram of a CPU + DSP + ASIC heterogeneous Internet of things system provided by the present application;

fig. 5 is a schematic diagram of a CPU + DSP + ASIC heterogeneous system provided in the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Fig. 1 is a structural diagram of a chip using a heterogeneous system according to the present invention. The chip shown in fig. 1 includes:

CPU；

In the present exemplary embodiment, the NB-IoT protocol dedicated chip and the CATM protocol dedicated chip are connected through two input interfaces, so that the purpose of realizing the functions required by the two protocols on one chip is achieved; when the chip is confirmed to be capable of executing the NB-IoT protocol and the CATM protocol, the requirement information of the two protocols on the DSP of the physical layer is obtained, and the requirement information with high performance of the DSP is selected for hardware configuration. For example, the CATM peak rate is 375Kbps and the NB peak rate is approximately 50 Kbps. So CATM has higher performance requirements for DSP. From the aspect of hardware configuration of the DSP, on one hand, the capacity of a Tightly Coupled Memory (TCM) can be increased, so that the advantages of the TCM can be fully utilized, and the time delay of accessing the memory is reduced to improve the overall performance; on the other hand, the capacity of the first-level cache can be increased, so that the area of on-chip storage can be reduced on the basis of improving the instruction fetching performance by dynamically accessing the external memory. The increased size of these two aspects of memory is balanced by software requirements and performance.

The cost of the hardware performance of the added DSP is lower than the cost of adding a CPU and a DSP, so that the hardware cost is reduced on the premise of ensuring the hardware performance.

The chip embodiment provided by the application, through the special chip of two input interface connection NB-IoT agreements and the special chip of CATM agreement, realize realizing the purpose that two agreement required functions are realized on a chip, realize that two special chips use the purpose of same group CPU and DSP, hardware cost has been saved, in addition, through the adjustment to the capacity of hardware in the DSP, effectively guaranteed the performance when CATM agreement moves, realize under the prerequisite of guaranteeing the hardware performance of chip, the hardware cost of chip has been reduced.

The technical features provided by the present application are explained as follows:

In the exemplary embodiment, the number of the data close-coupled memory and/or the instruction close-coupled memory is at least two, which aims to ensure that when a dedicated chip of the CATM protocol is operated, the application provides hardware performance of the chip, and when the dedicated chip of the NB-IoT protocol is operated, the performance is not insufficient, so that a part of the data close-coupled memory and/or the instruction close-coupled memory is in an operating state, and the rest of the data close-coupled memory and/or the instruction close-coupled memory is in a shutdown state, thereby reducing power consumption of the chip.

In the exemplary embodiment, the primary buffer is set to ensure that the application provides the hardware performance of the chip when the dedicated chip of the CATM protocol is run, and the primary buffer is not needed when the dedicated chip of the NB-IoT protocol is run, and the primary buffer can be closed, so that the power consumption of the chip is reduced.

By setting the adjustable signal frequency of the DSP, the two protocols can work conveniently in the required signal frequency, and the working performance of the chip is ensured.

In one exemplary embodiment, the chip further includes:

In the exemplary embodiment, the controller may be a software module integrated on the CPU, so as to effectively control the hardware cost of the chip.

When the NB-IOT protocol is used, dtcm0 and itcm0 are used, in which case dctm1 and itcm1 are in shutdown power-off mode to reduce power consumption. Whether the first-level cache icache and the dcache are used depends on software requirements, and if the first-level cache icache and the dcache are not used, the corresponding storage is also in a shutdown mode. When the CATM protocol is used, dtcm0+ dtcm1, itcm0+ itcm1 and icache + dcache are used.

In one exemplary embodiment, the first chip further includes:

The 3GPP defined network access technology standards are from LTE CAT1 to CAT 10. The standard evolves, and the application scenario differs, but only involves changes in part of the hardware logic and changes in the associated software. Part of the hardware logic change can also be made into a special ASIC chip and connected to a fixed chip in an abutting mode. As shown in fig. 4. This approach may also reduce the chip cost for optimizing protocol evolution.

In an exemplary embodiment, in a chip design stage, a fixed chip is designed separately from a dedicated chip based on NB internet of things algorithm, and an IO interface is reserved on both chips. The NB special chip is only used for realizing algorithms and standards, is small in area and has the advantage of repeatable design. The configuration of the NB-specific chip is made in a fixed chip. And when the packaging is carried out, the packaging is carried out between the two through the IO port. When the 3gpp r14 has an update to the NB standard, only the NB-specific chip may be redesigned and then repackaged. This may reduce the design complexity and cost of chip optimization.

In one exemplary embodiment, in the chip design phase, a fixed chip is designed separately from two dedicated chips, and an IO interface is reserved on each chip. The two special chips are respectively used for realizing the algorithms and standards of NB and CATM, the area of the special chips is not large, and the special chips have the advantage of repeatable design. The configuration of the special chip is arranged in the fixed chip, and the fixed chip and the two special chips are sealed through an IO port during packaging. Because different standards or algorithms are different in actual application scenes, a CPU can be flexibly used in the actual chip using process, and a special chip corresponding to the standard or algorithm of the NB or the CATM is selected by configuring a configuration file in a fixed chip through software.

In one exemplary embodiment, the first chip further includes:

In one exemplary embodiment, the fixed chip is designed separately from a single dedicated chip and the IO interface is reserved on both chips in the chip design phase. The special chip is only used for realizing the algorithm and the standard, the standard or the algorithm is not limited to the standard or the algorithm of the Internet of things, the area of the special chip is not large, and the special chip has the advantage of repeatable design. The configuration of the dedicated chip is made in a fixed chip. And when the packaging is carried out, the packaging is carried out between the two through the IO port. When the standard or algorithm is updated, the dedicated chip can be redesigned only and then packaged again. This may reduce the design complexity and cost of chip optimization.

In one exemplary embodiment, in the chip design phase, a fixed chip is designed separately from a plurality of dedicated chips, and an IO interface is reserved on each chip. Multiple dedicated chips are used to implement different algorithms and standards that are not limited to internet of things standards or algorithms. The area of the device is not too large, and the device has the advantage of repeatable design. The configuration of the special chip is arranged in the fixed chip, and the fixed chip and the special chip are sealed through an IO interface before being packaged. Because different standards or algorithms are different in actual application scenes, a CPU can be flexibly used in the actual chip using process, and special chips corresponding to different standards or algorithms can be selected by configuring configuration files in the fixed chip through software.

The following explains the hardware structure provided in the present application:

based on the Internet of things chip and the heterogeneous computing system, the invention provides a heterogeneous Internet of things chip system based on a CPU + DSP + ASIC.

Fig. 2 is a schematic diagram of an NB-IoT standard-based internet-of-things heterogeneous system in the related art; as shown in fig. 2, the internet of things chip is a heterogeneous system based on NB-IoT standard, using CPU + DSP. The CPU mainly processes control services, the DSP mainly processes operation services of a protocol stack and a physical layer, and an IoT hardware module is hung on a bus to realize an NB-IoT protocol.

Fig. 3 is a schematic diagram of an internet of things heterogeneous system of the CATM standard provided in the present application. As shown in fig. 3, the next generation internet of things chip is prepared based on the CATM standard, and compared with the NB-IoT standard chip, the differences are: IoT protocol hardware is implemented differently and physical layer software processes are different and the requirements on the physical layer processor DSP are different.

Under the condition of removing the programmable factor of the software part, different points of hardware are shown as a dotted line frame part in fig. 3, the realization of the protocol is different and is embodied on an IoT hardware module and the requirement on a DSP is different. The difference is caused by the fact that the CATM has a higher coverage and rate and places higher demands on the processor's computing power. After the reason is determined, the instruction fetching efficiency and the operation performance are improved by adding a first-level cache or adding a tightly coupled memory.

The following is a description of an application example provided by an embodiment of the present invention:

FIG. 4 is a schematic diagram of a CPU + DSP + ASIC heterogeneous Internet of things system provided by the present application; as shown in fig. 4, the functions of the modules are as follows:

a CPU: and processing the application layer control type service.

And (4) DSP: and processing protocol stack and physical layer operation services, wherein dtcm0, dtcm1, itcm0 and itcm1 are respectively a data tightly-coupled memory and an instruction tightly-coupled memory.

Peripheral: and the peripheral part comprises a peripheral IP and an external memory.

NB-IoT ASIC: a dedicated chip implementing the NB _ IoT standard.

CATM ASIC: a special chip for realizing the CATM standard.

Config: and the configuration module is used for configuring which internal memories are used and configuring which special chip is used.

When the execution of the NB protocol and the CATM protocol is confirmed, the requirement information of the NB protocol and the CATM protocol on the DSP of the physical layer is obtained, and the requirement information with high DSP performance is selected for hardware configuration. For example, the CATM peak rate is 375Kbps and the NB peak rate is approximately 50 Kbps. So CATM has higher performance requirements for DSP. On one hand, the capacity of the tightly coupled memory can be increased from the aspect of the hardware configuration of the DSP, so that the advantages of the TCM can be fully utilized, and the time delay of accessing the memory is reduced to improve the overall performance; on the other hand, the capacity of the first-level cache can be increased, so that the area of on-chip storage can be reduced on the basis of improving the instruction fetching performance by dynamically accessing the external memory. The increased size of these two aspects of memory is balanced by software requirements and performance.

Fig. 5 is a schematic diagram of the CPU + DSP + ASIC heterogeneous system provided in the present application, and as shown in fig. 5, when the NB-IOT protocol is used, dtcm0 and itcm0 are used, and in this scenario, dctm1 and itcm1 are in shutdown mode to reduce power consumption. Whether the first-level cache icache and the dcache are used depends on software requirements, and if the first-level cache icache and the dcache are not used, the corresponding storage is also in a shutdown mode. When the CATM protocol is used, dtcm0+ dtcm1, itcm0+ itcm1 and icache + dcache are used. Meanwhile, the DSP needs to have a frequency adjustable function, high frequency is used under a CATM protocol, and low frequency is used under an NB-IOT protocol.

The system comprises a CPU, a DSP and a peripheral SoC (system on chip) architecture, wherein the SoC architecture of the CPU, the DSP and the peripheral is independently used as an ASIC1 chip, an IO (input/output) interface butted with a special chip is reserved, a corresponding special ASIC2 chip is developed according to a current NB-IoT (NB-IoT) protocol, the IO interface is reserved, a corresponding special ASIC3 chip is developed according to a current CATM (control independent technology) protocol, the IO interface is reserved, and when the chips are packaged, the three chips of ASIC1, ASIC2 and ASIC3 are sealed. And finally, respectively developing physical layer software aiming at protocols of the CATM and the NB, and when the chip is manufactured into a product, determining an application scene specifically by using the standard of the NB or the standard of the CATM through Config configuration.

Since the internet of things standard is still in the process of development, some specifications of the NB standard, for example, are set in the 3gpp R14, and the R13 standard is implemented at present. After the standard is completely determined, only the ASIC special chip of the Internet of things protocol and the corresponding physical layer software can be updated without re-making the chip. Meanwhile, aiming at different chips of different Internet of things standards, a special chip can be made only for hardware implementation of the Internet of things standards, and then different standards are selected according to configuration to be applied to different scenes, so that the public part can be kept unchanged, and the cost is saved for next generation optimization of the chip. In addition, the heterogeneous system architecture is not limited to the chip of the Internet of things, and is suitable for the chip of the terminal data card.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A chip employing a heterogeneous system, comprising:

CPU；

the first input/output interface is connected with a special chip of a narrowband Internet of things NB-IoT protocol;

the second input/output interface is connected with the special chip of the grade CATM protocol;

2. The chip of claim 1, wherein:

the number of the data close coupling memories and/or the instruction close coupling memories is at least two;

3. The chip of claim 2, wherein:

when a special chip of an NB-IoT protocol runs, the primary buffer is in a closed state; the second buffer is in a working state.

4. The chip of claim 1, wherein:

the signal frequency of the DSP comprises a first frequency and a second frequency; wherein the first frequency is within a preset low frequency range and the second frequency is within a preset high frequency range;

5. The chip of claim 1, wherein the chip further comprises:

6. The chip of claim 1, wherein:

the CPU, the DSP and a peripheral system level chip form a first chip, are connected with a special chip of an NB-IoT protocol through a reserved first input/output interface and are connected with a special chip of a CATM protocol through a reserved second input/output interface.

7. The chip of claim 6, wherein the first chip further comprises:

8. The chip of claim 1, wherein the first chip, the NB-IoT protocol specific chip, and the CATM protocol specific chip are packaged together.

9. The chip of claim 6, wherein the first chip further comprises:

10. The chip of claim 9, wherein the first chip further comprises: