CN111324566A

CN111324566A - Synchronous RS422 data receiving equipment based on USB interface

Info

Publication number: CN111324566A
Application number: CN201811543240.0A
Authority: CN
Inventors: 李战行; 孙东芳; 白志强; 潘少朋; 于云翔
Original assignee: Beijing Huahang Radio Measurement Research Institute
Current assignee: Beijing Huahang Radio Measurement Research Institute
Priority date: 2018-12-17
Filing date: 2018-12-17
Publication date: 2020-06-23

Abstract

A synchronous RS422 data receiving device based on a USB interface comprises a level conversion module, a level conversion module and a Field Programmable Gate Array (FPGA), wherein the level conversion module converts an RS422 level signal into a linear voltage transistor logic (LVTTL) signal and outputs the LVTTL signal to the FPGA for processing; the programmable logic device (FPGA) is used for receiving data, synchronous code detection is carried out through shifting, conversion from bit flow to Byte data is completed, the Byte data is stored into an FIFO inside the FPGA, and the data of the FIFO inside the FPGA is transferred to a USB interface chip endpoint FIFO; the USB interface transmits the data in the endpoint FIFO to the computer through a USB bus according to a USB reading request of the computer interface; and the power supply module obtains a 5V direct current power supply from the USB interface. The invention aims to meet the test requirement of the data output device with the synchronous RS422 interface.

Description

Synchronous RS422 data receiving equipment based on USB interface

Technical Field

The invention belongs to the field of test equipment, and particularly relates to synchronous RS422 data receiving equipment.

Background

The synchronous RS422 interface is a communication interface commonly used on military equipment, Byte bytes are transmitted according to bit stream according to an input source clock beat through a pair of clock lines and a pair of data lines, the interference resistance is equivalent to that of the asynchronous RS422, and the transmission efficiency is far higher than that of an asynchronous RS422 transmission mode. The synchronous RS422 interface is currently used more as a communication interface between the data source and the wireless data link. In the process of converting the data from Byte to Bit stream, the position information of the Bit-to-Byte mapping is lost. In order to solve the problem, two bytes 0xEB and 0x90 are regularly inserted as a synchronization code when the Byte data is transmitted, Bit is shifted at a receiving end, and when the Bit is equal to the synchronization code, the corresponding relation between Bit and Byte can be determined, so that the data can be synchronized and recovered.

At present, PCI/PCIe and other general digital acquisition cards are mostly adopted, and the system is only suitable for industrial personal computers with card slots, and is large in size and complex in development difficulty.

Disclosure of Invention

The invention aims to meet the test requirement of data output equipment (pod and seeker) with a synchronous RS422 interface. The system meets the requirements of real-time acquisition and storage, has the advantages of hardware synchronization, low cost and easy portability.

A synchronous RS422 data receiving device based on a USB interface comprises a level conversion module, a programmable logic device (FPGA), the USB interface and a power supply module; the level conversion module converts the RS422 level signal into an LVTTL signal and outputs the LVTTL signal to the FPGA for processing; the programmable logic device (FPGA) is used for receiving data, synchronous code detection is carried out through shifting, conversion from bit flow to Byte data is completed, the Byte data is stored into an FIFO inside the FPGA, the FIFO state of a USB interface chip endpoint is detected, and the data of the FIFO inside the FPGA is transferred to the FIFO of the USB interface chip endpoint; the USB interface transmits the data in the endpoint FIFO to the computer through a USB bus according to a USB reading request of the computer interface; the power supply module obtains a 5V direct current power supply from the USB interface and converts a power supply required by an on-board chip by adopting the LDO.

The invention has low cost, low power consumption and light weight, can be used on equipment with a USB2.0 interface, such as a notebook computer and the like, and has easy portability and wider application range compared with a PCI/PCIe and other general digital acquisition cards. The invention solves the problem of testing the synchronous RS422 interface and meets the test requirement of military load equipment in the market.

Drawings

FIG. 1 is a block diagram of a synchronous RS422 data acquisition device;

FIG. 2 is a synchronization principle;

FIG. 3 is a state machine for FPGA control USB endpoint FIFO write control.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

The device realizes data acquisition through a universal USB2.0 data transmission interface, selects a mature, stable and reliable mainstream chip in the aspect of device selection, and considers the requirements of small volume and low power consumption.

A synchronous RS422 data receiving device based on a USB interface, as shown in fig. 1, includes a level conversion module, a programmable logic device, a USB interface, and a power supply module.

In the level conversion module, the low-voltage high-speed four-way differential line receiver AM26LV32 of the TI company is adopted in this embodiment, an RS422 level signal is converted into an LVTTL signal, and an output signal is accessed to the FPGA. The chip adopts 3.3V power supply, and the maximum wire rate of 32Mbps is supported.

The programmable logic device (FPGA) adopts Spartan6 series FPGA of Xilinx company, the selected model is XC6SLX9, and a 45nm low-power-consumption technology is adopted, so that the power consumption, the performance and the cost are well balanced. The development is realized through a hardware description language.

The following functions are realized, the DATA converted into LVTTL level and the associated clock CLK signal are received, and by performing a shift operation on the DATA signal, it is determined whether the DATA in the shift register is equal to 0xEB90, if so, the DATA is synchronized, otherwise, the shift is continued until the DATA is synchronized, as shown in fig. 2. And (3) forming Byte by the synchronized data and storing the Byte into an internal FIFO (first in first out) of the FPGA, and for the data input rate of 10Mbps, the depth of the FIFO is not less than 256. And detecting the state of the double ping-pong FIFO of the USB endpoint, reading data of the internal FIFO of the FPGA and writing the data into the endpoint FIFO when the endpoint FIFO is not empty, as shown in FIG. 3.

The USB interface adopts a CY7C68013 chip of Cypress technology, a 51-chip microcomputer inner core is arranged in the USB interface, a USB2.0 protocol is integrated, official firmware is adopted, the USB2.0 function can be completed only by simple configuration, data transmission is performed between the USB interface and the FPGA in a double-ping-pong Slave FIFO mode,

the power supply module adopts TLV1117LV33 and TLV1117LV18 low-voltage difference linear voltage-stabilizing chips of TI company to convert a 5V VBUS direct-current power supply provided by a USB interface into 3.3V and 1.2V required by equipment.

The device is matched with an official API function provided by a USB2.0 chip manufacturer, data acquisition and storage can be realized, the device is simple and easy to use, low in cost, easy to carry, stable and reliable in the actual use process, and the problem of acquiring synchronous RS422 data is solved.

Claims

1. A synchronous RS422 data receiving device based on a USB interface comprises a level conversion module, a programmable logic device (FPGA), the USB interface and a power supply module; the level conversion module converts the RS422 level signal into an LVTTL signal and outputs the LVTTL signal to the FPGA for processing; the programmable logic device (FPGA) is used for receiving data, synchronous code detection is carried out through shifting, conversion from bit flow to Byte data is completed, the Byte data is stored into an FIFO inside the FPGA, the FIFO state of a USB interface chip endpoint is detected, and the data of the FIFO inside the FPGA is transferred to the FIFO of the USB interface chip endpoint; the USB interface transmits the data in the endpoint FIFO to the computer through a USB bus according to a USB reading request of the computer interface; the power supply module obtains a 5V direct current power supply from the USB interface and converts a power supply required by an on-board chip by adopting the LDO.

2. The synchronous RS422 data receiving device according to claim 1, wherein said level conversion module uses a low voltage high speed four-way differential line receiver AM26LV32 of TI corporation, and is powered by 3.3V, and supports a line rate of up to 32 Mbps.

3. The synchronous RS422 data receiver of claim 1, wherein said programmable logic device (FPGA) is a Spartan6 series FPGA from Xilinx corporation, selected as model XC6SLX9, developed through a hardware description language.

4. The synchronous RS422 DATA receiving apparatus of claim 1 or 3, wherein a programmable logic device (FPGA) receives the DATA converted into LVTTL level and the associated clock CLK signal, judges whether the DATA in the shift register is equal to 0xEB90 by shifting the DATA signal, if so, the DATA is synchronized, otherwise, the shifting is continued until the DATA is synchronized, and stores the synchronized DATA into Byte stored in an internal FIFO of the FPGA; and detecting the state of the double ping-pong FIFO of the USB endpoint, reading the data of the FIFO inside the FPGA when the FIFO of the endpoint is not empty, and writing the data into the FIFO of the endpoint.

5. The synchronous RS422 data receiving apparatus of claim 4 wherein the FIFO depth is not less than 256 for a 10Mbps data input rate.

6. The synchronous RS422 data receiving device of claim 1, wherein the USB interface uses CY7C68013 chip of Cypress technology, has 51 single chip core inside, integrates USB2.0 protocol, uses official firmware, and uses double ping-pong Slave FIFO mode to transmit data between FPGA.

7. The synchronous RS422 data receiving device as claimed in claim 1, wherein the power supply module uses TLV1117LV33 and TLV1117LV18 low dropout linear regulator chips of TI company to convert the 5V VBUS DC power provided by the USB interface into 3.3V and 1.2V required by the device.

8. The synchronous RS422 data receiving device of claim 17 wherein the low dropout linear regulator chip cooperates with an official API function provided by a USB2.0 chip manufacturer to implement data collection and storage.