CN111324498A

CN111324498A - Hardware information detection device, identification device and method

Info

Publication number: CN111324498A
Application number: CN202010120777.7A
Authority: CN
Inventors: 李博
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2020-02-26
Filing date: 2020-02-26
Publication date: 2020-06-23

Abstract

The invention discloses a hardware information detection device, a hardware information identification device and a hardware information identification method. The hardware information detection device includes: the processing device comprises a detection port, the detection port is used for being connected to a resistance-capacitance circuit of hardware to be detected, the default level of the connection point of the detection port and the resistance-capacitance circuit in the hardware to be detected is a first level, wherein the processing device executes the following processing: setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level; setting the detection port to an interrupt mode triggered by a first level; detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and determining the information of the hardware to be detected based on the trigger time.

Description

Hardware information detection device, identification device and method

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a hardware information detection device, a hardware information identification device and a hardware information detection method.

Background

At present, the development of electronic products is more and more global, and the more the electronic products are updated, the faster. In addition, the number of the adapting peripheral devices of the electronic products is increasing. Accordingly, there is a need in the production industry to identify hardware version information for electronic products, and/or product information for peripherals.

For example, an electronic product needs to be supplied to users in many countries. Users in different countries have different customization needs. Thus, different versions of hardware are designed for different countries. Furthermore, at the time of product update, the software needs to identify the version of the hardware in order to perform the corresponding configuration. When product updates are fast, multiple different versions of hardware need to be set up and identified. In addition, there are more and more peripherals to which electronic products can be connected, and therefore, product information of different peripherals needs to be identified, for example, the peripheral is a camera, an earphone, a charger, or the like, or the model of the camera, the earphone, the charger, or the like.

There are two main ways of identifying the hardware version today.

In the first method, a hardware version is identified using a GPIO (general purpose input output) interface of a CPU and a preset pull-up/down resistor. Specifically, as shown in fig. 1, 4 resistance positions R1, R2, R3, R4 may be provided between the power source VCC and the ground. R1, R2 are connected in series between the power VCC and ground, and the first GPIO interface GPIO 1 of the CPU is connected between R1, R2. R3, R4 are connected in series between the power VCC and the ground, and the second GPIO interface GPIO 2 of the CPU is connected between R1, R4. Therefore, different high and low levels can be detected through the GPIO 1 and GPIO 2 interfaces, and therefore the version of hardware is determined. Table 1 shows the different settings of R1, R2, R3, R4, the detected levels of GPIO 1 and GPIO 2, and the corresponding hardware versions 1-4.

TABLE 1

R1

R2

R3

R4

GPIO

1

GPIO 2

Hardware version 1

10KΩ

Non-sticking

10KΩ

Non-sticking

Height of

Hardware version 2

Non-sticking

10KΩ

Non-sticking

10KΩ

Is low in

Hardware version 3

Non-sticking

10KΩ

Non-sticking

Is low in

Height of

Hardware version 4

10KΩ

Non-sticking

10KΩ

Height of

Is low in

In the first method, if multiple hardware versions need to be detected, multiple GPIO (general purpose input output) interfaces and multiple sets of pull-up and pull-down resistors are required. This approach may waste limited GPIO port resources. In addition, multiple sets of pull-up and pull-down resistors can affect device layout and routing.

In the second method, different divided voltage values can be detected using an ADC (analog-to-digital conversion) port of the CPU, thereby determining the hardware version. As shown in fig. 2, resistors R5, R6 are connected in series between the power supply VCC and the ground, and the ADC port is connected between R5 and R6. By setting different R5, R6, different voltage division values can be generated at the ADC port. The divided voltage values detected by the ADC ports may represent different hardware versions. By way of example, Table 2 below shows the hardware versions 1-4 and the corresponding resistances of resistors R5, R6.

TABLE 2

	R5	R6
			Hardware version 1	1KΩ	10KΩ
Hardware version
	2	2KΩ	10KΩ
Hardware version 3				3KΩ	10KΩ
	Hardware version 4	4KΩ	10KΩ

Generally, in a processing device such as a CPU, there are fewer ADC (analog-to-digital conversion) ports/pins and limited resources. Therefore, there are typically no extra ADC pins for hardware version detection. In addition, the analog-to-digital conversion process is complex and occupies more processing resources, so that the resource waste is caused to a certain extent when the analog-to-digital conversion process is used for hardware version detection.

Therefore, a new technical solution for detecting and identifying hardware version or product information is needed.

Disclosure of Invention

The embodiment of the invention provides a hardware information detection device, a hardware information identification device and a hardware information detection method, and aims to solve the technical problem of how to efficiently detect hardware information.

In order to solve the above-mentioned technical problems, the present invention has been accomplished as described above.

In a first aspect, an embodiment of the present invention provides a hardware information detection apparatus, including: the processing device comprises a detection port, the detection port is used for being connected to a resistance-capacitance circuit of hardware to be detected, the default level of the connection point of the detection port and the resistance-capacitance circuit in the hardware to be detected is a first level, wherein the processing device executes the following processing: setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level; setting the detection port to an interrupt mode triggered by a first level; detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and determining the information of the hardware to be detected based on the trigger time.

In a second aspect, an embodiment of the present invention provides a hardware information identification apparatus, including a resistor-capacitor circuit, where the resistor-capacitor circuit includes a connection point for connecting to a detection port, a default level of the connection point in hardware to be detected is a first level, and a resistor and a capacitor of the resistor-capacitor circuit are set to make a time when the resistor-capacitor circuit switches from a second level to the first level identify information of the hardware to be detected.

In a third aspect, an embodiment of the present invention provides a hardware information detection method, including: setting the level of a connection point of the detection port and the resistor-capacitor circuit to a second level different from a first level through the detection port, wherein the first level is a default level of the connection point in the hardware to be detected; setting the detection port to an interrupt mode triggered by a first level; detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and determining the information of the hardware to be detected based on the trigger time.

In the embodiment of the invention, the hardware information is determined by utilizing different discharge times of the RC circuit, so that the hardware information can be detected and identified efficiently.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 shows a circuit diagram of a prior art apparatus for detecting a hardware version.

Fig. 2 shows a circuit diagram of another prior art apparatus for detecting a hardware version.

Fig. 3 is a schematic diagram of a hardware structure of an electronic device implementing various embodiments of the present invention.

Fig. 4 shows a graph of voltage versus time in an RC circuit.

Fig. 5 shows a circuit diagram of a system for detecting hardware information according to the first embodiment.

Fig. 6 shows a circuit diagram of a system for detecting hardware information according to a second embodiment.

Fig. 7 shows a circuit diagram of a system for detecting hardware information according to a third embodiment.

Fig. 8 shows a circuit diagram of a system for detecting hardware information according to the fourth embodiment.

Fig. 9 shows a schematic flow chart of a method of detecting hardware information according to a sixth embodiment.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Fig. 1 is a schematic diagram of a hardware structure of an electronic device that can be used to implement various embodiments of the present invention.

The electronic device 100 includes, but is not limited to: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, processor 110, and power supply 111. Those skilled in the art will appreciate that the electronic device configuration shown in fig. 1 does not constitute a limitation of the electronic device, and that the electronic device may include more or fewer components than shown, or some components may be combined, or a different arrangement of components. In the embodiment of the present invention, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted terminal, a wearable device, a pedometer, a household appliance, a medical device, a network device, and the like.

It should be understood that, in the embodiment of the present invention, the rf unit 101 may be used for receiving and transmitting signals during a message transmission or a call. Specifically, the rf unit 101 receives downlink data from a base station and then processes the received downlink data to the processor 110. In addition, the uplink data is transmitted to the base station. Typically, radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with a network and other devices through a wireless communication system.

The electronic device provides wireless broadband internet access to the user via the network module 102, such as assisting the user in sending and receiving e-mails, browsing web pages, and accessing streaming media.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the network module 102 or stored in the memory 109 into an audio signal and output as sound. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the electronic apparatus 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 includes a speaker, a buzzer, a receiver, and the like.

The input unit 104 is used to receive an audio or video signal. The input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, and the Graphics processor 1041 processes image data of a still picture or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphic processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the network module 102. The microphone 1042 may receive sound and may be capable of processing such sound into audio data. The processed audio data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 101 in case of a phone call mode.

The electronic device 100 also includes at least one sensor 105, such as a light sensor, motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor that can adjust the brightness of the display panel 1061 according to the brightness of ambient light, and a proximity sensor that can turn off the display panel 1061 and/or backlight when the electronic device 100 is moved to the ear. As one type of motion sensor, an accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes), detect the magnitude and direction of gravity when stationary, and can be used to identify the posture of an electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), and identify related functions of vibration (such as pedometer, tapping); the sensors 105 may also include fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., which are not described in detail herein.

The display unit 106 is used to display information input by a user or information provided to the user. The Display unit 106 may include a Display panel 1061, and the Display panel 1061 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 107 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. Specifically, the user input unit 107 includes a touch panel 1071 and other input devices 1072. Touch panel 1071, also referred to as a touch screen, may collect touch operations by a user on or near the touch panel 1071 (e.g., operations by a user on or near touch panel 1071 using a finger, stylus, or any other suitable object or attachment). The touch panel 1071 may include two parts of a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 110, and receives and executes commands sent by the processor 110. In addition, the touch panel 1071 may be implemented in various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may include other input devices 1072. Specifically, the other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described herein again.

Further, the touch panel 1071 may be overlaid on the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or nearby, the touch panel 1071 transmits the touch operation to the processor 110 to determine the type of the touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of the touch event. Although in fig. 3, the touch panel 1071 and the display panel 1061 are two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated to implement the input and output functions of the electronic device, and is not limited herein.

The interface unit 108 is an interface for connecting an external device to the electronic apparatus 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic apparatus 100 or may be used to transmit data between the electronic apparatus 100 and the external device.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 109 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The processor 110 is a processing device, which is a control center of the electronic device, connects various parts of the whole electronic device by using various interfaces and lines, and performs various functions of the electronic device and processes data by running or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby monitoring the electronic device as a whole. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The processor 110 typically includes a variety of ports (pins), e.g., a plurality of GPIO ports. The GPIO port may be utilized to detect hardware information such as a hardware version of the electronic device 100. In addition, when a peripheral such as a printer, a camera, etc. is connected to the electronic device 100, the processor 110 may detect hardware information of the peripheral through the GPIO port, thereby identifying the peripheral.

The electronic device 100 may further include a power source 111 (such as a battery) for supplying power to various components, and preferably, the power source 111 may be logically connected to the processor 110 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system.

In addition, the electronic device 100 includes some functional modules that are not shown, and are not described in detail herein.

It is proposed to detect hardware information using GPIO ports with interrupt function using different discharge times of a resistor-capacitor circuit (RC circuit). In the RC circuit, by setting the resistance value of the resistor and the capacitance value of the capacitor to different values, the discharge time of the RC circuit may be different. The larger the time constant τ of the RC circuit, the longer the time required for discharge.

Fig. 4 shows a graph of voltage versus time in an RC circuit. In fig. 4, the voltage Uc in the RC circuit is normalized. As shown in fig. 4, the voltage Uc drops to 0.37Uc over time τ. After a time of 2.3 τ, the voltage Uc drops to 0.10 Uc.

Thus, different hardware information can be detected by detecting different discharge times of the RC circuit. Here, there may be provided a hardware information detecting apparatus including: the processing device comprises a detection port, the detection port is used for being connected to a resistance-capacitance circuit of the hardware to be detected, and the default level of the connection point of the detection port and the resistance-capacitance circuit in the hardware to be detected is a first level. The processing device executes the following processing: setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level; setting the detection port to an interrupt mode triggered by a first level; detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and determining the information of the hardware to be detected based on the trigger time.

For example, the detection port is a GPIO port of the processing device.

In order to ensure that the RC circuit reaches a stable state at the second level, the hardware detection means may wait for more than 100ms after the processing means sets the level of the connection point to the second level through the detection port.

The information of the hardware to be detected may include version information of the hardware to be detected, product information of the hardware to be detected, and the like.

Depending on the circuit settings, the first level and the second level may be a high level and a low level, or a low level and a high level, respectively, or two levels set between a high level and a low level by a special device. The default level refers to a level: under the condition of no external circuit influence, when the hardware to be detected is powered on, under the stable condition, the level of the connection point of the detection port and the RC circuit is a default level.

Because different RC time constants can be set by setting different resistance values and capacitance values, so that various different hardware information can be represented, and various hardware information can be detected only through one GPIO port.

In addition, because a plurality of groups of pull-up and pull-down resistors are not required to be arranged, the wiring resources in hardware can be saved, and the possibility of mutual interference among wirings is reduced.

In addition, the method does not need to occupy limited ADC resources.

Various embodiments are described below with reference to fig. 5-9, respectively.

[ first embodiment ] A method for manufacturing a semiconductor device

Fig. 5 shows the hardware information detection means 110 and the hardware information identification means 120. The hardware information detecting device 110 and the hardware information identifying device 120 may be located in the same electronic device, or may be located in different electronic devices, for example, in a main electronic device and a peripheral device, respectively.

The hardware information detection device 110 includes a processing device 10. The processing device 10 may be a central processor and comprises a detection port, e.g. the GPIO port GPIO a. A timer 11 may also be included in the processing device 10 for recording the time of the trigger.

In fig. 5, the resistor-capacitor circuit in the hardware information identification device 120 is a resistor-capacitor parallel circuit Ra, Ca. One end of the resistor-capacitor parallel circuit is grounded. The other end of the resistor-capacitor parallel circuit is connected to a detection port (GPIOA) as said connection point a. In this case, the first level is a low level, and the second level is a high level.

When the hardware information starts to be detected, the port GPIOA is set to output high. At this time. The level of connection point a is high. For example, wait 100ms to allow the RC parallel circuit to reach a stable state.

Next, setting the port GPIOA to low triggers the interrupt mode and turns on the timer 11.

When the port GPIOA triggers an interrupt, the time of the timer is read out as the trigger time. Different values of Ra and Ca may be set so that the trigger times are different. Different hardware information may be determined based on different trigger times. For example, table 3 below shows resistance values, capacitance values, and their corresponding trigger times.

TABLE 3

[ second embodiment ]

Fig. 6 shows the hardware information detection means 210 and the hardware information identification means 220.

The hardware information detection device 210 includes a processing device 20. The processing means 20 may be a central processor and comprise a detection port, for example a GPIO port GPIO ob. A timer 21 may also be included in the processing means 20 for calculating the trigger time.

In fig. 6, the resistor-capacitor circuit in the hardware information identification means 220 is a resistor-capacitor parallel circuit Rb, Cb. One end of the resistor-capacitor parallel circuit is connected with a power supply VCC. The other end of the resistor-capacitor parallel circuit is connected to a detection port (GPIOA) as said connection point a. In this case, the first level is a high level, and the second level is a low level.

When the hardware information starts to be detected, the port GPIOB is set to the output low level. At this time. The level of connection point B is low. For example, wait 100ms to allow the RC parallel circuit to reach a stable state.

Then, setting the port GPIOB to the high level triggers the interrupt mode and turns on the timer 21.

When the port GPIOB triggers an interrupt, the time of the timer is read out as the trigger time. Different values of Rb and Cb may be set so that the trigger times are different. Different hardware information may be determined based on different trigger times.

In the second embodiment, since the GPIO port is not required to set the high level, the power burden of the processing device can be reduced.

Furthermore, the level required for triggering the GPIOB port can be adjusted to some extent here by setting the level of VCC.

[ third embodiment ]

Fig. 7 shows the hardware information detection means 310 and the hardware information identification means 320.

The hardware information detection device 310 includes a processing device 30. The processing means 30 may be a central processor and comprise a detection port, for example a GPIO port GPIOC. A timer 31 may also be included in the processing device 30 for calculating the trigger time.

In fig. 7, the resistor-capacitor circuits in the hardware information identification device 320 are resistor-capacitor series circuits Rc, Cc. The resistance end Rc of the resistance-capacitance series circuit is connected with a power supply, and the capacitance end Cc of the resistance-capacitance series circuit is grounded. The detection port (GPIOC) is connected between the capacitance Cc and the resistance Rc in the resistance-capacitance series circuit as the connection point C. In this case, the first level is a high level, and the second level is a low level.

When the hardware information starts to be detected, the port GPIOC is set to the output low level. At this time. The level of connection point C is low. For example, wait 100ms to allow the RC series circuit to reach a stable state.

Then, setting the port GPIOC to high triggers the interrupt mode and turns on the timer 31.

When the port GPIOC triggers an interrupt, the time of the timer is read out as the trigger time. Different values of Rc and Cc may be set so that the trigger times are different. Different hardware information may be determined based on different trigger times. For example, table 4 below shows resistance values, capacitance values, and their corresponding trigger times.

TABLE 4

	R1	C1	Time of day
				Hardware version
1	1KΩ	0.1uF	0.1ms
				Hardware version
2	5KΩ	0.1uF	0.5ms
				Hardware version 3	10KΩ	0.1uF	1ms
Hardware version 4	15KΩ	0.1uF	1.5ms
				Hardware version 5	20KΩ	0.1uF	2ms
Hardware version 6	25KΩ	0.1uF	2.5ms
				Hardware version 7	30KΩ	0.1uF	3.0ms
Hardware version 8	35KΩ	0.1uF	3.5ms
				Hardware version 9	40KΩ	0.1uF	4.0ms
Hardware version 10	45KΩ	0.1uF	4.5ms
				Hardware version 11	50KΩ	0.1uF	5.0ms
Hardware version 12	55KΩ	0.1uF	5.5ms
				Hardware version 13	60KΩ	0.1uF	6.0ms
Hardware version 14	65KΩ	0.1uF	6.5ms
				Hardware version 15	70KΩ	0.1uF	7.0ms
Hardware version 16	75KΩ	0.1uF	7.5ms
				Hardware version 17	80KΩ	0.1uF	8.0ms
Hardware version 18	85KΩ	0.1uF	8.5ms
				Hardware version 19	90KΩ	0.1uF	9.0ms
Hardware version 20	95KΩ	0.1uF	9.5ms
				Hardware version 21	100KΩ	0.1uF	10.0ms

[ fourth example ] A

Fig. 8 shows a hardware information detection means 410 and a hardware information identification means 420.

The hardware information detection device 410 includes a processing device 40. The processing means 40 may be a central processor and comprise a detection port, e.g. a GPIO port GPIO d. A timer 41 may also be included in the processing means 40 for calculating the trigger time.

In fig. 8, the resistor-capacitor circuit in the hardware information identification device 420 is a resistor-capacitor series circuit Rd, Cd. The resistance end Rd of the resistance-capacitance series circuit is grounded, and the capacitance end Cd of the resistance-capacitance series circuit is connected with a power supply. And the detection port (GPIOD) is connected between the capacitor Cd and the resistor Rd in the resistor-capacitor series circuit and serves as the connection point D. In this case, the first level is a low level, and the second level is a high level.

When the hardware information starts to be detected, the port GPIOD is set to output high level. At this time. The level of the connection point D is high. For example, wait 100ms to allow the RC series circuit to reach a stable state.

Then, setting the port GPIOD to low triggers the interrupt mode and turns on the timer 41.

When the port GPIOD triggers an interrupt, the time of the timer is read out as the trigger time. Different values of Rd and Cd may be set so that the trigger times are different. Different hardware information may be determined based on different trigger times.

[ fifth embodiment ]

As shown in fig. 5-8, embodiments disclosed herein also include a hardware information identification device that includes a resistor-capacitor circuit, such as an RC series circuit or an RC parallel circuit. The resistor-capacitor circuit comprises a connection point for connecting to the detection port, the default level of the connection point in the hardware to be detected is a first level, and the resistor and the capacitor of the resistor-capacitor circuit are set to enable the time when the resistor-capacitor circuit is switched from a second level to the first level to identify the information of the hardware to be detected. As shown in tables 3 and 4 above, different switching times (trigger times) can be set by different resistance values and capacitance values.

[ sixth embodiment ]

As shown in fig. 9, in step S2, the level of the connection point of the detection port and the resistor-capacitor circuit is set to a second level different from the first level through the detection port, wherein the first level is the default level of the connection point in the hardware to be detected.

In step S4, the detection port is set to an interrupt mode triggered by the first level.

In step S6, the time required for detecting the change of the port level value from the second level to the first level, i.e., the trigger time required for triggering the interrupt, is detected.

In step S8, information of the hardware to be detected is determined based on the trigger time.

The above respective embodiments may be mutually referred to, and in the description about the later embodiment, the description of the same or similar elements as those in the previous embodiment is omitted.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A hardware information detection apparatus comprising:

processing means comprising a detection port for connection to a resistor-capacitor circuit of the hardware to be detected, a default level of a connection point of the detection port and the resistor-capacitor circuit in the hardware to be detected being a first level,

wherein the processing device executes the following processing:

setting a level of the connection point to a second level through the detection port, wherein the second level is different from the first level;

setting the detection port to an interrupt mode triggered by a first level;

detecting the time required for the level value of the detection port to change from the second level to the first level, wherein the time is the trigger time required for triggering interruption; and

and determining the information of the hardware to be detected based on the trigger time.

2. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor parallel circuit, one end of the resistor-capacitor parallel circuit is grounded, and the other end of the resistor-capacitor parallel circuit is connected to the detection port as a connection point, the first level is a low level, and the second level is a high level.

3. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor parallel circuit, one end of the resistor-capacitor parallel circuit is connected to a power supply, and the other end of the resistor-capacitor parallel circuit is connected to the detection port as a connection point, the first level is a high level, and the second level is a low level.

4. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor series circuit, a resistor end of the resistor-capacitor series circuit is connected to a power supply, a capacitor end of the resistor-capacitor series circuit is connected to ground, and the detection port is connected between a capacitor and a resistor in the resistor-capacitor series circuit as the connection point, the first level is a high level, and the second level is a low level.

5. The hardware detection device according to claim 1, wherein, in a case where the resistor-capacitor circuit is a resistor-capacitor series circuit, a resistor end of the resistor-capacitor series circuit is grounded, a capacitor end of the resistor-capacitor series circuit is connected to a power supply, and the detection port is connected between a capacitor and a resistor in the resistor-capacitor series circuit as the connection point, the first level is a low level, and the second level is a high level.

6. The hardware detection device according to claim 1, wherein the information of the hardware to be detected includes at least one of version information of the hardware to be detected and product information of the hardware to be detected.

7. The hardware detection device of claim 1, wherein the detection port is a GPIO port of the processing device.

8. The hardware detection device of claim 1, wherein the hardware detection device waits more than 100ms after the processing device sets the level of the connection point to the second level through the detection port.

9. A hardware information identification apparatus comprising a resistor-capacitor circuit comprising a connection point for connection to a detection port, the connection point having a default level in hardware to be detected which is a first level, the resistor and capacitor of the resistor-capacitor circuit being arranged such that: the time at which the resistor-capacitor circuit transitions from the second level to the first level is used to identify information about the hardware to be tested.

10. A hardware information detection method comprises the following steps:

setting the level of a connection point of the detection port and the resistor-capacitor circuit to a second level different from a first level through the detection port, wherein the first level is a default level of the connection point in the hardware to be detected;

setting the detection port to an interrupt mode triggered by a first level;