CN111324289B - Memory device - Google Patents
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- CN111324289B CN111324289B CN201811532634.6A CN201811532634A CN111324289B CN 111324289 B CN111324289 B CN 111324289B CN 201811532634 A CN201811532634 A CN 201811532634A CN 111324289 B CN111324289 B CN 111324289B
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- 238000013507 mapping Methods 0.000 claims abstract description 81
- 238000011084 recovery Methods 0.000 claims abstract description 19
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The embodiment of the invention discloses a memory, which comprises: the storage module comprises a plurality of data source blocks and at least one data destination block, wherein the data destination block comprises n page areas, and each page area comprises a plurality of pages; the control module is electrically connected with the storage module and is used for controlling the data of at least one data source block to be moved to a data destination block in a data recovery mode and recording mapping information of the data written in the ith page area and the data source block after the ith page area of the data destination block is written. In the embodiment of the invention, the control module intermittently stores the mapping information, so that the written page area before power failure can be determined according to the mapping information after power-on restarting, the data integrity and the effectiveness of the written page area are ensured, the written data of the data destination block is not required to be completely abandoned, the data recovery operation is not required to be executed again, the data recovery efficiency is improved, and the influence of power failure on the data recovery is reduced.
Description
Technical Field
Embodiments of the present invention relate to memory technologies, and in particular, to a memory.
Background
An eMMC (Embedded Multi Media Card) chip is an embedded memory mainly aiming at products such as a mobile phone or a tablet computer. The eMMC chip is integrated with a controller which can provide a standard interface and manage the flash memory, so that a mobile phone manufacturer using the eMMC chip can concentrate on other parts of product development and shorten the time for pushing out products to the market.
The eMMC chip is mainly composed of a controller and flash memory grains, data is stored in the flash memory grains through a write operation, and data is read from the flash memory grains through a read operation. The flash memory which is mainstream in the market at present is NAND flash, has the advantages of small size, large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is also widely applied in the industry. A memory based on NAND flash, such as an eMMC chip, is characterized in that a flash memory conversion layer can recycle garbage in the use process, and data of a plurality of data blocks with less effective data are moved to another empty physical block.
Pages in each physical block of the NAND flash must be written sequentially, and if power is turned off in the writing process, after power is turned on, the memory cannot completely determine the page position of the last operation block after the last power is turned on, so that writing cannot be continued, and the data integrity of the last writing after the last power is turned on cannot be completely ensured. If a garbage collection operation of NAND flash is in progress or is not finished, a power failure occurs, and after restarting power-on, the integrity of the data before power-on cannot be ensured, so that the common processing mode is to discard the written data after discarding the previous operation, and restore the mapping information in the original data. However, this garbage collection needs to be re-executed, and the comparison affects efficiency and wastes a block of data.
Disclosure of Invention
The embodiment of the invention provides a memory, which is used for solving the problem that garbage collection needs to be re-executed due to power failure in the prior art.
The embodiment of the invention provides a memory, which comprises:
a storage module comprising a plurality of data source blocks and at least one data destination block, the data destination block comprising n page areas, each of the page areas comprising a plurality of pages;
the control module is electrically connected with the storage module and is used for controlling at least one data source block to be moved to the data destination block in a data recovery mode, and recording mapping information of the data written in the ith page area and the data source block after the writing of the ith page area of the data destination block is completed, wherein i=1, 2,3, …, n and n are positive integers, and n is more than or equal to 2.
Further, the control module is used for controlling the i+1th page area of the data destination block to write data, and recording mapping information of the data written in the i page area and the data source block.
Further, the control module is further configured to update the mapping location of the data destination block to i after the i-th page area of the data destination block is written.
Further, the control module is further configured to update a mapping position of the data destination block to which no data is written to 0.
Further, the control module is further configured to detect that the mapping position of the data destination block is updated to i after power-up, delete the data in the kth page area, and k=i+1, i+2, i+3, ….
Further, the data destination block includes n page areas, and the data of at least one data source block is written into one page area correspondingly.
Further, the data destination block includes n page areas, and the data of the data source block is written into at least one page area correspondingly.
Further, the storage module is a NAND Flash.
The memory provided by the embodiment of the invention comprises a plurality of data source blocks and at least one data destination block, wherein the data destination block comprises n page areas, and the control module is used for controlling the data of the at least one data source block to be moved to the data destination block in a data recovery mode, and recording the mapping information of the data written in the ith page area and the data source block after the writing of the ith page area of the data destination block is completed. In the embodiment of the invention, the control module records the mapping information of each page area and the data source block after writing each page area, intermittently saves the mapping information, and if power failure occurs in the data recovery mode, the written page area of the last operation block before power failure can be determined according to the mapping information after power-on restarting, thereby ensuring the integrity and effectiveness of the data of the written page area, avoiding completely discarding the written data of the data destination block, avoiding re-executing the data recovery operation, improving the data recovery efficiency and reducing the influence of power failure on the data recovery.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory according to an embodiment of the present invention;
fig. 2 is an internal structure diagram of a data destination block of a memory according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described by means of implementation examples with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a memory according to an embodiment of the present invention, and fig. 2 is an internal structure diagram of a data destination block of the memory according to the embodiment of the present invention. The memory may be selected from any memory module integrated chip or device, such as an eMMC chip integrated with flash particles, and may be selected from other memory module integrated devices in other embodiments. The optional storage module is a flash memory, optionally a NAND flash, and more specifically, the optional storage module is an MLC flash memory, namely a multi-layer storage flash memory.
The memory provided in this embodiment includes: a memory module 10, the memory module 10 including a plurality of data source blocks 11 and at least one data destination block 12, the data destination block 12 including n page areas 12a, each page area 12a including a plurality of pages; the control module 20 is electrically connected to the storage module 10, and the control module 20 is configured to control, in a data recovery mode, moving data of at least one data source block 11 to the data destination block 12, and recording mapping information of the data written in the ith page area 12a and the data source block 11 after the writing of the ith page area 12a of the data destination block 12 is completed, where i=1, 2,3, …, n, n is a positive integer and n is greater than or equal to 2.
In this embodiment, the optional storage module 10 is a flash memory NAND flash. The memory module 10 includes a plurality of physical blocks 10a, wherein physical blocks to which data is written are data blocks, and physical blocks to which data is not written are free blocks. If the valid data in the data block is less, when the garbage collection mode, i.e. the data collection mode, is triggered, the control module 20 may select at least two data blocks with less valid data as the data source block 11, at least one idle block is selected as the data destination block 12, and then move the data of the data source block 11 to the data destination block 12, thereby releasing at least two idle blocks.
In the present embodiment, the data destination block 12 includes n page areas 12a, and each page area 12a includes a plurality of page pages. It should be noted that, the pages inside each block in the flash memory must be sequentially written with data, so that the pages in each page area 12a of the data destination block 12 are all continuous pages, and when two adjacent pages belong to different page areas, the two page areas are also continuous page areas. As shown in fig. 2, which shows an internal structure diagram of the data destination block 12, the data destination block 12 optionally includes pages 0 to 23 and is divided into 4 page areas, pages 0 to 5 are divided into 1 st page area 12a/1, pages 6 to 11 are divided into 2 nd page area 12a/2, pages 12 to 17 are divided into 3 rd page area 12a/3, pages 18 to 23 are divided into 4 th page area 12a/4. Those skilled in the art will appreciate that the number of page areas and the number of pages in a page area in a data destination block may be set by the relevant practitioner at his or her discretion, and the number of pages in different page areas in the data destination block may be the same or different.
In this embodiment, the optional control module 20 is a flash translation layer of the memory. The control module 20 triggers the data reclamation mode periodically or non-periodically, and when the data reclamation mode, i.e. the garbage collection mode, is triggered, the control module 20 controls the data of the plurality of data source blocks 11 with less effective data to be moved to another empty physical block, i.e. the data destination block 12. It should be noted that, the process of the control module 20 moving the data of at least two data source blocks 11 to the data destination block 12 may be alternatively that the data is moved according to the whole data source block 11.
In this embodiment, the control module 20 controls the data of at least one data source block 11 to be moved to the data destination block 12, and records the mapping information between the data written in the i-th page area 12a and the data source block 11 after the i-th page area 12a of the data destination block 12 is written. Here, the control module 20 is provided with a data reclamation mapping table, in which mapping information of each data reclamation operation is recorded, where the mapping information may be a mapping relationship between a physical address of a page area and a physical address of a data source block, a mapping relationship between a physical address of a page area and a logical address of data of a data source block, or a mapping relationship between other data capable of linking the page area and the data source block.
Specifically, after the 1 st page area 12a of the data destination block 12 is written, the control module 20 records the data written in the 1 st page area 12a and the mapping information of the data source block 11 corresponding to the data source area. For example, after the data of the data source block a is written into the 1 st page area of the data destination block and is written, the control module records the mapping relationship between the 1 st page area and the physical address of the data source block a, and/or the control module records the mapping relationship between the 1 st page area and the logical address of the data source block a, so that when the data of the data source block a needs to be read subsequently, the control module directly reads from the 1 st page area of the data destination block according to the mapping relationship. By analogy, the control module 20 records the data written by each page area 12a of the data destination block 12 and the mapping information of the data source block 11 corresponding thereto in the data reclamation mode.
Optionally, the data destination block includes n page areas, and the data of at least one data source block is written into one page area correspondingly. The page of the data-destination block may be uniformly divided into n page areas, or the page area division may be performed according to other means. For example, the control module controls the data of the three data source blocks to be moved to one data destination block, and then the page of the data destination block can be divided into 3 page areas, and the number of pages of each page area can be equal to that of the valid data of the corresponding data source block.
Optionally, the data destination block includes n page areas, and the data of the data source block is written in at least one page area correspondingly. The page of the data-destination block may be uniformly divided into n page areas, or the page area division may be performed according to other means. For example, the control module controls the data of two data source blocks to be moved to one data destination block, and the data of each data source block can correspond to 2 page areas, so that the page of the data destination block can be divided into 4 page areas, and the total number of pages of each two adjacent page areas is equal to the number of pages of the effective data of one data source block corresponding to the total number of pages.
The memory provided in this embodiment includes a storage module including a plurality of data source blocks and at least one data destination block, where the data destination block includes n page areas, and the control module is configured to control, in a data reclamation mode, moving data of the at least one data source block to the data destination block, and record mapping information of the data written in an i-th page area of the data destination block and the data source block after the i-th page area is written. In this embodiment, the control module records the mapping information of each page area and the data source block after writing each page area, intermittently saves the mapping information, if power failure occurs in the data recovery mode, the written page area of the last operation block before power failure can be determined according to the mapping information after power-on restarting, so that the integrity and effectiveness of the data of the written page area are ensured, the written data of the data destination block is not required to be completely discarded, the data recovery operation is not required to be re-executed, the data recovery efficiency is improved, and the influence of power failure on data recovery is reduced.
On the basis of the technical scheme, the optional control module is used for controlling the i+1th page area of the data destination block to write data, and recording mapping information of the data written in the i page area and the data source block. Assuming that the number of pages of a physical block is m, which is currently 128/256/512, the physical block can be divided into 4 page areas, and each page area can be m/4 pages. When the control module moves data under the data recovery module, the write operation sequence is as follows: 1. writing a 1 st page area; 2. writing the 2 nd page area, and simultaneously recording mapping information of the 1 st page area and a data source block corresponding to the 1 st page area; 3. writing a 3 rd page area, and simultaneously recording mapping information of the 2 nd page area and a data source block corresponding to the 2 nd page area; 4. writing a 4 th page area, and simultaneously recording mapping information of a 3 rd page area and a data source block corresponding to the 3 rd page area; 5. after the 4 th page area is written, the data destination block is fully written, and the mapping information of the 4 th page area and the data source block corresponding to the 4 th page area is recorded. Obviously, when the current page area is written, the writing operation of the previous page area is completed, and the mapping information of the previous page area is recorded at the moment, so that the integrity and the effectiveness of the data of the previous page area are ensured, and the failure and the discarding of the moved data caused by power failure are avoided.
It will be understood by those skilled in the art that the present invention is not limited to recording the mapping information of the previous page area when writing the current page area, but may also write data in the i+2th page area, and simultaneously record the mapping information of the data written in the i and i+1th page areas and the data source block, or other recording modes, which are not particularly limited in the present invention. For example, taking the example that the data destination block includes 4 page areas, 1, writing the 1 st page area and the 2 nd page area in turn; 2. writing a 3 rd page area, and simultaneously recording mapping information of the 1 st page area and mapping information of the 2 nd page area respectively; 3. writing a 4 th page area; 4. after writing the 4 th page area, the mapping information of the 3 rd page area and the mapping information of the 4 th page area are recorded respectively.
The optional control module is further configured to update the mapping location of the data destination block to i after writing the ith page area of the data destination block. In this embodiment, a mapping location is also introduced to characterize the location of the written data.
Assuming that the number of pages of a physical block is m, which is currently 128/256/512, the physical block can be divided into 4 page areas, and each page area can be m/4 pages. When the control module moves data under the data recovery module, the write operation sequence is as follows: 1. writing a 1 st page area; 2. writing the 2 nd page area, recording the mapping information of the 1 st page area and the data source block corresponding to the 1 st page area, and updating the mapping position of the data destination block to be 1; 3. writing the 3 rd page area, recording the mapping information of the 2 nd page area and the data source block corresponding to the 2 nd page area, and updating the mapping position of the data destination block to 2; 4. writing the 4 th page area, recording mapping information of the 3 rd page area and a data source block corresponding to the 3 rd page area, and updating the mapping position of a data destination block to 3; 5. after the 4 th page area is written, the data destination block is fully written, at this time, the mapping information of the 4 th page area and the data source block corresponding to the 4 th page area is recorded, and the mapping position of the data destination block is updated to be 4.
The optional control module is further configured to detect that the mapping location of the data destination block is updated to i after power-up, delete the data of the kth page area, and k=i+1, i+2, i+3, …. The control module can directly determine the position of the page area where the data is written according to the mapping position information of the data destination block, and can judge whether the data recovery operation is interrupted or not through the mapping position information of the data destination block after the power-on restart.
Specifically, after the power-on restart, if the control module detects that the mapping position of the data destination block is 1, the data in the 1 st page area is valid, and the later data is discarded; or if the control module detects that the mapping position of the data destination block is 2, the data of the 1 st page area and the 2 nd page area are valid, and the later data are discarded; and so on, if the control module detects that the mapping position of the data destination block is 4, the data of the whole data destination block is valid. The control module can quickly determine the writing position and the effective data according to the mapping position of the data destination block, and can reserve the effective data without discarding all the data. It should be noted that, in other embodiments, the optional control device records at least one of the mapping location and the mapping information, and any one of the mapping location and the mapping information may be used to characterize the page area or the location of the written valid data.
In other embodiments, the mapping position may be updated by taking two adjacent page areas as a unit, for example, 1, the 1 st page area and the 2 nd page area are written in sequence; 2. writing a page 3 area, and updating the mapping position to 1 at the same time; 3. the page 4 area is written out while the mapping position is updated to 2. Obviously, after power-up, firstly judging whether garbage collection is interrupted or not, and then judging according to the value of the mapping position, 1. If the stored mapping position=1, the data of the 1 st and 2 nd page areas are valid, the garbage collection is interrupted, and the later data are discarded; 2. if the saved mapping position=2, the data of the whole data destination block is valid, and garbage collection execution is completed.
Optionally, the control module is further configured to update the mapping location of the data destination block to which the data is not written to 0. And the mapping position of the data destination block in the initial state is 0, and the mapping position is updated only after the corresponding page area is written, so that the written page area can be determined according to the mapping position. The above example is exemplified by updating the mapping position in units of adjacent two page areas. If power failure occurs when writing the page1 area or the page2 area, the mapping position of the data destination block is still 0; when writing the page 3 area, the mapping position of the data destination block has been updated to 1, and even if power failure occurs, it can be determined that the data of the page1 and page2 areas are valid, and the data is discarded later.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (6)
1. A memory, comprising:
a storage module comprising a plurality of data source blocks and at least one data destination block, the data destination block comprising n page areas, each of the page areas comprising a plurality of pages;
the control module is electrically connected with the storage module and is used for controlling the data of at least one data source block to be moved to the data destination block in a data recovery mode, and recording the mapping information of the data written in the ith page area and the data source block after the writing of the ith page area of the data destination block is finished, wherein i=1, 2,3, …, n is a positive integer, and n is more than or equal to 2;
the data destination block comprises n page areas, the data of at least one data source block is correspondingly written into one page area, and the page number of each page area is equal to the page number of the effective data of the corresponding data source block; or,
the data destination block comprises n page areas, the data of the data source block is correspondingly written into at least one page area, and the total number of pages of every two adjacent page areas is equal to the number of pages of the effective data of one corresponding data source block.
2. The memory according to claim 1, wherein the control module is configured to control writing of data in an i+1th page area of the data destination block, and also record mapping information of the data written in the i-th page area and the data source block.
3. The memory of claim 1, wherein the control module is further configured to update the mapping location of the data destination block to i after the i-th page area of the data destination block is written.
4. The memory of claim 3 wherein the control module is further configured to update a mapping location of the data destination block to which no data is written to 0.
5. The memory of claim 4 wherein the control module is further configured to detect that the mapping location of the data destination block is updated to i after power-up, delete data for a kth page region, k = i +1, i +2, i +3, ….
6. The memory of claim 1, wherein the memory module is a NAND Flash.
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| CN114398008A (en) * | 2021-12-31 | 2022-04-26 | 珠海妙存科技有限公司 | Data recovery method, controller and computer-readable storage medium |
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