CN111312894A - Method for preparing bottom electrode in MRAM - Google Patents
Method for preparing bottom electrode in MRAM Download PDFInfo
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- CN111312894A CN111312894A CN202010130439.1A CN202010130439A CN111312894A CN 111312894 A CN111312894 A CN 111312894A CN 202010130439 A CN202010130439 A CN 202010130439A CN 111312894 A CN111312894 A CN 111312894A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 239000007772 electrode material Substances 0.000 claims abstract description 36
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 238000002360 preparation method Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
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- 230000008569 process Effects 0.000 abstract description 20
- 230000009467 reduction Effects 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N50/00—Galvanomagnetic devices
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- Mram Or Spin Memory Techniques (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a preparation method of a bottom electrode in MRAM. The preparation method comprises the following steps: arranging a metal wire layer on a substrate, wherein the metal wire layer comprises a plurality of metal wire parts arranged at intervals, and a first diffusion barrier layer and a dielectric layer are sequentially formed on the surface of the metal wire layer; forming a plurality of electrode through holes connected with the metal lead layer in the dielectric layer, wherein each electrode through hole is communicated with each metal lead part in a one-to-one correspondence manner, and an electrode channel is formed in each electrode through hole; and forming an alignment through hole sequentially penetrating through the dielectric layer and the first diffusion barrier layer on one side of the electrode channel so that the alignment through hole penetrates to the interval area between the adjacent metal wire parts, depositing a bottom electrode material to cover the electrode channel and the dielectric layer, partially filling the bottom electrode material in the alignment through hole to form an alignment mark, and patterning the bottom electrode material according to the alignment mark to form a bottom electrode layer. The preparation method avoids the reduction of the device performance caused by the fact that the bottom electrode layer is etched through in the subsequent etching process.
Description
Technical Field
The invention relates to the field of semiconductor process, in particular to a preparation method of a bottom electrode in MRAM.
Background
Magnetic Random Access Memory (MRAM) is a novel nonvolatile Memory, and compared with other types of current memories, the MRAM has the advantages of high read-write speed, unlimited erasing and writing, easy compatibility with the current semiconductor process, and the like, and has wide application prospects.
The main functional unit in MRAM is an MTJ cell, whose structure mainly includes a magnetic free layer/nonmagnetic oxide layer (MgO)/magnetic pinned layer. Under the drive of an external magnetic field or current and the like, the magnetic moment of the magnetic free layer is overturned, and the direction of the magnetic moment of the magnetic pinning layer is parallel or antiparallel to the direction of the magnetic moment of the magnetic pinning layer, so that the MRAM has high and low configurations which can be respectively defined as a storage state '0' and '1', and the storage of information is realized.
In the existing MRAM process, all vias (Via) and interconnects (Metal) typically use damascene structures to form copper interconnects. In order to prevent Cu diffusion and provide a relatively flat surface for MTJ film deposition, a diffusion barrier layer (Bottom Electrode) is usually added at the Bottom of MTJ as a Bottom Electrode. However, due to the light-tight bottom electrode after reaching a certain thickness and the limitation of the photolithography machine itself, the thickness of the deposited bottom electrode material needs to be limited, otherwise the bottom electrode layer with the required pattern cannot be formed by the patterning process. However, this can cause the bottom electrode to be etched through during the MTJ etch and the copper metal to be exposed, thereby affecting the final device performance.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a bottom electrode in MRAM (magnetic random access memory), which aims to solve the problem that the final performance of a device is reduced due to a preparation process of the bottom electrode in the MRAM in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for manufacturing a bottom electrode in an MRAM, including the steps of: s1, arranging a metal wire layer on the substrate, wherein the metal wire layer comprises a plurality of metal wire parts arranged at intervals, and a first diffusion barrier layer and a dielectric layer are sequentially formed on the surface of the metal wire layer; s2, forming a plurality of electrode through holes connected with the metal lead layer in the dielectric layer, wherein each electrode through hole is communicated with each metal lead part in a one-to-one correspondence manner, and an electrode channel is formed in each electrode through hole; s3, forming an etching barrier layer covering the electrode channel and the dielectric layer, forming an alignment through hole on one side of the electrode channel and sequentially penetrating the dielectric layer and the first diffusion barrier layer to enable the alignment through hole to penetrate through to the interval region between the adjacent metal wire portions, removing the etching barrier layer, depositing a bottom electrode material to cover the electrode channel and the dielectric layer, partially filling the bottom electrode material in the alignment through hole to form an alignment mark, and patterning the bottom electrode material according to the alignment mark to form a bottom electrode layer.
Further, the material of the etching barrier layer is selected from any one or more of SiN, SiC and SiCN.
Further, the etching barrier layer is removed by adopting a chemical mechanical polishing process.
Further, the depth of the alignment through hole is
Further, the material forming the first diffusion barrier layer is selected from any one or more of SiN, SiC, and SiCN.
Further, step S2 further includes the step of forming a second diffusion barrier layer on the surface of the electrode via hole before the step of forming the electrode via.
Further, the material forming the second diffusion barrier layer is selected from any one or more of Ta, TaN, Ti, and TiN.
Further, the bottom electrode material is selected from any one or more of Ta, TaN, Ti, TiN, Co and Ru.
Further, the dielectric layer is formed from a material selected from any one or more of silicon oxide, silicon dioxide, oxycarbide, fluorosilicone glass, phosphosilicate glass, borophosphosilicate glass, tetraethylorthosilicate, Low-K dielectric, and Ultra-Low-K dielectric.
Further, the material forming the electrode channel is selected from any one or more of Cu, W, and Al.
The technical scheme of the invention is applied to provide a method for preparing a bottom electrode in MRAM, in the preparation method, before a bottom electrode layer is formed, an alignment through hole penetrating through a dielectric layer and a first barrier layer is formed on one side of an electrode channel, a bottom electrode material is deposited to cover the electrode channel and the dielectric layer, the bottom electrode material is partially filled in the alignment through hole to form an alignment mark, and then the bottom electrode material is patterned according to the alignment mark to form the bottom electrode layer, so that the bottom electrode layer with a required pattern can be accurately etched in a patterning process through the alignment mark, the thickness of the bottom electrode layer is not limited, the thickness of the bottom electrode layer can be increased, and the reduction of device performance caused by the fact that the bottom electrode layer is etched through in a subsequent etching process is avoided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a substrate after a metal wiring layer is formed on a substrate and a dielectric layer is formed on the metal wiring layer in a method for fabricating a bottom electrode in an MRAM according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of the substrate after forming a plurality of electrode vias in the dielectric layer of FIG. 1, the electrode vias being connected to a metal trace layer;
FIG. 3 is a schematic cross-sectional view of the substrate shown in FIG. 2 in phantom after forming electrode vias in the respective electrode vias shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view of the substrate after forming an etch stop layer covering the electrode via and the dielectric layer shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the substrate after forming an aligned via through the dielectric layer on one side of the electrode via shown in FIG. 4;
FIG. 6 is a schematic cross-sectional view of the substrate after depositing a bottom electrode material to cover the electrode vias and dielectric layer shown in FIG. 5 to form alignment marks;
FIG. 7 is a schematic cross-sectional view of the substrate after patterning the bottom electrode material to form the bottom electrode layer according to the alignment marks shown in FIG. 6.
Wherein the figures include the following reference numerals:
1. a substrate; 10. a metal wire layer; 20. a first diffusion barrier layer; 30. a dielectric layer; 40. an electrode through hole; 50. a second diffusion barrier layer; 60. an electrode channel; 70. etching the barrier layer; 80. aligning the through holes; 90. aligning and marking; 100. and a bottom electrode layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background section, due to the limitations of the lithography machine itself, the thickness of the deposited bottom electrode material needs to be limited, otherwise the bottom electrode layer cannot be patterned by the patterning process. However, this can cause the bottom electrode to be etched through during the MTJ etch and the copper metal in the electrode via to be exposed, thereby affecting the final device performance.
In order to solve the above technical problems, the present applicant provides a method for manufacturing a bottom electrode in an MRAM, as shown in fig. 1 to 7, including the following steps: s1, disposing a metal wire layer 10 on the substrate 1, wherein the metal wire layer 10 includes a plurality of metal wire portions disposed at intervals, and sequentially forming a first barrier layer and a dielectric layer 30 on the surface of the metal wire layer 10; s2, forming a plurality of electrode through holes 40 connected to the metal lead layer 10 in the dielectric layer 30, each electrode through hole 40 communicating with each metal lead portion in one-to-one correspondence, and forming an electrode channel 60 in each electrode through hole 40; s3, forming an etching barrier layer 70 covering the electrode channel 60 and the dielectric layer 30, forming an alignment via 80 penetrating the dielectric layer 30 at one side of the electrode channel 60, so that the alignment via 80 penetrates to the space region between the adjacent metal wire portions, removing the etching barrier layer 70 and depositing a bottom electrode material to cover the electrode channel 60 and the dielectric layer 30, the bottom electrode material partially filling the alignment via 80 to form an alignment mark 90, and patterning the bottom electrode material according to the alignment mark 90 to form a bottom electrode layer 100.
In the preparation method, the alignment mark can be formed by using the bottom electrode material before the bottom electrode layer is formed, so that the bottom electrode layer with the required pattern can be accurately etched and formed in the patterning process through the alignment mark, the thickness of the bottom electrode layer is not limited, and the reduction of the device performance caused by the fact that the bottom electrode layer is etched through in the subsequent etching process can be avoided by increasing the thickness of the bottom electrode layer.
An exemplary embodiment of a method for fabricating a bottom electrode in an MRAM provided in accordance with the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: a metal wiring layer 10 is disposed on a substrate 1, the metal wiring layer 10 (including a silicon substrate and all necessary structures and devices fabricated by previous processes on the substrate, such as CMOS and inter-metal interconnect layers) includes a plurality of metal wiring portions disposed at intervals, and a first diffusion barrier layer 20 and a dielectric layer 30 are sequentially formed on the surface of the metal wiring layer 10, as shown in fig. 1.
The material forming the first diffusion barrier layer 20 described above may be selected from any one or more of SiN, SiC, and SiCN. The material forming the dielectric layer 30 may be selected from silicon oxide (SiO) and silicon dioxide (SiO)2) Any one or more of carbon oxide (CDO), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Tetraethylorthosilicate (TEOS), Low-K dielectrics, and Ultra-Low-K dielectrics.
After the above step S1, step S2 is executed: a plurality of electrode through-holes 40 connected to the metal lead layer 10 are formed in the dielectric layer 30, the electrode through-holes 40 communicate with the metal lead portions in a one-to-one correspondence, and an electrode via 60 is formed in each electrode through-hole 40, as shown in fig. 2 and 3.
The above step S2 may include the following processes: forming a plurality of electrode through holes 40 connected with the metal wire layer 10 in the dielectric layer 30 by dry etching, and sequentially forming a second diffusion barrier layer 50 and a conductive metal layer in each electrode through hole 40, wherein the electrode through holes 40 are filled with parts of the conductive metal layer; then, the conductive metal layer is chemically polished, and the conductive metal layer and the second diffusion barrier layer 50 above the dielectric layer 30 are removed, so that the dielectric layer 30 and one side layer of the conductive metal layer, which is far away from the metal wire portion, are flush, so as to form electrode channels 60 on the conductive metal layer, and each electrode channel 60 is in one-to-one correspondence with each metal wire portion. The second diffusion barrier layer 50 may be a TaN/Ta bilayer structure.
The material (i.e., the conductive metal layer) forming the electrode path 60 may be selected from a mixture of one or more of Cu, W, and Al. The material forming the second diffusion barrier layer 50 described above may be selected from any one or more of Ta, TaN, Ti, and TiN. The materials of the conductive metal layer and the second diffusion barrier layer 50 can be appropriately selected by those skilled in the art according to the prior art.
After the above step S2, step S3 is executed: forming an etching barrier layer 70 covering the electrode channel 60 and the dielectric layer 30, forming an alignment through hole 80 penetrating the dielectric layer 30 at one side of the electrode channel 60 so that the alignment through hole 80 penetrates to a spacing region between adjacent metal wire portions, removing the etching barrier layer 70 and depositing a bottom electrode material to cover the electrode channel 60 and the dielectric layer 30, partially filling the bottom electrode material in the alignment through hole 80 to form an alignment mark 90, and patterning the bottom electrode material according to the alignment mark 90 to form a bottom electrode layer 100, as shown in fig. 5 to 7.
In the step S3, a part of the bottom electrode material covers the dielectric layer 30, and the other part of the bottom electrode material is filled in the alignment through hole 80 to form the alignment mark 90, and the alignment accuracy of the pre-patterned region in the bottom electrode material can be improved by the alignment mark 90 during the photolithography process, so that the bottom electrode layer 100 with the required pattern can be obtained after the photolithography process, thereby avoiding the limitation of the photolithography process on the thickness of the layer to be etched in the prior art, further enabling the bottom electrode material deposited before patterning to have a larger thickness, and avoiding the problem that the bottom electrode material is etched through due to a smaller thickness.
The depth of the alignment mark 90 is related to the depth of the alignment through hole 80, and since the bottom electrode material covering the dielectric layer 30 is used to form the bottom electrode layer 100, the depth of the alignment mark 90 is also related to the thickness of the bottom electrode layer 100, in order to obtain the alignment mark 90 with a proper depth by depositing the bottom electrode material, so as to obtain the bottom electrode layer 100 with a larger thickness according to the alignment mark 90, preferably, the depth of the alignment through hole 80 is the same as that of the alignment through hole 80
In step S3, the bottom electrode material may be selected from one or more of Ta, TaN, Ti, TiN, Co and Ru, and those skilled in the art can select the above bottom electrode material according to the prior art.
Before the step of forming the alignment via 80, the step S3 further includes the step of forming an etch stopper 70 covering the electrode via 60 and the dielectric layer 30, as shown in fig. 4; also, step S3 further includes a step of removing the etch stopper 70 after the step of forming the alignment via 80 and before the step of depositing the bottom electrode material. The etch stopper 70 prevents an etching process from affecting the electrode via 60 during the formation of the alignment via 80.
In the above preferred embodiment, the material of the etching barrier layer 70 may be selected from any one or more of SiN, SiC and SiCN, and those skilled in the art can reasonably select the material of the etching barrier layer 70 according to the prior art. And, more preferably, the etch stopper 70 is removed using a chemical mechanical polishing process.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
according to the preparation method, the alignment mark is formed by using the bottom electrode material before the bottom electrode layer is formed, so that the bottom electrode layer with the required pattern can be etched and formed more accurately in the patterning process through the alignment mark, meanwhile, the thickness of the bottom electrode layer is not limited, the thickness of the bottom electrode layer can be increased, and the reduction of the device performance caused by the fact that the bottom electrode layer is etched through in the subsequent etching process is avoided.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for fabricating a bottom electrode in an MRAM, the method comprising:
s1, arranging a metal wire layer (10) on a substrate (1), wherein the metal wire layer (10) comprises a plurality of metal wire parts arranged at intervals, and a first diffusion barrier layer (20) and a dielectric layer (30) are sequentially formed on the surface of the metal wire layer (10);
s2, forming a plurality of electrode through holes (40) connected with the metal lead layer (10) in the dielectric layer (30), wherein each electrode through hole (40) is communicated with each metal lead part in a one-to-one correspondence manner, and an electrode channel (60) is formed in each electrode through hole (40);
s3, forming an etching barrier layer (70) covering the electrode channel (60) and the dielectric layer (30), forming an alignment through hole (80) sequentially penetrating through the dielectric layer (30) and the first diffusion barrier layer (20) on one side of the electrode channel (60) so that the alignment through hole (80) penetrates to a spacing area between adjacent metal wire portions, removing the etching barrier layer (70) and depositing a bottom electrode material to cover the electrode channel (60) and the dielectric layer (30), wherein the bottom electrode material is partially filled in the alignment through hole (80) to form an alignment mark (90), and patterning the bottom electrode material according to the alignment mark (90) to form a bottom electrode layer (100).
2. A production method according to claim 1, characterized in that the material of the etch barrier layer (70) is selected from any one or more of SiN, SiC and SiCN.
3. Preparation method according to claim 1, characterized in that the etch stop layer (70) is removed using a chemical mechanical polishing process.
4. The method of claim 1, wherein the depth of the alignment via (80) is
5. A production method according to any one of claims 1 to 4, characterized in that the material forming the first diffusion barrier layer (20) is selected from any one or more of SiN, SiC and SiCN.
6. The production method according to any one of claims 1 to 4, characterized in that, prior to the step of forming the electrode via (60), the step S2 further includes a step of forming a second diffusion barrier layer (50) on the surface of the electrode via (40).
7. A production method according to claim 6, characterized in that the material forming the second diffusion barrier layer (50) is selected from any one or more of Ta, TaN, Ti and TiN.
8. A method of manufacturing as claimed in any one of claims 1 to 4, wherein the bottom electrode material is selected from any one or more of Ta, TaN, Ti, TiN, Co and Ru.
9. The production method according to any one of claims 1 to 4, wherein a material forming the dielectric layer (30) is selected from any one or more of silicon oxide, silicon dioxide, oxycarbide, fluorosilicone glass, phosphosilicate glass, borophosphosilicate glass, tetraethoxysilane, Low-K dielectric, and Ultra-Low-K dielectric.
10. The production method according to any one of claims 1 to 4, wherein a material forming the electrode channel (60) is selected from any one or more of Cu, W, and Al.
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| CN202010130439.1A CN111312894A (en) | 2020-02-28 | 2020-02-28 | Method for preparing bottom electrode in MRAM |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364569A (en) * | 2007-08-07 | 2009-02-11 | 株式会社瑞萨科技 | Method for manufacturing a magnetic memory device and magnetic memory device |
| CN105336850A (en) * | 2014-06-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Alignment method of MRAM device formation process |
| US20160093670A1 (en) * | 2014-09-25 | 2016-03-31 | Globalfoundries Singapore Pte. Ltd. | Magnetic tunnel junction stack alignment scheme |
| CN108232008A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of magnetic RAM hearth electrode contact and preparation method thereof |
| US20180233661A1 (en) * | 2017-02-15 | 2018-08-16 | Globalfoundries Singapore Pte. Ltd. | Device alignment mark using a planarization process |
-
2020
- 2020-02-28 CN CN202010130439.1A patent/CN111312894A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364569A (en) * | 2007-08-07 | 2009-02-11 | 株式会社瑞萨科技 | Method for manufacturing a magnetic memory device and magnetic memory device |
| CN105336850A (en) * | 2014-06-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Alignment method of MRAM device formation process |
| US20160093670A1 (en) * | 2014-09-25 | 2016-03-31 | Globalfoundries Singapore Pte. Ltd. | Magnetic tunnel junction stack alignment scheme |
| CN108232008A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of magnetic RAM hearth electrode contact and preparation method thereof |
| US20180233661A1 (en) * | 2017-02-15 | 2018-08-16 | Globalfoundries Singapore Pte. Ltd. | Device alignment mark using a planarization process |
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