CN111312664A

CN111312664A - Substrate structure for bearing semiconductor component, semiconductor wafer and wafer manufacturing method

Info

Publication number: CN111312664A
Application number: CN202010404609.0A
Authority: CN
Inventors: 杨国江; 张胜凯; 于世珩
Original assignee: Jiangsu Changjing Technology Co ltd
Current assignee: Jiangsu Changjing Technology Co.,Ltd.
Priority date: 2020-05-14
Filing date: 2020-05-14
Publication date: 2020-06-19
Anticipated expiration: 2040-05-14
Also published as: CN111312664B

Abstract

The present application provides a substrate structure for carrying a semiconductor device, comprising: a wafer layer having a first surface and a second surface corresponding to the first surface, wherein the second surface has a central recess region recessed toward the first surface, the central recess region being located in the second surface such that a frame structure region of the wafer layer surrounds the second surface; and a metal layer having a third surface and a fourth surface corresponding to each other, wherein the third surface is completely attached to the second surface.

Description

Substrate structure for bearing semiconductor component, semiconductor wafer and wafer manufacturing method

Technical Field

The present application relates generally to semiconductor devices, and more particularly to the design and fabrication of wafer level chip package substrate structures.

Background

Modern electronic devices are becoming thinner and smaller, and the size of integrated circuits is also becoming smaller. Compared with the traditional chip, the thinned chip can bear smaller physical stress and thermal stress. During heat treatment and other processing, particularly when the chip is attached to the printed circuit board, the physical and thermal stresses are likely to cause cracks and/or warpage of the substrate, which may lead to failure of the semiconductor device.

In addition, when the chip is thinned, the conductive lines may become smaller and narrower, so that the resistance increases. This is not favorable for reducing power consumption, and also results in a rapid temperature rise. When the heat dissipation efficiency cannot cope with the temperature rise speed, an additional heat dissipation assembly may be required, and the advantage of thinning the chip is lost.

Accordingly, a substrate structure with high strength is needed to reduce the probability of failure caused by stress or thermal stress when the chip is subjected to heat treatment, processing, and bonding. Meanwhile, the resistance of the substrate structure is also reduced, so that the power consumption is reduced, the thermal loss is reduced, and the service life of the chip is prolonged.

Disclosure of Invention

The substrate structure and the substrate structure for wafer level chip packaging have the thin wafer layer in the center of the chip, and the overall resistance value of the substrate structure can be reduced. The peripheral part of the chip is provided with a frame structure, and the central part of the chip can be provided with one or multiple inner frame structures to make up for the structural strength of the thinner wafer layer. The application also provides a semiconductor wafer with the substrate structure and a wafer manufacturing method for manufacturing the substrate structure.

According to the scheme of the application, a substrate structure with a frame structure, a semiconductor wafer and a wafer manufacturing method are provided.

According to an aspect of the present application, there is provided a substrate structure for supporting a semiconductor device, comprising: a wafer layer having a first surface and a second surface corresponding to the first surface, wherein the second surface has a central recess region recessed toward the first surface, the central recess region being located in the second surface such that a frame structure region of the wafer layer surrounds the second surface; and a metal layer having a third surface and a fourth surface corresponding to each other, wherein the third surface is completely attached to the second surface.

Furthermore, in order to compensate for the structural strength of the thinner wafer layer, the second surface further includes a first annular recessed area recessed toward the first surface, and the first annular recessed area and the central recessed area are located in the second surface, so that the wafer layer forms an annular first inner frame structure area between the first annular recessed area and the central recessed area.

Furthermore, in order to further compensate for the structural strength of the thinner wafer layer, the second surface further has a second annular recessed area recessed toward the first surface, the second annular recessed area is located in the second surface, so that the wafer layer forms an annular second inner frame structure area between the second annular recessed area and the central recessed area, the first annular recessed area completely includes the annular first inner frame structure area, the first inner frame structure area completely surrounds the second annular recessed area, and the second annular recessed area completely surrounds the second inner frame structure area.

Further, in order to protect the metal layer and reduce the influence of physical stress and thermal stress, the substrate structure further comprises: and the resin layer is provided with a fifth surface and a sixth surface which correspond to each other, wherein the shape of the fifth surface corresponds to that of the fourth surface.

Furthermore, in order to simplify the design of the semiconductor device carried by the substrate structure, the frame structure region sequentially includes a first side structure region, a second side structure region, a third side structure region and a fourth side structure region, and the first side structure region and the third side structure region have the same width.

Furthermore, in order to simplify the design of the semiconductor device carried by the substrate structure, the widths of the first side structure region, the second side structure region, the third side structure region and the fourth side structure region are the same.

Furthermore, in order to adapt the substrate structure to different designs of the semiconductor device, the frame structure region sequentially includes a first side structure region, a second side structure region, a third side structure region and a fourth side structure region, and the first side structure region and the third side structure region have different widths.

Furthermore, in order to adapt the substrate structure to the semiconductor device having a larger design flexibility, the widths of the first side structure region, the second side structure region, the third side structure region and the fourth side structure region are different.

Further, to fit the shape of most rectangular chips, the central recessed area is rectangular.

Further, to fit the shape of most square chips, the central recessed area is square.

Further, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the recessed region.

Further, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the first annular recessed region or the central recessed region.

Further, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to a distance between the first surface and the second surface of the first inner frame structure region.

Further, in order to save the thickness of the metal layer and thus save the cost, the fourth surface has a metal layer recessed region recessed toward the third surface, and a projection region of the metal layer recessed region on the second surface is located in the central recessed region.

Further, for design and manufacturing convenience, the metal layer recessed region corresponds to the recessed region in shape, and the area of the metal layer recessed region is smaller than that of the central recessed region.

According to an aspect of the present application, a semiconductor wafer is provided, wherein a first chip region is to be cut out of the semiconductor wafer, the first chip region comprising a substrate structure of a semiconductor device as described above.

Furthermore, in order to make different chips by using the area of the wafer as much as possible, a second chip region is pre-cut from the semiconductor wafer, which includes the same substrate structure as the first chip region, and the first chip region and the second chip region have different shapes.

Further, in order to speed up the chip fabrication with the substrate structure using the wafer level chip fabrication technology, a plurality of chip regions are pre-cut from the semiconductor wafer, each of the plurality of chip regions includes the same substrate structure as the first chip region, and each of the plurality of chip regions and the first chip region have the same shape.

According to an aspect of the present invention, there is provided a method for manufacturing a wafer, comprising: coating a shielding layer on a second surface of a wafer layer according to the sizes and patterns of a plurality of chip areas to be cut, wherein a first chip area in the plurality of chip areas comprises a central depressed area uncovered by the shielding layer and a frame structure area covered by the shielding layer, the central depressed area is positioned in the frame structure area, and the frame structure area surrounds the second surface; etching the wafer layer in the central depression region; removing the shielding layer; and fabricating a metal layer on the second surface.

Furthermore, in order to compensate for the structural strength of the thinner wafer layer, the first chip region further includes a first annular recessed region uncovered by the shielding layer and a first inner frame structure region covered by the shielding layer, the first annular recessed region surrounds the first inner frame structure region, the central recessed region is located in the first inner frame structure region, and the first annular recessed region is located in the frame structure region.

Further, in order to further compensate for the structural strength of the thinner wafer layer, the first chip region further includes a second annular recessed region uncovered by the shielding layer and a second inner frame structure region covered by the shielding layer, the first inner frame structure region completely surrounds the second annular recessed region, the second annular recessed region surrounds the second inner frame structure region, and the second inner frame structure region surrounds the central recessed region.

Further, in order to protect the metal layer and reduce the influence of physical stress and thermal stress, the wafer manufacturing method further comprises: a resin layer is coated on the metal layer.

Further, in order to speed up the chip fabrication with the substrate structure using wafer level chip fabrication techniques, the above steps are performed simultaneously for the plurality of chip regions of the wafer layer.

Further, in order to speed up the chip fabrication with the substrate structure by using the wafer level chip fabrication technology, the wafer fabrication method further includes: dicing of the plurality of chip regions is performed.

Further, in order to speed up the chip fabrication with the substrate structure by using the wafer level chip fabrication technology, the wafer fabrication method further includes: after the step of coating the resin layer, cutting of the plurality of chip regions is performed.

Further, in order to reduce the resistance of the substrate region, wherein the wafer layer includes a first surface corresponding to the second surface, after the etching step is performed, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the central recessed region.

Furthermore, in order to reduce the resistance of the substrate region, after a portion of the etching step is performed, the shielding layer is covered on the first inner frame structure region, so that the distance from the first surface to the second surface of the frame structure region is greater than or equal to the distance from the first surface to the second surface of the first inner frame structure region.

Furthermore, in order to reduce the resistance of the substrate region, after a portion of the etching step is performed, the shielding layer is covered on the second inner frame structure region, such that the distance from the first surface to the second surface of the frame structure region is greater than or equal to the distance from the first surface to the second surface of the second inner frame structure region.

Furthermore, in order to fabricate different chips by using the area of the wafer as much as possible, the plurality of chip regions include a second chip region, and the first chip region and the second chip region have different shapes.

Further, in order to speed up the chip fabrication with the substrate structure using the wafer level chip fabrication technique, each of the plurality of chip regions and the first chip region have the same shape.

Furthermore, in order to save the thickness of the metal layer and thus save the cost, the metal layer has a third surface and a fourth surface corresponding to each other, the third surface completely fits the second surface, wherein the fourth surface has a metal layer recessed region recessed toward the third surface, and a projection region of the metal layer recessed region on the second surface is located in the central recessed region.

Further, for design and manufacturing convenience, the metal layer recessed region corresponds to the central recessed region in shape, and the area of the metal layer recessed region is smaller than that of the central recessed region.

In summary, the present application provides a chip having a substrate structure with a large strength, which has a frame structure of a wafer layer and also has an inner frame structure of the wafer layer, so as to reduce the probability of failure caused by stress or thermal stress when the chip is subjected to processes such as heat treatment, processing and bonding. Meanwhile, the resistance of the substrate structure is also reduced, so that the power consumption is reduced, the thermal loss is reduced, and the service life of the chip is prolonged.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor substrate structure.

Fig. 2 is another cross-sectional view of a conventional semiconductor substrate.

Fig. 3 is a schematic cross-sectional view illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 4 is a schematic cross-sectional view illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 5A and 5B are schematic cross-sectional views illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a cross-section of a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a cross-section of a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 8A is a schematic cross-sectional view illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 8B is a cross-sectional view of a semiconductor substrate according to an embodiment of the present application.

Fig. 9 is a schematic cross-sectional view illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 10A and 10B are schematic cross-sectional views illustrating a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 11A is a schematic view of a cross-section of a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 11B is a schematic diagram of a cross-section of a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 12 is a schematic view of a cross section of a structure of a semiconductor substrate according to an embodiment of the present application.

Fig. 13 is a schematic view of a wafer according to an embodiment of the present application.

Fig. 14 is a schematic view of a wafer according to another embodiment of the present application.

FIG. 15 is a flowchart illustrating a method of fabricating a wafer according to an embodiment of the present application.

FIGS. 16A-16J are cross-sectional views of various stages of a wafer fabrication process according to an embodiment of the present disclosure.

Detailed Description

The present invention will be described in detail with reference to some examples. However, the scope of the present invention is not limited by the embodiments other than those disclosed, and is subject to the claims below. In order to provide a clear description and to enable one of ordinary skill in the art to understand the present invention, the various portions of the drawings are not drawn to relative sizes, some sizes or other relative scale may be exaggerated, and irrelevant details are not fully drawn for clarity of illustration.

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor substrate structure 100. The structure 100 sequentially includes a metal layer 110, a wafer layer 120, and a semiconductor device layer 130. A wafer layer 120 is sandwiched between the metal layer 110 and a semiconductor device layer 130. In fig. 1, the semiconductor device layer 130 may include a vertical semiconductor device, such as at least one metal-oxide-semiconductor field-effect transistor (MOSFET).

In the design of the semiconductor component, a part of the current flows from one part of the semiconductor component to the metal layer 110 through the wafer layer 120, and then flows from the metal layer 110 to the other part of the semiconductor component through the wafer layer 120, as indicated by a dotted arrow. For example, the current path may be from the drain to the source of a mosfet. The total resistance of the current paths includes the resistance of the wafer layer 120 and the resistance of the metal layer 110 after two passes. In vertical field effect transistors below 30 volts, the resistance of the wafer layer 120 is between thirty percent and fifty percent of the total resistance.

Fig. 2 is another cross-sectional view of a conventional semiconductor substrate structure 200. The semiconductor device layer of the structure 200 comprises at least two vertically configured semiconductor devices, such as a first N-type mosfet 231 and a second N-type mosfet 232. The two NFETs 231 and 232 may have a common source. A current path may be established between the two devices, for example, from the first nmos 231 to the second nmos 232. The total resistance of the current paths includes the resistance of the wafer layer 120 and the resistance of the metal layer 110 after two passes. In the vertical field effect transistor with a voltage lower than 30 v, the resistance of the wafer layer 120 accounts for 30% to 50% of the total resistance.

If the resistance of the wafer layer 120 can be reduced, the total resistance of the current paths of fig. 1 and 2 can be reduced. The improvement can reduce power consumption, reduce heat loss and prolong the service life of the chip. In order to reduce the resistance of the wafer layer 120, the thickness of the wafer layer 120 may be reduced. However, as mentioned above, after reducing the thickness of the wafer layer 120, a sufficient structural strength can be maintained to resist damage caused by stress and/or thermal stress. One of the solutions proposed in this application is to have a thicker wafer layer at least at the edges of the chips, but to reduce the wafer thickness where there are semiconductor components in the middle of the chips. Thus, the resistance of the wafer layer 120 can be reduced while maintaining a sufficient structural strength.

Fig. 3 is a schematic cross-sectional view of a semiconductor substrate structure 300 according to an embodiment of the present application. The structure 300 sequentially includes a semiconductor device layer 130, a wafer layer 320, and a metal layer 310. The wafer layer 320 is sandwiched between the metal layer 310 and the semiconductor device layer 130.

The semiconductor device layer 130, which has been mentioned in the description of fig. 1 and 2, may comprise one or more semiconductor devices. The semiconductor devices may comprise vertical transistors, in particular mosfets. In one embodiment, the thickness of the semiconductor device layer 130 may be between 2-4 um. However, it will be understood by those skilled in the art that the semiconductor device layer 130 may comprise one or more semiconductor devices, and the thickness, number of layers and other parameters of the semiconductor device layer 130 are not limited herein. As long as the semiconductor devices included in the semiconductor device layer 130 need to pass current through the wafer layer 320 and the metal layer 310, the present application is applicable.

The wafer layer 320 includes a first surface 321 and a second surface 322 opposite to each other, and the first surface 321 is connected to the semiconductor device layer 130. The second surface 322 is connected to or attached to the metal layer 310. As can be seen in fig. 3, the maximum distance between the first surface 321 and the second surface 322 occurs at the edge of the structure 300. In one embodiment, the minimum distance between the first surface 321 and the second surface 322 occurs at the center of the structure 300. In another embodiment, the minimum distance between the first surface 321 and the second surface 322 occurs where the devices of the semiconductor device layer 130 project onto the first surface 321.

In one embodiment, when the structure 300 is a thinned chip, the maximum distance between the first surface 321 and the second surface 322, or the thickness of the wafer layer 320, may be less than 75 um. In another embodiment, the maximum distance between the first surface 321 and the second surface 322, or the thickness of the wafer layer 320, may be between 100-150 um. In additional embodiments, the maximum distance between the first surface 321 and the second surface 322, or the thickness of the wafer layer 320, may be between 75-125 um. However, it will be understood by those skilled in the art that the thickness of the wafer layer 320 is not limited in this application.

The minimum distance between the first surface 321 and the second surface 322 of the wafer layer 320 may be half of the maximum distance, compared to the conventional wafer layer 120. In other words, the resistance of the wafer layer 320 is about half of the resistance of the wafer layer 120. In other embodiments, the ratio of the minimum distance to the maximum distance between the first surface 321 and the second surface 322 may be other ratios less than 100%.

In this manner, there is a thicker wafer layer 320 at the edges of the chip, but the thickness of the wafer is reduced where there are semiconductor components in the middle of the chip. In addition, the resistance value in the middle of the wafer layer 320 can be reduced, and meanwhile, the structural strength of a chip can be maintained, and the device failure in the process can be reduced.

In one embodiment, the wafer layer 320 with thicker chip edge has a width between about 50um and 200 um. It will be appreciated by those skilled in the art that the above-mentioned widths may be adjusted according to the semiconductor device implemented by the chip, and the environment and specifications to which the chip is applied.

The metal layer 310 may include a third surface 313 and a fourth surface 314 opposite to each other, wherein the third surface 313 and the second surface 322 of the wafer layer 320 are connected or attached to each other. Therefore, the second surface 322 and the third surface 313 have shapes corresponding to each other.

The metal layer 310 may comprise one or more metal layers, and the metal layer 310 may comprise a single metal, alloy or metal compound. For example, the metal layer 310 may include titanium-nickel-silver-nickel alloy (TiNiAgNi), nickel-aluminum alloy (AlNi), aluminum-copper-cobalt alloy (alcuini), titanium-copper-nickel alloy (ticoni), titanium alloy, vanadium-nickel alloy, silver alloy, nickel alloy, copper alloy, pure cobalt, and alloys containing various metals such as aluminum, titanium, nickel, silver, nickel, and copper. It will be appreciated by those skilled in the art that the composition and thickness of the metal layer 310 may be adjusted according to the manufacturing process of the chip, the cost, and the environment and specification of the chip. In one embodiment, the thickness of the third surface 313 and the fourth surface 314 is between 25-50 um. In another embodiment, both are between 6-30 um. As shown in fig. 3, the maximum distance between the third surface 313 and the fourth surface 314 occurs in the middle of the chip, i.e., the component of the semiconductor device layer 130 is projected to correspond to the first surface 321. In this way, the thickness of the metal layer 310 in the middle of the chip is increased, and the resistance value of the metal layer 310 can be reduced, thereby further reducing the total resistance value of the current path of the semiconductor device. So as to reduce power consumption, reduce thermal loss and prolong the service life of the chip.

Fig. 4 is a schematic cross-sectional view of a semiconductor substrate structure 400 according to an embodiment of the present application. The description of the embodiment shown in fig. 3 may be applied to the components included in the structure 400 shown in fig. 4, if the same reference numerals are used for the components included in the structure 300 shown in fig. 3.

In comparison to the structure 300 shown in fig. 3, the structure 400 of fig. 4 further includes an epoxy resin (epoxy resin) layer or resin layer 440. Epoxy resins, also known as artificial resins, resin glues, are known for their structural epoxy groups. It will be understood by those of ordinary skill in the art of semiconductor fabrication that the present application is not limited to any particular epoxy resin. The resin layer 440 may be used to protect the metal layer 310 of the structure 400 and reduce the influence of physical stress and thermal stress, thereby protecting the device.

The resin layer 440 includes a fifth surface 445 and a sixth surface 446 opposite to each other, and the fifth surface 445 and the fourth surface 314 of the metal layer 310 are connected or attached to each other. Therefore, the fifth surface 445 and the fourth surface 314 have shapes corresponding to each other. In one embodiment, the distance between the fifth surface 445 and the sixth surface 446 of the resin layer 440 may be between 50-200 um.

In the embodiments of fig. 3 and 4, the metal layer 310 in the middle of the chip is thicker. Since the metal price of the metal layer 310 is more expensive than the resin of the resin layer 440, the step of fabricating the metal layer 310 thicker is also more expensive than the step of fabricating the resin layer 440. If design specifications permit, a thinner metal layer 310 may be made to reduce cost.

Fig. 5A is a schematic cross-sectional view of a semiconductor substrate structure 500 according to an embodiment of the present application. In contrast to the structure 400 shown in fig. 4, the structure 500 comprises, in order, a semiconductor device layer 130, a wafer layer 320, a metal layer 510, and a resin layer 540. The description of the embodiment shown in fig. 4 may be applied to the components included in the structure 500 shown in fig. 5A, if the symbols are the same as those included in the structure 400 shown in fig. 4.

In contrast to the structure 400 shown in fig. 4, the fourth surface 514 of the metal layer 510 included in the structure 500 is not planar as the fourth surface 314 of the metal layer 310 included in the structure 400. The cross-section of the fourth surface 514 corresponds to the cross-section of the third surface 513 of the metal layer. The shortest distance between the fourth surface 514 of the metal layer 510 and the first surface 321 of the wafer layer 320 is smaller than the shortest distance between the fourth surface 314 of the metal layer 310 and the first surface 321 of the wafer layer 320. Since most of the metal layer 510 of the structure 500 is thinner than most of the metal layer 310 of the structure 400, the cost of the metal itself and the cost of the steps for fabricating the metal layer 510 can be saved.

Fig. 5B is a schematic cross-sectional view illustrating a structure 500 of a semiconductor substrate according to an embodiment of the present application. The embodiment shown in fig. 5B is a variation of the embodiment shown in fig. 5A. The metal layer 510 of the embodiment shown in fig. 5B is thicker than the metal layer 510 of fig. 5A. The remaining features of the embodiment of fig. 5B are the same as those of the embodiment of fig. 5A.

Fig. 6 is a schematic diagram illustrating a cross-section 600 of a semiconductor substrate according to an embodiment of the present application. The cross-section 600 of the structure may be the AA-line cross-section of the structure 300 shown in fig. 3, the AA-line cross-section of the structure 400 shown in fig. 4, or the BB-line cross-section of the structure 500 shown in fig. 5B. For convenience of explanation, the embodiment shown in fig. 6 is the structure 300 shown in fig. 3, and therefore the symbols of the metal layer 310 and the wafer layer 320 are used. One of ordinary skill in the art will appreciate that profile 600 may be adapted for use with

structures

400 or 500 and metal layer 310 may be replaced with metal layer 510.

At the periphery of the cross-section 600 shown in fig. 6 is the wafer layer 320. The chip formed by the structure 300 may be rectangular or square. In the middle of the wafer layer 320 is the metal layer 310. The up-down axial length 611 and the left-right axial length 612 of the metal layer 310 may be the same or different. When the two are the same, the cross-section of the metal layer 310 is square.

Between the cross section of the metal layer 310 and the outer edge of the wafer layer 320, there are four frames of the wafer layer 320 surrounding the metal layer 310. The thicknesses of the four frames can be the same or different. For example, the

thicknesses

621 and 623 for the upper and lower outer edges may be the same, and the

thicknesses

622 and 624 for the left and right outer edges may be the same. But

thicknesses

621 and 622 may be different.

As can be appreciated by those skilled in the art with reference to fig. 6, the present application is not limited to the shape of the outer edge of the wafer layer 320. In other words, the present application does not limit the shape of the chip. The shape of the metal layer 310 is not limited in this application. In addition, when the wafer layer 320 and the metal layer 310 are rectangular, the thickness of the four frames of the wafer layer 320 surrounding the metal layer 310 is not limited in the present application. In one embodiment, the thicknesses 621-624 of the four frames can be the same, so as to simplify the design and manufacturing problems. In another embodiment, the thicknesses of the two groups of the four frames can be the same, so as to simplify the design and manufacturing problems. In a further embodiment, the thicknesses 621-624 of the four frames can be different to suit the chip design.

Fig. 7 is a schematic diagram illustrating a cross-section 700 of a semiconductor substrate structure according to an embodiment of the present application. The cross-section 700 of the structure may be the BB-line cross-section of the structure 500 shown in fig. 5A.

Between the resin layer 540 and the outer edge of the metal layer 510 are four metal frames of the metal layer 510 surrounding the resin layer 540. The thicknesses of the four metal frames can be the same or different. For example, the

thicknesses

711 and 713 may be the same for the upper and lower outer edges, and the

thicknesses

712 and 714 may be the same for the left and right outer edges. But

thicknesses

711 and 712 may be different.

As can be understood by those skilled in the art from fig. 7, the present application does not limit the shape of the outer edge of the resin layer 540, and the outer edge may be square, rectangular, oval, or circular. When the metal layer 510 and the resin layer 540 are rectangular, the application also does not limit the thickness of the four frames of the metal layer 510 surrounding the resin layer 540. In one embodiment, the thicknesses 711-714 of the four frames can be the same, so as to simplify the design and manufacturing problems. In another embodiment, the thicknesses of the two groups of the four frames can be the same, so as to simplify the design and manufacturing problems. In a further embodiment, the thicknesses 711-714 of the four frames may be completely different to suit the chip design.

Different areas of the chip can bear different semiconductor components, and the resistance values of the substrate structures required by the different semiconductor components can be different. Therefore, as shown in the embodiment of fig. 7, the thickness of the metal layer 510 may be made thicker in some regions, and the metal of some metal layers 510 may be replaced by thicker resin layers 540 in other regions, so as to adapt to the substrate structure resistance values required by different semiconductor components. In terms of production, although the depth, shape and position of the resin layer 540 vary, the same process is used to produce the resin layer 540, and therefore the cost is only related to the amount of metal used.

Fig. 8A is a schematic cross-sectional view of a structure 800 of a semiconductor substrate according to an embodiment of the present application. The structure 800, in turn, includes a semiconductor device layer 130, a wafer layer 820, and a metal layer 810. In contrast to the structure 300 shown in fig. 3, there is a reinforcing inner frame structure in the center of the wafer layer 820 in addition to the frame at the outer edge of the wafer layer 820. In fig. 8A, two

inner frame structures

821 and 822 can be seen.

It will be appreciated by those skilled in the art that the inner frame structure may improve the structural strength of the wafer layer 820. It should be noted that the resistance of the substrate structure to which the semiconductor device is arranged above the frame structure is higher than the resistance of other regions. Therefore, it is possible to eliminate as much as possible the arrangement of semiconductor components requiring a lower resistance value of the substrate structure above these inner frame structures.

Although in the embodiment shown in fig. 8A, only two

inner frame structures

821 and 822 are shown, and the distances of the

inner frame structures

821 and 822 with respect to the bezel are the same. However, the present application does not limit the number, position, shape, and other parameters of the inner frame structure.

Fig. 8B is a schematic cross-sectional view of a structure 800 of a semiconductor substrate according to an embodiment of the present application. In the embodiment shown in fig. 8B, four inner frame structures are shown. As can be understood from fig. 8A and 8B, the present application does not limit the number, position, shape, and other parameters of the inner frame structure.

In one embodiment, as shown in FIG. 8A, the thickness of the wafer layer 820 is the same as that of the frame structure at the locations of the

frame structures

821 and 822. In another embodiment, the thickness of the

inner frame structures

821 and 822 can be different from the thickness of the bezel structures. For example, the thickness of the wafer layers in the

frame structures

821 and 822 can be smaller than the thickness of the wafer layers in the frame structures. Since the stresses and/or thermal stresses experienced in the middle of the chip can be less than at the edges, a thinner inner frame structure can be used for reinforcement. On one hand, the resistance value of the substrate structure is reduced, and on the other hand, the substrate structure can be reinforced.

Fig. 9 is a schematic cross-sectional view of a semiconductor substrate structure 900 according to an embodiment of the present application. The structure 900 shown in fig. 9 incorporates a resin layer 440 beneath the structure 800 shown in fig. 8. As with the structure 400 shown in fig. 4, the resin layer 440 may be used to protect the metal layer 810 of the structure 900 and reduce the effects of physical and thermal stresses, thereby protecting the device.

In the embodiments of fig. 8A and 9, the metal layer 810 in the middle of the chip is thicker. Since the metal price of the metal layer 810 is more expensive than the resin of the resin layer 440, the step of fabricating the metal layer 810 thicker is also more expensive than the step of fabricating the resin layer 440. If design specifications allow, a thinner metal layer 810 may be made to reduce cost.

Fig. 10A is a schematic cross-sectional view of a structure 1000 of a semiconductor substrate according to an embodiment of the present application. The difference from the embodiment shown in fig. 9 is that the structure 1000 includes a metal layer 1010 and a resin layer 1040. To thin the metal layer 810 between the bezel structure and the inner frame structure, a thicker resin layer 1040 may be used in place of the metal layer 1010 in the areas described above.

Compared to the structure 900 shown in fig. 9, the shortest distance between the fourth surface 1014 of the metal layer 1010 and the first surface 821 of the wafer layer 820 is smaller than the shortest distance between the fourth surface of the metal layer 810 and the first surface of the wafer layer 820. Since most of the metal layer 1010 of the structure 1000 is thinner than most of the metal layer 810 of the structure 900, the cost of the metal itself can be saved, and the cost of the step of manufacturing the metal layer 810 can also be saved.

Fig. 10B is a schematic cross-sectional view of a structure 1000 of a semiconductor substrate according to an embodiment of the present application. The embodiment shown in fig. 10B is a variation of the embodiment shown in fig. 10A. The metal layer 1010 of the embodiment shown in FIG. 10B is thicker than the metal layer 1010 of FIG. 10A. The remaining features of the embodiment of fig. 10B are the same as those of the embodiment of fig. 10A.

Fig. 11A is a schematic diagram illustrating a cross-section 1100 of a semiconductor substrate structure according to an embodiment of the present application. The cross-section 1100 of this structure may be the CC-line cross-section of the structure 800 shown in fig. 8A, the CC-line cross-section of the structure 900 shown in fig. 9, or the DD-line cross-section of the structure 1000 shown in fig. 10B. For convenience of explanation, the embodiment shown in fig. 11A is the structure 800 shown in fig. 8A, and therefore the symbols of the metal layer 810 and the wafer layer 820 are used. It will be understood by those skilled in the art that profile 1100 may be adapted for use with either

structure

900 or 1000, and metal layer 810 may be replaced with metal layer 1010.

As mentioned previously, the present application does not limit the shape of the inner frame structure. For example, the inner frame structure may be an X-shape, a V-shape, or a cross-shape, that is, two sets of parallel lines perpendicular to each other. In the embodiment shown in fig. 11A, the outer edge of the wafer layer 820 is square in shape and is shown in white. The four rims 820A of the wafer layer 820 have equal widths. Inside the metal layer 810A, there is also an inner frame structure 820B of the wafer layer. The inner frame structure 820B has a metal layer 810B therein.

The frame structure 820A and the inner frame structure 820B of the wafer layer 820 shown in fig. 11A are concentric and have corresponding shapes. Since the chip is designed such that the central area has the geometric property of being equidistant from the four sides, it is usually the best choice for placing logic circuits. In the peripheral area, the associated analog circuitry is typically placed and accessed. In such a circuit design, the entire chip may be scrapped due to the failure of the logic circuit. The analog circuitry is typically relatively thick and may be subject to the same degree of damage without failing. The inner frame structure 820B can be used to reinforce the structural strength of the central area of the logic circuit, so as to increase the strength of the chip.

Furthermore, although in the embodiment shown in FIG. 11A, there is only one inner frame structure 820B. It will be appreciated by those skilled in the art that multiple inner frame structures, such as a zigzag-shaped inner frame structure, may be utilized to enhance structural strength. The shape of the Chinese character hui is that the inner frame is also provided with an inner frame.

In one embodiment, multiple inner frame structures may be concentric to simplify the design. In another embodiment, the width of the frames of the multiple inner frame structure is the same. In a further embodiment, the shape of the large inner frame structure and the small inner frame structure may be corresponding. For example, the large inner frame structure and the small inner frame structure may be the same shape, but different sizes. The width of the frame may be proportional to the size of the inner frame structure. In one embodiment, there may be more than two multiple inner frame structures.

Fig. 11B is a schematic diagram illustrating a cross-section 1100 of a semiconductor substrate structure according to an embodiment of the present application. The embodiment shown in fig. 11B is a zigzag inner frame structure, which is a multiple inner frame structure having an inner frame inside.

The technical features to be protected in the present application are that at least one or multiple inner frame structures are provided inside the frame structure of the wafer layer for reinforcing the structure inside the one or multiple inner frame structures, and the number of the inner frame structures is not limited in the present application.

Please refer to fig. 12, which is a schematic diagram illustrating a cross-section 1200 of a semiconductor substrate structure according to an embodiment of the present application. The cross-section 1200 of the structure may be the DD line cross-section of the structure 1000 shown in fig. 10A.

As can be appreciated by those skilled in the art with reference to fig. 12, the present application is not limited to the shape of the outer edges of the resin layers 1040A and 1040B, which may be square, rectangular, oval, or circular. When the metal layer 1010A and the resin layer 1040A are rectangular, the application also does not limit the thickness of the metal layer 1010A for surrounding the four borders of the resin layer 1040A. When the metal layer 1010B and the resin layer 1040B are rectangular, the application also does not limit the thickness of the metal layer 1010B for surrounding the four borders of the resin layer 1040B. In one embodiment, the four rims may have the same thickness to simplify design and manufacturing issues. In another embodiment, the thicknesses of the two groups of the four frames can be the same, so as to simplify the design and manufacturing problems. In a further embodiment, the thicknesses of the four rims may be substantially different to accommodate the requirements of the chip design.

Different areas of the chip can bear different semiconductor components, and the resistance values of the substrate structures required by the different semiconductor components can be different. Therefore, as shown in the embodiment of fig. 12, the thickness of the metal layer 1010 may be made thicker in some regions, and the metal of the metal layer 1010 may be replaced by a thicker resin layer 1040 in other regions, so as to adapt to the substrate structure resistance required by different semiconductor components. In terms of production, although the depth, shape and position of the resin layer 1040 vary, the same process is used to produce the resin layer 1040, and therefore the cost is only related to the amount of metal used.

Please refer to fig. 13, which is a diagram illustrating a wafer 1300 according to an embodiment of the present application. The wafer 1300 may be a four-inch, six-inch, eight-inch, twelve-inch, fourteen-inch, or sixteen-inch wafer as is commonly used in the industry. A wafer 1300 may be diced after semiconductor fabrication and packaging, which is commonly referred to as Wafer Level Chip Scale Package (WLCSP). As shown in fig. 13, the wafer 1300 may be pre-designed to be diced at the dashed lines to form a plurality of chips after packaging.

In FIG. 13, the wafer 1300 may include three chips 1310-1330 of the same size. In one embodiment, the three chips 1310-1330 may be chips of the same design. In other words, the three chips 1310-1330 may include one of the substrate structures 300-1200. Or all of the dies contained in the entire wafer 1300 may comprise the same substrate structure.

In another embodiment, the three chips 1310-1330 can be chips of different designs. That is, the three chips 1310-1330 may include two or three of the substrate structures 300-1200. In other words, the plurality of chips throughout the wafer 1300 include two or more substrate structures. For example, die 1310 may include substrate structure 500, die 1320 may include substrate structure 900, and die 1330 may include substrate structure 400. In another example, die 1310 may include substrate structure 300 and die 1320 may include substrate structure 800.

The chip of fig. 13 may also include the four

profiles

600, 700, 1100, and 1200 shown in fig. 6, 7, 11, and 12, respectively. In other words, the present application does not limit any two chips on the same wafer to use the same cross section.

Please refer to fig. 14, which is a diagram illustrating a wafer 1400 according to an embodiment of the present disclosure. The description above with respect to wafer 1300 may be applied to the embodiment of wafer 1400, except for the following differences.

Wafer 1400 includes three different shaped or sized dies, die 1310, 1420, and 1430, respectively. In one embodiment, the three chips 1310-1430 may be chips of the same design. In other words, the three chips 1310-1430 may include one of the substrate structures 300-1200. Or all of the dies contained in the entire wafer 1300 may comprise the same substrate structure.

In another embodiment, the three chips 1310-1430 may be chips of different designs. That is, the three chips 1310-1330 may include two or three of the substrate structures 300-1200. In other words, the plurality of chips of the entire wafer 1400 includes more than two substrate structures. For example, die 1310 may include substrate structure 500, die 1420 may include substrate structure 900, and die 1430 may include substrate structure 400. In another example, die 1310 may include substrate structure 300 and die 1420 may include substrate structure 800.

The chip of fig. 14 may also include the four

profiles

As can be seen from the

wafers

1300 and 1400 shown in fig. 13 and 14, the present application does not limit whether the chips on the same wafer have the same size and shape, or the chips have the same cross-sectional design, or the same substrate structure. When wafer level chip packaging is performed, a specific process may be performed on a wafer according to the design of the chips to be cut on the same wafer.

Referring to fig. 15, a flow chart of a wafer fabrication method 1500 according to an embodiment of the present application is shown. The wafer fabrication method 1500 shown in fig. 15 may be part of a wafer level chip packaging method. The wafer level chip packaging method can be a process of firstly manufacturing, packaging and testing an entire wafer, then cutting the wafer, and then placing the chip on an individual printed circuit board. One of the parts to be protected in this application is a manufacturing method for a substrate structure before package testing. Of course, the present application also contemplates a complete wafer level chip packaging method. The die fabricated by the wafer fabrication method 1500 of fig. 15 may include various substrate structures and cross-sections as described in fig. 3-14.

Please refer to fig. 16A-16J, which are cross-sectional views illustrating various stages of a wafer manufacturing process according to an embodiment of the present disclosure. FIGS. 16A-16J are each drawn for one of the dies in the wafer. In explaining the steps of fig. 15, reference may be made to the respective drawings of fig. 16A to 16J. It will be understood by those skilled in the art that although fig. 16A-16J are drawn for a cross-section of a die, they may be applied to the entire wafer generally, depending on the wafer design. In addition, in fig. 16A to 16J, drawings are mainly made for the substrate structure 1000. It will be appreciated by those skilled in the art that the wafer fabrication method 1500 may be used to fabricate other substrate structures as claimed herein, and is not limited to the substrate structure 1000.

Step 1510: a wafer is provided. The wafer may be the

wafer

1300 or 1400 shown in fig. 13 or 14. In fig. 16A, a cross-section of the wafer layer 820 can be seen. The top surface of the wafer layer 820 of fig. 16A is referred to as the second surface 822 of the embodiment of fig. 10A.

Step 1520: coating a shielding layer according to the size and the pattern of the chip to be cut. In fig. 16B, the pattern of the shield layer 1610 can be seen to be formed on the top surface of the wafer layer 820. The pattern of the shielding layer 1610 in each predetermined area of the chip is to form a frame region at least around the chip. When the substrate structure to be implemented is similar to the substrate structures 800-1000 shown in fig. 8A-10B or has inner frame structures, the pattern of the shielding layer 1610 can cover the areas of the inner frame structures. In one embodiment, the shielding layer may be a photoresist layer (photoresist layer) or other shielding layers such as silicon nitride.

Step 1530: and etching the wafer. The etching method may include wet etching, dry etching, plasma etching, Reactive Ion Etching (RIE), etc. As shown in fig. 16C, the etching depth may be about half the thickness of the wafer layer 820, but the thickness of the etching step is not limited in this application. After step 1530, a frame structure at the edge of the chip and/or a frame structure inside the chip are formed.

With the two

steps

1520 and 1530, the entire frame structure and inner frame structure of the wafer layer for all chips on the wafer can be formed. However, it will be understood by those skilled in the art that the steps of the wafer fabrication method 1500 may be performed not only on an entire wafer, but also on a single chip.

In one embodiment, steps 1520 and 1530 may be repeated if the wafer layer thickness of the inner frame structure is smaller than the wafer layer thickness of the bezel structure. In the first execution of step 1520, the pattern of the mask layer only includes the frame region. The first time the etching step 1530 is performed, the depth of the etch reaches the thickness of the inner frame structure. Next, step 1530 is performed for the second time, wherein the pattern of the mask layer includes the inner frame region. Next, a second etch 1530 may etch the wafer layer to half the height. Therefore, the frame structure and the frame structure with different thicknesses exist.

Step 1540: and removing the shielding layer on the wafer. As shown in fig. 16D, shield layer 1610 has been removed. It will be appreciated by those skilled in the art that removing the shield layer is a well known technique and is not described in detail herein.

Step 1550: one or more metal layers are fabricated on the wafer. This step may fabricate the metal layer on the etched second surface 822. Step 1550 may be performed using one of a variety of methods. These processes include sputtering, evaporation or Chemical Vapor Deposition (CVD), plating, or coating.

The metal layer may comprise one or more metal layers, which may comprise a single metal, alloy or metal compound. For example, the metal layer may include titanium-nickel-silver-nickel alloy (TiNiAgNi), nickel-aluminum alloy (AlNi), aluminum-copper-cobalt alloy (AlCuNi), titanium-copper-nickel alloy (ticoni), titanium alloy, vanadium-nickel alloy, silver alloy, nickel alloy, copper alloy, pure cobalt, and alloys containing various metals such as aluminum, titanium, nickel, silver, nickel, and copper.

In one embodiment, shown in FIG. 16E, the top surface of the metal layer, i.e., the fourth surface, formed in step 1550, is a flat surface. The fourth surface and the lower surface of the wafer layer, i.e. the first surface, should be parallel.

In one embodiment as shown in fig. 16F, the metal layer 1010 of the substrate structure may further include two

metal sub-layers

1011 and 1012. The two

metal sublayers

1011 and 1012 may be made of the same material or different materials. The shape of the metal sub-layer 1011 corresponds to the second surface 8222. The shape of the metal sublayer 1012 corresponds to the shape of the metal sublayer 1011. The method for forming metal sub-layer 1011 may be the same as or different from the method for forming metal sub-layer 1012. In a variation of the embodiment shown in FIG. 16F, only one metal layer 1010 may be included, which corresponds in shape to the second surface 822.

In one embodiment as shown in FIG. 16G, the substrate structure may comprise two

metal sub-layers

1011 and 1012. The shape of the metal sub-layer 1011 corresponds to the second surface 822. The lower surface of the metal sub-layer 1012 corresponds to the upper surface of the metal sub-layer 1011, but the upper surface of the metal sub-layer 1012, i.e. the fourth surface, is a plane. The fourth surface and the lower surface of the wafer layer, i.e. the first surface, should be parallel.

Although only two

metal sub-layers

1011 and 1012 are shown in the embodiments of FIGS. 16F and 16G, it will be understood by those skilled in the art that step 1550 can produce a metal layer containing more metal sub-layers.

After step 1550, the

substrate structure

300 or 800 shown in fig. 3, 8A, or 8B can be obtained.

After step 1550, flow may proceed to optional step 1570. In one embodiment, step 1580 may also be proceeded to.

Optional step 1570: coating a resin layer. To form the

substrate structures

400, 500, 900 and 1000 as shown in fig. 4, 5A, 5B, 9, 10A and 10B, the present step 1570 may be performed after step 1550.

The embodiments shown in FIGS. 16H-J are the results of applying a resin layer to the metal layer of the embodiments shown in FIGS. 16E-G, respectively.

Step 1580: and (5) subsequent packaging. Step 1580 may include multiple sub-steps, such as attaching an adhesive film (typically a blue PVC adhesive film) to the wafer for protection. Then, a chip label is printed for marking a manufacturer of the chip, a model number of the chip, a manufacturing lot number, a manufacturing factory, a manufacturing date, and the like. Then, dicing of the chip, and a subsequent packaging step of a tray (tray) or tape (tape reel), and the like are performed.

If 1520-1570 are applied to the chips, step 1580 may include a step of printing a chip label and packaging with a tray (tray) or tape and reel (tape and reel), and the step of cutting the wafer to obtain chips is omitted.

The wafer manufacturing method 1500 provided by the present application can perform a simultaneous construction on all chips of the wafer, so that all chips of the wafer can have one of the aforementioned substrate structures. And each chip is not required to be constructed individually, so that the construction time can be saved, and the cost can be reduced.

According to an embodiment of the present application, a substrate structure having a frame structure, a semiconductor wafer, and a wafer fabrication method are provided.

According to an embodiment of the present application, a substrate structure for supporting a semiconductor device is provided, comprising: a wafer layer having a first surface and a second surface corresponding to the first surface, wherein the second surface has a central recess region recessed toward the first surface, the central recess region being located in the second surface such that a frame structure region of the wafer layer surrounds the second surface; and a metal layer having a third surface and a fourth surface corresponding to each other, wherein the third surface is completely attached to the second surface.

In one embodiment, to compensate for the structural strength of the thinner wafer layer, the second surface further includes a first annular recessed region recessed toward the first surface, and the first annular recessed region and the central recessed region are located in the second surface, such that the wafer layer forms an annular first inner frame structure region between the first annular recessed region and the central recessed region.

In a specific embodiment, to further compensate for the structural strength of the thinner wafer layer, the second surface further has a second annular recessed area recessed toward the first surface, the second annular recessed area is located in the second surface, such that the wafer layer forms an annular second inner frame structure area between the second annular recessed area and the central recessed area, the first annular recessed area completely includes the annular first inner frame structure area, the first inner frame structure area completely surrounds the second annular recessed area, and the second annular recessed area completely surrounds the second inner frame structure area.

In one embodiment, to protect the metal layer and reduce the influence of physical stress and thermal stress, the substrate structure further comprises: and the resin layer is provided with a fifth surface and a sixth surface which correspond to each other, wherein the shape of the fifth surface corresponds to that of the fourth surface.

In one embodiment, to simplify the design of the semiconductor device carried by the substrate structure, the frame structure region sequentially includes a first side structure region, a second side structure region, a third side structure region and a fourth side structure region, and the first side structure region and the third side structure region have the same width.

In a specific embodiment, in order to simplify the design of the semiconductor device carried by the substrate structure, the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have the same width.

In one embodiment, in order to adapt the substrate structure to different designs of the semiconductor device to be carried, the frame structure region sequentially includes a first side structure region, a second side structure region, a third side structure region and a fourth side structure region, and the first side structure region and the third side structure region have different widths.

In a specific embodiment, in order to adapt the substrate structure to the semiconductor device to be carried with greater design flexibility, the widths of the first side structure region, the second side structure region, the third side structure region and the fourth side structure region are different.

In one embodiment, the central recessed area is rectangular in shape in order to fit the shape of most rectangular chips.

In one embodiment, to fit the shape of most square chips, the central recessed area is square.

In an embodiment, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the recessed region.

In one embodiment, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the first annular recessed region or the central recessed region.

In one embodiment, in order to reduce the resistance of the substrate region, a distance between the first surface and the second surface of the frame structure region is greater than or equal to a distance between the first surface and the second surface of the first inner frame structure region.

In an embodiment, to save the thickness of the metal layer and thus save the cost, the fourth surface has a metal layer recess area recessed toward the third surface, and a projection area of the metal layer recess area on the second surface is located in the central recess area.

In one embodiment, for design and manufacturing convenience, the metal layer recessed region corresponds to the shape of the recessed region, and the area of the metal layer recessed region is smaller than that of the central recessed region.

According to an embodiment of the present application, a semiconductor wafer is provided, wherein a first chip region is to be cut out of the semiconductor wafer, the first chip region comprising the substrate structure of the semiconductor device as described.

In one embodiment, in order to fabricate different chips by using the wafer area as much as possible, a second chip region is predetermined to be cut out of the semiconductor wafer, and includes the same substrate structure as the first chip region, and the first chip region and the second chip region have different shapes.

In one embodiment, in order to speed up the chip fabrication with the substrate structure using wafer-level chip manufacturing technology, a plurality of chip regions are pre-cut from the semiconductor wafer, each of the plurality of chip regions includes the same substrate structure as the first chip region, and each of the plurality of chip regions and the first chip region have the same shape.

According to an embodiment of the present application, a method for manufacturing a wafer is provided, comprising: coating a shielding layer on a second surface of a wafer layer according to the sizes and patterns of a plurality of chip areas to be cut, wherein a first chip area in the plurality of chip areas comprises a central depressed area uncovered by the shielding layer and a frame structure area covered by the shielding layer, the central depressed area is positioned in the frame structure area, and the frame structure area surrounds the second surface; etching the wafer layer in the central depression region; removing the shielding layer; and fabricating a metal layer on the second surface.

In an embodiment, to compensate for the structural strength of the thinner wafer layer, the first chip region further includes a first annular recessed area uncovered by the shielding layer and a first inner frame structure area covered by the shielding layer, the first annular recessed area surrounds the first inner frame structure area, the central recessed area is located in the first inner frame structure area, and the first annular recessed area is located in the frame structure area.

In an embodiment, to further compensate for the structural strength of the thinner wafer layer, the first chip region further includes a second annular recessed region uncovered by the shielding layer and a second inner frame structure region covered by the shielding layer, the first inner frame structure region completely surrounds the second annular recessed region, the second annular recessed region surrounds the second inner frame structure region, and the second inner frame structure region surrounds the central recessed region.

In one embodiment, to protect the metal layer and reduce the influence of physical stress and thermal stress, the wafer manufacturing method further comprises: a resin layer is coated on the metal layer.

In one embodiment, in order to speed up the chip fabrication with the substrate structure using wafer-level chip fabrication techniques, the steps are performed simultaneously for the plurality of chip regions of the wafer layer.

In one embodiment, in order to speed up the chip fabrication with the substrate structure using wafer-level chip fabrication technology, the wafer fabrication method further includes: dicing of the plurality of chip regions is performed.

In one embodiment, in order to speed up the chip fabrication with the substrate structure using wafer-level chip fabrication technology, the wafer fabrication method further includes: after the step of coating the resin layer, cutting of the plurality of chip regions is performed.

In an embodiment, in order to simplify the design of the semiconductor device carried by the substrate structure, the widths of the first side structure region, the second side structure region, the third side structure region and the fourth side structure region are the same.

In one embodiment, in order to adapt the substrate structure to the semiconductor device to be carried with greater design flexibility, the widths of the first side structure region, the second side structure region, the third side structure region and the fourth side structure region are different.

In one embodiment, in order to reduce the resistance of the substrate region, wherein the wafer layer includes a first surface corresponding to the second surface, after the etching step is performed, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the central recessed region.

In one embodiment, in order to reduce the resistance of the substrate region, after the etching step is partially performed, the shielding layer is covered on the first inner frame structure region, such that the distance from the first surface to the second surface of the frame structure region is greater than or equal to the distance from the first surface to the second surface of the first inner frame structure region.

In one embodiment, in order to reduce the resistance of the substrate region, after the etching step is partially performed, the shielding layer is covered on the second inner frame structure region, such that the distance from the first surface to the second surface of the frame structure region is greater than or equal to the distance from the first surface to the second surface of the second inner frame structure region.

In one embodiment, in order to fabricate different chips by using the area of the wafer as much as possible, the plurality of chip regions includes a second chip region, and the first chip region and the second chip region have different shapes.

In one embodiment, in order to speed up the chip fabrication with the substrate structure using wafer-level chip fabrication techniques, each of the plurality of chip regions and the first chip region have the same shape.

In an embodiment, in order to save the thickness of the metal layer and thus save the cost, the metal layer has a third surface and a fourth surface corresponding to each other, the third surface completely fits the second surface, wherein the fourth surface has a metal layer recessed region recessed toward the third surface, and a projection region of the metal layer recessed region on the second surface is located in the central recessed region.

In an embodiment, for design and manufacturing convenience, the metal layer recessed region corresponds to the central recessed region, and the area of the metal layer recessed region is smaller than that of the central recessed region.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A substrate structure for supporting a semiconductor device, comprising:

a wafer layer having a first surface and a second surface corresponding to the first surface, wherein the second surface has a central recess region recessed toward the first surface, the central recess region being located in the second surface such that a frame structure region of the wafer layer surrounds the second surface; and

a metal layer having a third surface and a fourth surface corresponding to each other, wherein the third surface is completely attached to the second surface.

2. The substrate structure of claim 1, wherein the second surface further comprises a first annular recessed region recessed toward the first surface, the first annular recessed region and the central recessed region being located within the second surface such that the wafer layer forms an annular first inter-frame structure region between the first annular recessed region and the central recessed region.

3. The substrate structure of claim 2, wherein the second surface further comprises a second annular recessed region recessed toward the first surface, the second annular recessed region being located within the second surface such that the wafer layer forms an annular second inner frame structure region between the second annular recessed region and the central recessed region, the first annular recessed region completely encompassing the annular first inner frame structure region, the first inner frame structure region completely encompassing the second annular recessed region, and the second annular recessed region completely encompassing the second inner frame structure region.

4. The substrate structure of a semiconductor device according to any one of claims 1, 2, and 3, further comprising: and the resin layer is provided with a fifth surface and a sixth surface which correspond to each other, wherein the shape of the fifth surface corresponds to that of the fourth surface.

5. The substrate structure of one of claims 1, 2 and 3, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have the same width.

6. The substrate structure of claim 4, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have the same width.

7. The substrate structure of claim 5, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have the same width.

8. The substrate structure of claim 6, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have the same width.

9. The substrate structure of one of claims 1, 2 and 3, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have different widths.

10. The substrate structure of claim 4, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, the first side structure region and the third side structure region having different widths.

11. The substrate structure of claim 7, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have different widths.

12. The substrate structure of claim 10, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have different widths.

13. The substrate structure of a semiconductor device according to any one of claims 1, 2, and 3, wherein the central recess region is rectangular.

14. The substrate structure of claim 4, wherein the central recessed region is rectangular.

15. The substrate structure of a semiconductor device according to any one of claims 1, 2, and 3, wherein the central recess region is square.

16. The substrate structure of claim 4, wherein the central recessed area is square.

17. The substrate structure of claim 1, 2 or 3, wherein a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the central recessed region.

18. The substrate structure of claim 2 or 3, wherein a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the first annular recessed region or the central recessed region.

19. The substrate structure of one of claims 2 and 3, wherein a distance between the first surface and the second surface of the bezel structure region is greater than or equal to a distance between the first surface and the second surface of the first inner frame structure region.

20. The substrate structure of claim 1, 2 or 3, wherein the fourth surface has a metal layer recess region recessed toward the third surface, and a projection region of the metal layer recess region on the second surface is located in the central recess region.

21. The substrate structure of claim 4, wherein the fourth surface has a metal layer recess region recessed toward the third surface, a projection of the metal layer recess region on the second surface being located in the central recess region.

22. The substrate structure of claim 20, wherein the metal layer recessed region corresponds in shape to the recessed region, the metal layer recessed region having an area smaller than the area of the central recessed region.

23. The substrate structure of claim 21, wherein the metal layer recessed region corresponds in shape to the recessed region, the metal layer recessed region having an area smaller than the area of the central recessed region.

24. A semiconductor wafer, wherein a first chip region is to be cut out of the semiconductor wafer, the first chip region comprising the substrate structure of the semiconductor component according to one of claims 1 to 3.

25. The semiconductor wafer of claim 24, wherein a second chip region is to be cut out of the semiconductor wafer, the second chip region comprising the same substrate structure as the first chip region, the first chip region and the second chip region having different shapes.

26. The semiconductor wafer of claim 24, wherein a plurality of chip regions are pre-cut from the semiconductor wafer, each of the plurality of chip regions comprises the same substrate structure as the first chip region, and each of the plurality of chip regions has the same shape as the first chip region.

27. A semiconductor wafer, wherein a first chip region is to be cut out of the semiconductor wafer, the first chip region comprising the substrate structure of the semiconductor device according to claim 4.

28. The semiconductor wafer of claim 27, wherein a second chip region is to be cut out of the semiconductor wafer, the second chip region comprising the same substrate structure as the first chip region, the first chip region and the second chip region having different shapes.

29. The semiconductor wafer of claim 27, wherein a plurality of chip regions are pre-cut from the semiconductor wafer, each of the plurality of chip regions comprising the same substrate structure as the first chip region, each of the plurality of chip regions having the same shape as the first chip region.

30. A method for fabricating a wafer, comprising:

coating a shielding layer on a second surface of a wafer layer according to the size and the pattern of a plurality of chip areas to be cut, wherein a first chip area in the plurality of chip areas comprises a central sunken area uncovered by the shielding layer and a frame structure area covered by the shielding layer, the central sunken area is positioned in the frame structure area, and the frame structure area surrounds the second surface;

etching the wafer layer in the central depression region;

removing the shielding layer; and

a metal layer is fabricated on the second surface.

31. The method of claim 30, wherein the first chip region further comprises a first annular recessed region uncovered by the mask layer and a first inner frame structure region covered by the mask layer, the first annular recessed region surrounds the first inner frame structure region, the central recessed region is located in the first inner frame structure region, and the first annular recessed region is located in the frame structure region.

32. The method of claim 31, wherein the first die area further comprises a second annular recessed area uncovered by the mask layer and a second inner frame structure area covered by the mask layer, the first inner frame structure area completely surrounding the second annular recessed area, the second annular recessed area surrounding the second inner frame structure area, and the second inner frame structure area surrounding the central recessed area.

33. The method of one of claims 30, 31 and 32, further comprising: a resin layer is coated on the metal layer.

34. The method of one of claims 30, 31 and 32, wherein said steps are performed simultaneously for said plurality of chip areas of said wafer layer.

35. The method of claim 33, wherein the steps are performed simultaneously for the plurality of die regions of the wafer layer.

36. The method of one of claims 30, 31 and 32, further comprising: dicing of the plurality of chip regions is performed.

37. The method of claim 33, further comprising: after the step of coating the resin layer, cutting of the plurality of chip regions is performed.

38. The method of one of claims 30, 31 and 32, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have the same width.

39. The method of claim 33, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have the same width.

40. The method of one of claims 30, 31 and 32, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have the same width.

41. The method of claim 33, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have the same width.

42. The method of one of claims 30, 31 and 32, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have different widths.

43. The method of claim 33, wherein the frame structure region comprises a first side structure region, a second side structure region, a third side structure region and a fourth side structure region in sequence, and the first side structure region and the third side structure region have different widths.

44. The method of claim 42, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have different widths.

45. The method of claim 43, wherein the first side structure region, the second side structure region, the third side structure region and the fourth side structure region have different widths.

46. The method of one of claims 30, 31 and 32, wherein said central recessed area is rectangular.

47. The method of claim 33, wherein the central recessed area is rectangular.

48. The method of one of claims 30, 31 and 32, wherein said central recessed area is square.

49. The method of claim 33, wherein the central recessed area is square.

50. The method of one of claims 30, 31 and 32, wherein the wafer layer comprises a first surface corresponding to the second surface, and wherein after the etching step, a distance between the first surface and the second surface of the frame structure region is greater than or equal to twice a distance between the first surface and the second surface of the central recessed region.

51. The method as claimed in claim 31, wherein after the etching step is performed partially, the shielding layer is covered on the first inner frame structure region such that a distance from the first surface to the second surface of the frame structure region is greater than or equal to a distance from the first surface to the second surface of the first inner frame structure region.

52. The method as claimed in claim 32, wherein the masking layer is applied to the second inner frame structure region after the etching step is partially performed, such that a distance between the first surface and the second surface of the frame structure region is greater than or equal to a distance between the first surface and the second surface of the second inner frame structure region.

53. The method of one of claims 30, 31 and 32, wherein said plurality of chip regions includes a second chip region, and said first chip region and said second chip region have different shapes.

54. The method of claim 33, wherein the plurality of chip regions includes a second chip region, and the first chip region and the second chip region have different shapes.

55. The method of one of claims 30, 31 and 32, wherein each of the plurality of chip regions and the first chip region have the same shape.

56. The wafer manufacturing method as claimed in claim 33, wherein each of the plurality of chip regions has the same shape as the first chip region.

57. The method of one of claims 30, 31 and 32, wherein the metal layer has a third surface and a fourth surface corresponding to each other, the third surface completely fits the second surface, and the fourth surface has a metal layer recessed region recessed toward the third surface, and a projected area of the metal layer recessed region on the second surface is located in the central recessed region.

58. The method of claim 33, wherein the metal layer has a third surface and a fourth surface corresponding to each other, the third surface completely adheres to the second surface, the fourth surface has a metal layer recessed region recessed toward the third surface, and a projected area of the metal layer recessed region on the second surface is located in the central recessed region.

59. The wafer manufacturing method as claimed in claim 57, wherein the metal layer recessed region corresponds to the shape of the central recessed region, and the area of the metal layer recessed region is smaller than that of the central recessed region.

60. The method as claimed in claim 58, wherein the metal layer recess region has a shape corresponding to that of the central recess region, and the area of the metal layer recess region is smaller than that of the central recess region.