CN111312190A - GOA driving circuit, positive and negative polarity charging compensation method thereof and display panel - Google Patents

GOA driving circuit, positive and negative polarity charging compensation method thereof and display panel Download PDF

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Publication number
CN111312190A
CN111312190A CN202010250481.7A CN202010250481A CN111312190A CN 111312190 A CN111312190 A CN 111312190A CN 202010250481 A CN202010250481 A CN 202010250481A CN 111312190 A CN111312190 A CN 111312190A
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unit
pull
signal
thin film
film transistor
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CN111312190B (en
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李艳
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a GOA driving circuit, a positive and negative polarity charging compensation method thereof and a display panel, wherein the GOA driving circuit is formed by cascading a plurality of levels of GOA units, and the current level of GOA unit comprises an up-pull control unit, an up-pull unit, a down-transfer unit, a down-pull maintaining unit, a bootstrap capacitor and a clock signal adjusting unit; the pull-up control unit is connected with the pull-up unit, the pull-down unit, the download unit, the pull-down maintaining unit and the bootstrap capacitor respectively; the clock signal adjusting unit is respectively connected with the downloading unit and the pulling-up unit. And the clock signal adjusting unit can adjust the voltage of the clock signal of the current stage according to the accessed selection signal. According to the method and the device, after the positive and negative polarities of the same column are reversed, the rising time of the voltage of the first line is kept the same as that of the same line in the same polarity, the charging of two adjacent lines is ensured to be the same, and the quality of a display effect is improved.

Description

GOA driving circuit, positive and negative polarity charging compensation method thereof and display panel
Technical Field
The application relates to the technical field of display panels, in particular to a GOA driving circuit, a positive and negative polarity charging compensation method thereof and a display panel.
Background
With the development of display technology and the improvement of TFT (Thin Film Transistor) performance, a GOA (Gate On Array) driving circuit has been increasingly commonly applied to a liquid crystal display device. The GOA driving circuit GOA is a driving method for making a scanning driving circuit on an array substrate of a conventional thin film transistor liquid crystal display panel to scan scanning lines line by line.
Currently, more and more display panels adopt the requirement of polarity inversion in the same column, for example, the inversion manner of "+/-/-/+/-" or "+/-/-/+/-, so that the rising time of the voltage of the first row after polarity inversion is longer than the time when the previous row and the current row have the same polarity, which significantly affects the adjustment of the charging of two adjacent rows in each row.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: after the polarity of the same row is inverted in the traditional GOA circuit, the rising time of the voltage of the first row is longer than the time when the previous row and the current row have the same polarity, the charging of two adjacent rows in each row is obviously influenced, and the quality of the display effect is reduced.
Disclosure of Invention
Therefore, after the same-column positive and negative polarities of the traditional GOA circuit are inverted, the rising time of the voltage of the first row is longer than the time when the previous row and the current row have the same polarity, which obviously affects the adjustment of the charging of each row and the charging of two adjacent rows, and causes the problem of the reduction of the quality of the display effect.
In order to achieve the above object, an embodiment of the present invention provides a GOA driving circuit, where the GOA driving circuit is formed by cascading multiple levels of GOA units, each level of GOA unit is used to drive a row of pixel units, and a current level of GOA unit includes:
the pull-up control unit is used for receiving a scanning signal of a previous stage and a level transmission signal of the previous stage and generating a scanning level signal of a current stage;
a pull-up unit for pulling up a scan signal of a current stage according to a scan level signal of the current stage and a clock signal of the current stage;
the down-transfer unit is used for generating a current stage level transfer signal according to a current stage scanning level signal and a current stage clock signal;
the pull-down unit is used for pulling down the scanning level signal of the current stage according to the scanning signal of the next stage;
a pull-down maintaining unit for maintaining a low level of the scan signal of the current stage and the scan level signal of the current stage;
a bootstrap capacitor for generating a high level of a scan signal of a current stage;
the clock signal adjusting unit is used for adjusting the voltage of the clock signal of the current stage according to the accessed selection signal;
the pull-up control unit is respectively connected with the pull-up unit, the pull-down unit, the download unit, the pull-down maintaining unit and the bootstrap capacitor; the clock signal adjusting unit is respectively connected with the downloading unit and the pulling-up unit; the pull-up unit is connected with the pull-down unit; the pull-down maintaining unit is respectively connected with the pull-up unit and the pull-down unit.
In one embodiment, the clock signal adjusting unit includes eighty-first, eighty-second, and eighty-third thin film transistors; the selection signals comprise a first selection signal, a second selection signal and a third selection signal;
the grid electrode of the eighty-first thin film transistor is used for accessing a first selection signal, the source electrode of the eighty-first thin film transistor is used for accessing a constant-voltage low-level signal, and the drain electrode of the eighty-first thin film transistor is respectively connected with the pull-up unit and the pull-down unit;
the grid electrode of the eighty-two thin film transistor is used for accessing a second selection signal, the source electrode of the eighty-two thin film transistor is used for accessing a first high-potential level signal, and the drain electrode of the eighty-two thin film transistor is respectively connected with the upper pulling unit and the lower transmission unit;
the gate of the eighty-third thin film transistor is used for accessing a third selection signal, the source is used for accessing a second high-potential level signal, and the drain is respectively connected with the pull-up unit and the pull-down unit.
In one embodiment, the pull-down sustain unit includes a first pull-down sustain subunit and a second pull-down sustain subunit;
the first pull-down maintaining subunit is respectively connected with the pull-up control unit, the pull-up unit and the download unit;
the second pull-down maintaining subunit is respectively connected with the pull-up control unit, the pull-up unit and the download unit.
In one embodiment, the system further comprises a reset unit which is connected with the pull-up control unit;
the reset unit is used for resetting the scanning level signal of the current stage.
In one embodiment, the pull-up control unit includes an eleventh thin film transistor;
the eleventh thin film transistor has a gate for receiving a previous stage scanning signal, a source for receiving a previous stage scanning signal, and a drain for outputting a current stage scanning level signal.
In one embodiment, the pull-up unit includes a twenty-first thin film transistor;
the twenty-first thin film transistor has a gate for receiving a scan level signal of a current stage, a source for receiving a clock signal of the current stage, and a drain for outputting a scan signal of the current stage.
In one embodiment, the downloading unit includes a twenty-second thin film transistor;
the gate of the twenty-second thin film transistor is used for receiving a scanning level signal of the current stage, the source of the twenty-second thin film transistor is used for receiving a clock signal of the current stage, and the drain of the twenty-second thin film transistor outputs a stage transmission signal of the current stage.
On the other hand, the embodiment of the invention also provides a positive and negative polarity charging compensation method, which comprises the following steps:
when the positive and negative polarities of the current moment are reversed, transmitting a selection signal to a clock signal adjusting unit; the selection signal is used for instructing the clock signal adjusting unit to adjust the voltage of the clock signal of the current stage.
In one embodiment, the method further comprises the following steps:
and when the positive and negative polarities of the current moment are reversed, adjusting the relative time of the clock signal of the current stage based on a preset step length, and respectively transmitting the adjusted clock signal of the current stage to the pull-up unit and the pull-down unit.
On the other hand, an embodiment of the present invention further provides a display panel, including the GOA driving circuit as described in any one of the above.
One of the above technical solutions has the following advantages and beneficial effects:
in each embodiment of the foregoing GOA driving circuit, the GOA driving circuit is formed by cascading multiple stages of GOA units, each stage of GOA unit is configured to drive a row of pixel units, and the current stage of GOA unit includes a pull-up control unit, a pull-up unit, a pull-down maintaining unit, a bootstrap capacitor, and a clock signal adjusting unit; the pull-up control unit is connected with the pull-up unit, the pull-down unit, the download unit, the pull-down maintaining unit and the bootstrap capacitor respectively; the clock signal adjusting unit is respectively connected with the downloading unit and the pulling-up unit; the pull-up unit is connected with the pull-down unit; the pull-down maintaining unit is respectively connected with the pull-up unit and the pull-down unit. The clock signal adjusting unit can adjust the voltage of the clock signal of the current stage according to the accessed selection signal, and the charging of each Gate is adjusted by adjusting the voltage of the clock signal of the current stage (the voltage of opening the Gate). According to the method and the device, after the positive and negative polarities of the same column are reversed, the rising time of the voltage of the first line is kept the same as that of the same line in the same polarity, the charging of two adjacent lines is ensured to be the same, and the quality of a display effect is improved.
Drawings
The present application will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram of a conventional GOA circuit;
FIG. 2 is a schematic diagram of a first structure of a GOA driving circuit according to an embodiment;
FIG. 3 is a schematic diagram of a second structure of a GOA driving circuit according to an embodiment;
FIG. 4 is a flow diagram illustrating a method for positive and negative charge compensation in one embodiment;
FIG. 5 is a diagram illustrating first waveforms of a positive and negative charge compensation method according to an embodiment;
FIG. 6 is a diagram illustrating a second waveform of the positive and negative polarity charging compensation method according to an embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In the description of the present application, it is to be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the conventional GOA circuit includes a pull-up control unit 110, a pull-up unit 120, a pull-down unit 130, a pull-down unit 140, a bootstrap capacitor 150, and a pull-down sustain unit 160. The pull-up control unit 110 includes an eleventh thin film transistor T11; the pull-up unit 120 includes a twenty-first thin film transistor T21; the down-transfer unit 130 includes a twenty-second thin film crystal T22; the pull-down unit 140 includes a thirty-first thin film transistor T31 and a forty-first thin film transistor T41; the pull-down maintaining unit 160 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, a fifty-fourth thin film transistor T54, a sixty-first thin film transistor T61, a sixty-second thin film transistor T62, a sixty-third thin film transistor T63, a sixty-fourth thin film transistor T64, a thirty-second thin film transistor T32, a thirty-third thin film transistor T33, a forty-second thin film transistor T42, a forty-third thin film transistor T43, a seventy-second thin film transistor T72, and a seventy-third thin film transistor T73.
The working process of the conventional GOA circuit is as follows: when the STV signal input to the pull-up control unit 110 is high, the eleventh thin film transistor T11 is turned on, the Q point is a high voltage, and the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 are turned on; and at this time, the CK signal inputted to the pull-up unit 120 and the pull-down unit 130 is at a low level, and the fifty-second thin film transistor T52, the fifty-fourth thin film transistor T54, the sixty-second thin film transistor T62, and the sixty-fourth thin film transistor T64 are turned on; knSum of signals PnThe signal is pulled low, the forty-second thin film transistor T42 and the thirty-second thin film transistor T32 are turned off, and the forty-third thin film transistor T43 and the thirty-third thin film transistor T33 are turned off. At the next moment, the CK signal is at a high level, the STV signal is at a low level, and at this moment, the Q point is in a floating state, and at this moment, the bootstrap capacitor 150 will bootstrap the Q point under the effect of the capacitor coupling due to the low and high voltage change of the CK signal, so that the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 are completely turned on, and G is turned onnIs a high level output. At the next time, the CK signal is low, STn+1Is at a high level, GnWhen the voltage is low, the thirty-first thin film transistor T31 and the forty-first thin film transistor T41 are turned on, the Q point is low, and the fifty-fourth thin film transistor T54, the fifty-second thin film transistor T52, the sixty-second thin film transistor T62, and the sixty-fourth thin film transistor T64 are turned off; when the LC signal or the LC2 signal is at a high level, the fifty-first thin film transistor T51/the fifty-third thin film transistor T53 or the sixty-first thin film transistor T61/the sixty-second thin film transistor T62 is turned on; pnSignals or KnWhen the signal is high level, the fourth TFT T42/the fifth TFT T32 or the fourth TFTT43/thirty-third TFT T33 is turned on, point Q is low voltage, GnIs continuously pulled low, the seventy-second thin film transistor T72 or the seventy-third thin film transistor T73 is turned on, STnIs pulled down, a series of guarantees GnThe level remains low.
After the polarity of the same row is inverted in the traditional GOA circuit, the rising time of the voltage of the first row is longer than the time when the previous row and the current row have the same polarity, the charging of two adjacent rows in each row is obviously influenced, and the quality of the display effect is reduced.
The GOA circuit aims to solve the problem that after the same-column positive and negative polarities of a traditional GOA circuit are reversed, the rising time of the voltage of a first row is longer than the time when the previous row and the current row have the same polarity, the charging of two adjacent rows of each row is obviously influenced, and the quality of a display effect is reduced. In one embodiment, as shown in fig. 2, a GOA driving circuit is provided. The GOA driving circuit is formed by cascading a plurality of levels of GOA units, each level of GOA unit is used for driving one line of pixel units, and the current level of GOA unit comprises:
a pull-up control unit 210, configured to receive a scanning signal STV of a previous stage and a stage signaling signal STV1 of the previous stage, and generate a scanning level signal of a current stage;
a pull-up unit 220 for pulling up the scan signal of the current stage according to the scan level signal of the current stage and the clock signal CK of the current stage;
a down-transfer unit 230 for generating a stage transfer signal of the present stage according to the scan level signal of the present stage and the clock signal CK of the present stage;
a pull-down unit 240 for pulling down a scan level signal of a current stage according to a scan signal of a next stage;
a pull-down maintaining unit 250 for maintaining a low level of the scan signal of the current stage and the scan level signal of the current stage;
a bootstrap capacitor 260 for generating a high level of the scan signal of the current stage;
the clock signal adjusting unit 270 is configured to adjust a voltage VGH of a clock signal of a current stage according to the accessed selection signal EN;
the pull-up control unit 210 is respectively connected to the pull-up unit 220, the pull-down unit 240, the pull-down unit 230, the pull-down sustain unit 250, and the bootstrap capacitor 260; the clock signal adjusting unit 270 is connected to the downloading unit 230 and the pulling-up unit 220 respectively; the pull-up unit 220 is connected with the pull-down unit 240; the pull-down maintaining unit 250 is connected to the pull-up unit 220 and the pull-down unit 230, respectively.
Specifically, the pull-up control unit 210 may generate a scan level signal of a current stage according to the received scan signal STV of the previous stage and the stage transmission signal of the previous stage, and transmit the scan level signal of the current stage to the pull-down unit 230 and the pull-up unit 220, respectively. The pull-up unit 220 may pull up the scan signal of the current stage according to the scan level signal of the current stage and the clock signal CK of the current stage; the downloading unit 230 may generate a stage transmission signal of the current stage according to the scan level signal of the current stage and the clock signal CK of the current stage; the pull-down unit 240 may pull down a scan level signal of a current stage according to a scan signal of a next stage; the pull-down maintaining unit 250 may maintain the low levels of the scan signal of the current stage and the scan level signal of the current stage; the bootstrap capacitor 260 may generate a high level of the scan signal of the current stage; the clock signal adjusting unit 270 may adjust a voltage of the clock signal of the current stage according to the accessed selection signal EN.
Further, the pull-up control unit 210 is respectively connected to the pull-up unit 220, the pull-down unit 240, the pull-down unit 230, the pull-down sustain unit 250, and the bootstrap capacitor 260; the clock signal adjusting unit 270 is connected to the downloading unit 230 and the pulling-up unit 220 respectively; the pull-up unit 220 is connected with the pull-down unit 240; the pull-down maintaining unit 250 is connected to the pull-up unit 220 and the pull-down unit 230, respectively. The clock signal adjusting unit 270 can adjust the voltage of the clock signal CK at the current stage according to the accessed selection signal EN, and adjust the charging of each Gate by adjusting the voltage of the clock signal at the current stage (the voltage at which the Gate is turned on).
In the embodiment of the GOA driving circuit, by adjusting the voltage of the clock signal of the current stage, after the polarities of the same columns are inverted, the rising time of the voltage of the first row is kept the same as that of the row with the same polarity, so that the charging of two adjacent rows is the same, and the quality of the display effect is improved.
In one embodiment, as shown in fig. 3, a GOA driving circuit is provided, where the GOA driving circuit is formed by cascading multiple levels of GOA units, each level of GOA unit is used to drive a row of pixel units, and a current level of GOA unit includes a pull-up control unit 310, a pull-up unit 320, a pull-down unit 330, a pull-down unit 340, a pull-down maintaining unit 350, a bootstrap capacitor 360, and a clock signal adjusting unit 370; the pull-up control unit 310 is connected to the pull-up unit 320, the pull-down unit 340, the pull-down unit 330, the pull-down sustain unit 350, and the bootstrap capacitor 360, respectively; the clock signal adjusting unit 370 is connected to the downloading unit 330 and the pulling-up unit 320, respectively; the pull-up unit 320 is connected with the pull-down unit 340; the pull-down maintaining unit 350 is connected to the pull-up unit 320 and the pull-down unit 330, respectively.
Wherein the clock signal adjusting unit 370 includes an eighty-first thin film transistor T81, an eighty-second thin film transistor T82, and an eighty-third thin film transistor T83; the select signals include a first select signal EN1, a second select signal EN2, and a third select signal EN 3.
The gate of the eighty-first thin film transistor T81 is used for receiving the first selection signal EN1, the source is used for receiving the constant voltage low level signal VSSQ, and the drain is connected to the pull-up unit 320 and the pull-down unit 330, respectively; the gate of the eighty-two thin film transistor T82 is used for receiving the second selection signal EN2, the source is used for receiving the first high-level signal VGH2, and the drain is respectively connected to the pull-up unit 320 and the pull-down unit 330; the gate of the eighty-three thin film transistor T83 is coupled to the third selection signal EN3, the source is coupled to the second high voltage level signal VGH1, and the drain is coupled to the pull-up unit 320 and the pull-down unit 330, respectively.
Note that the thin Film transistor is a tft (thin Film transistor).
Specifically, the first selection signal EN1 is connected based on the eighty-first thin film transistor T81, the source is connected to the constant voltage low level signal VSSQ, and the drain is connected to the pull-up unit 320 and the pull-down unit 330, respectively; the gate of the eighty-two thin film transistor T82 is used for receiving the second selection signal EN2, the source is used for receiving the first high-level signal VGH2, and the drain is respectively connected to the pull-up unit 320 and the pull-down unit 330; the gate of the eighty-three thin film transistor T83 is coupled to the third selection signal EN3, the source is coupled to the second high voltage level signal VGH1, and the drain is coupled to the pull-up unit 320 and the pull-down unit 330, respectively. When the first selection signal EN1 is asserted, the eighty-first thin film transistor T81 is turned on, and the constant voltage low level signal VSSQ asserted by the source is transmitted to the pull-up unit 320 and the pull-down unit 330 through the drain, respectively; when the second selection signal EN2 is asserted, the eighty-two thin film transistor T82 is turned on, and the first high level signal VGH1 asserted by the source is transmitted to the pull-up unit 320 and the pull-down unit 330 through the drain, respectively; when the third selection signal EN3 is asserted, the eighty-third tft T83 is turned on, and the first high level signal VGH2 whose source is asserted is transmitted to the pull-up unit 320 and the pull-down unit 330 through the drain.
Furthermore, when the polarities of the same row are inverted, the corresponding thin film transistors (the eighty-first thin film transistor T81, the eighty-second thin film transistor T82 or the eighty-third thin film transistor T83) can be turned on according to the accessed selection signals (the first selection signal EN1, the second selection signal EN2 or the third selection signal EN3), the voltage of the clock signal CK of the current stage is adjusted, and the charging of each Gate is adjusted by adjusting the voltage of the clock signal (the voltage at which the Gate is turned on) of the current stage.
Note that, the charging is adjusted by adjusting the high voltage of the clock signal CK at the present stage, and the higher the high voltage is, the better the charging capability is.
In one example, the bootstrap capacitor 350 may be used to maintain a voltage between the gate and the source of the twenty-first thin film transistor T21, stabilizing the output of the twenty-first thin film transistor T21.
In a specific embodiment, as shown in fig. 3, the pull-down sustain unit 360 includes a first pull-down sustain subunit and a second pull-down sustain subunit.
The first pull-down maintaining subunit is respectively connected to the pull-up control unit 310, the pull-up unit 320 and the pull-down unit 330; the second pull-down maintaining sub-unit is respectively connected to the pull-up control unit 310, the pull-up unit 320 and the pull-down unit 330.
Specifically, the first pull-down sustain subunit may include a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, a fifty-fourth thin film transistor T54, a forty-second thin film transistor T42, a thirty-second thin film transistor T32, and a seventy-second thin film transistor T72.
The second pull-down sustain sub-unit may include sixty-first, sixty-second, sixty-third, sixty-fourth, forty-third, thirty-third, T33, and seventy-third thin film transistors T73, a sixty-third thin film transistor T61, a sixty-second thin film transistor T62, a sixty-third thin film transistor T63, a sixty-fourth thin film transistor T64, a forty-third thin film transistor T43, a thirty-third thin film transistor T33.
Further, the first pull-down sustain subunit is controlled by a control signal LC1 applied to the gate of the fifty-first thin film transistor T51; the second pull-down sustain subunit is controlled by a control signal LC2 applied to the gate of the sixty-first thin film transistor T61. Under the alternate driving of the control signals LC1 and LC2, the first pull-down sustain subunit and the second pull-down sustain subunit alternately pair the Q point and the G pointnThe output signal of (a) is pull-down maintained.
It should be noted that the control signals LC1 and LC2 may be low-frequency signals with a period of 200 times the frame period and a duty ratio of one half, and the control signals LC1 and LC2 are out of phase by one half period.
In one embodiment, as shown in fig. 3, the GOA driving circuit further includes a reset unit 380 that connects the pull-up control unit; the reset unit 380 is used to reset the scan level signal of the current stage.
Specifically, the Reset unit 380 includes a forty-fourth thin film transistor T44, a gate of the forty-fourth thin film transistor T44 receiving a Reset signal Reset, a source of the Reset signal Reset receiving a constant voltage signal VSS, and a drain of the Reset signal Reset receiving a node Q.
It should be noted that the node Q is a common connection point of the pull-up control unit, the pull-up unit, the pull-down unit, the reset unit, the pull-down maintaining unit, the pull-down unit, and the bootstrap capacitor.
In one embodiment, as shown in fig. 3, the pull-up control unit 310 includes an eleventh thin film transistor T11. The eleventh thin film transistor T11 has a gate for receiving a previous stage scanning signal, a source for receiving a previous stage scanning signal, and a drain for outputting a current stage scanning level signal.
The gate of the eleventh tft T11 is used for receiving a previous stage signal, and the source is used for receiving a previous stage scanning signal, so that a current stage scanning level signal output by the drain of the eleventh tft T11 can be transmitted to the pull-down maintaining unit 360, the pull-up unit 320, and the pull-down unit 330, respectively.
In one embodiment, as shown in fig. 3, the pull-up unit 320 includes a twenty-first thin film transistor T21. The twenty-first thin film transistor T21 has a gate for receiving a scan level signal of a current stage, a source for receiving a clock signal CK of the current stage, and a drain for outputting a scan signal of the current stage.
Specifically, the gate of the twenty-first thin film transistor T21 is connected to the scan level signal of the current stage, the source is connected to the clock signal of the current stage, and the drain of the twenty-first thin film transistor T21 is pulled up to output the scan signal of the current stage.
In one embodiment, as shown in fig. 3, the drop-down unit 330 includes a twenty-second thin film transistor T22. The gate of the twenty-second thin film transistor T22 is used for receiving the scan level signal of the present stage, the source is used for receiving the clock signal CK of the present stage, and the drain outputs the stage transmission signal of the present stage.
Specifically, based on the gate of the twenty-second thin film transistor T22 accessing the scan level signal of the current stage, the source is accessed to the clock signal CK of the current stage, and the drain of the twenty-second thin film transistor T22 pulls down the sustain unit to transmit the stage signal of the current stage.
In one embodiment, as shown in fig. 4, there is provided a positive and negative polarity charge compensation method, including the steps of:
step S410, when the positive and negative polarities of the current moment are reversed, a selection signal is transmitted to the clock signal adjusting unit; the selection signal is used for instructing the clock signal adjusting unit to adjust the voltage of the clock signal of the current stage.
Wherein the selection signal may be a first selection signal, a second selection signal or a third selection signal. When the positive and negative polarities at the current moment are reversed, the corresponding selection signals are transmitted to the clock signal adjusting unit, then the clock signal adjusting unit can adjust the voltage of the clock signal of the current stage according to the accessed selection signals, and the charging of each Gate is adjusted by adjusting the voltage of the clock signal of the current stage (the voltage for opening the Gate).
In the embodiment of the positive and negative polarity charging compensation method, after the positive and negative polarities of the same column are reversed, the rising time of the voltage of the first row is kept to be the same as that of the row when the polarity of the same column is the same by adjusting the voltage of the clock signal of the current stage, so that the charging of two adjacent rows is the same, and the quality of the display effect is improved.
In a specific embodiment, as shown in fig. 4, the positive and negative polarity charge compensation method further includes the following steps:
step S420, when the positive and negative polarities of the current time are reversed, adjusting the relative time of the clock signal of the current stage based on the preset step length, and transmitting the adjusted clock signal of the current stage to the pull-up unit and the pull-down unit, respectively.
Specifically, the waveform diagram is based on the positive and negative polarity charging compensation method. And when the positive polarity and the negative polarity of the current moment are reversed, the relative time of the clock signal of the current stage is increased based on the preset step length, and the increased clock signal of the current stage is respectively transmitted to the pull-up unit and the pull-down unit. The charging of each Gate is adjusted by adjusting the relative time of the clock signal of the current stage (the relative time when the Gate is turned on).
For another example, when the positive and negative polarities of the current time are inverted, the relative time of the clock signal of the current stage is reduced based on the preset step length, and the reduced clock signal of the current stage is transmitted to the pull-up unit and the pull-down unit respectively. The charging of each Gate is adjusted by adjusting the relative time of the clock signal of the current stage (the relative time when the Gate is turned on).
In one example, as shown in fig. 5, a CK waveform schematic of a positive and negative polarity charge compensation method is provided. By adjusting the relative time of the CK signal, for example, on the basis of the original relative time H, the relative time is increased or decreased by 0.2H. Namely, when the current positive and negative polarities are reversed, the opening relative time of the CK signal is H; then the on time of the CK signal is 2H +/-0.2H at the next positive and negative polarity reversal; and when the positive polarity and the negative polarity are reversed next time, the opening time of the CK signal is 3H, and the like.
Further, as shown in fig. 6, a gate waveform diagram of the positive and negative polarity charge compensation method is provided. Based on the CK waveform diagram shown in fig. 5, the on time of the CK signal, i.e., the on time of the gate, is adjusted. If the current positive and negative polarities are reversed, the relative opening time of the gate is H; the opening time of the gate is H +/-0.2H when the positive and negative polarities are reversed next time; when the positive and negative polarities are reversed next time, the opening time of the gate is adjusted to be H again, and so on. The charging of each Gate is adjusted by adjusting the time that the Gate is on, i.e., the relative time of the CK signal.
In the embodiment of the positive and negative polarity charging compensation method, by adjusting the relative time of the clock signal of the current stage, after the positive and negative polarities of the same column are reversed, the rising time of the voltage of the first row is kept to be the same as that of the row, the charging of the two adjacent rows is ensured to be the same, and the quality of the display effect is improved.
It should be understood that, although the steps in the flowchart of fig. 4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, there is also provided a display panel including the GOA driving circuit as described in any one of the above.
Among them, the display panel may be a current driving type display panel. For example, the display panel may be, but is not limited to, an OLED display panel, a Micro-LED display panel, a Mini-LED display panel, and the like.
For specific definition of the display panel, reference may be made to the definition of the GOA driving circuit in the above, and details are not described herein.
It should be noted that the display panel of the above embodiments can be applied to various sizes and mode display liquid crystal panels.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the division methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. The GOA driving circuit is characterized in that the GOA driving circuit is formed by cascading a plurality of GOA units, each GOA unit is used for driving a row of pixel units, and the current GOA unit comprises:
the pull-up control unit is used for receiving a scanning signal of a previous stage and a level transmission signal of the previous stage and generating a scanning level signal of a current stage;
a pull-up unit for pulling up the scan signal of the current stage according to the scan level signal of the current stage and the clock signal of the current stage;
the down-transfer unit is used for generating a current stage level transfer signal according to the current stage scanning level signal and the current stage clock signal;
the pull-down unit is used for pulling down the scanning level signal of the current stage according to the scanning signal of the next stage;
a pull-down maintaining unit for maintaining a low level of the scan signal of the present stage and the scan level signal of the present stage;
a bootstrap capacitor for generating a high level of the scan signal of the present stage;
the clock signal adjusting unit is used for adjusting the voltage of the clock signal of the current stage according to the accessed selection signal;
the pull-up control unit is respectively connected with the pull-up unit, the pull-down unit, the download unit, the pull-down maintaining unit and the bootstrap capacitor; the clock signal adjusting unit is respectively connected with the downloading unit and the pulling-up unit; the pull-up unit is connected with the pull-down unit; the pull-down maintaining unit is connected with the pull-up unit and the pull-down unit respectively.
2. The GOA driving circuit according to claim 1, wherein the clock signal conditioning unit comprises an eighty-first thin film transistor, an eighty-second thin film transistor, and an eighty-third thin film transistor; the selection signals comprise a first selection signal, a second selection signal and a third selection signal;
the gate of the eighty-first thin film transistor is used for accessing the first selection signal, the source of the eighty-first thin film transistor is used for accessing a constant-voltage low-level signal, and the drain of the eighty-first thin film transistor is respectively connected with the pull-up unit and the pull-down unit;
the gate of the eighty-second thin film transistor is used for accessing the second selection signal, the source of the eighty-second thin film transistor is used for accessing the first high-potential level signal, and the drain of the eighty-second thin film transistor is respectively connected with the pull-up unit and the pull-down unit;
and the gate of the eighty-third thin film transistor is used for accessing the third selection signal, the source of the eighty-third thin film transistor is used for accessing the second high-potential level signal, and the drain of the eighty-third thin film transistor is respectively connected with the pull-up unit and the pull-down unit.
3. The GOA driving circuit according to claim 1, wherein the pull-down sustain unit comprises a first pull-down sustain subunit and a second pull-down sustain subunit;
the first pull-down maintaining subunit is respectively connected with the pull-up control unit, the pull-up unit and the pull-down unit;
the second pull-down maintaining subunit is connected to the pull-up control unit, the pull-up unit, and the pull-down unit, respectively.
4. The GOA driving circuit according to claim 1, further comprising a reset unit connected to the pull-up control unit;
the reset unit is used for resetting the scanning level signal of the current stage.
5. The GOA driving circuit according to claim 1, wherein the pull-up control unit comprises an eleventh thin film transistor;
the eleventh thin film transistor has a gate for receiving the previous stage scanning signal, a source for receiving the previous stage scanning signal, and a drain for outputting the current stage scanning level signal.
6. The GOA driving circuit according to claim 1, wherein the pull-up unit comprises a twenty-first thin film transistor;
the twenty-first thin film transistor has a gate connected to the scan level signal of the current stage, a source connected to the clock signal of the current stage, and a drain outputting the scan signal of the current stage.
7. The GOA driving circuit according to claim 1, wherein the down-transfer unit comprises a twenty-second thin film transistor;
the gate of the twenty-second thin film transistor is used for accessing the scanning level signal of the current stage, the source of the twenty-second thin film transistor is used for accessing the clock signal of the current stage, and the drain of the twenty-second thin film transistor outputs the stage transmission signal of the current stage.
8. A positive and negative polarity charging compensation method is characterized by comprising the following steps:
when the positive and negative polarities of the current moment are reversed, transmitting a selection signal to a clock signal adjusting unit; the selection signal is used for instructing the clock signal adjusting unit to adjust the voltage of the clock signal of the current stage.
9. The positive-negative polarity charge compensation method according to claim 8, further comprising the steps of:
and when the positive and negative polarities of the current moment are reversed, adjusting the relative time of the clock signal of the current stage based on a preset step length, and respectively transmitting the adjusted clock signal of the current stage to the pull-up unit and the pull-down unit.
10. A display panel comprising the GOA driver circuit of any one of claims 1-7.
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