CN111310396B - FPGA virtual platform and method for realizing FPGA virtual platform - Google Patents
FPGA virtual platform and method for realizing FPGA virtual platform Download PDFInfo
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Abstract
The invention provides an FPGA virtual platform and a method for realizing the same. The beneficial effects of the invention are as follows: the invention is developed based on systemc, verilog design language, so that the user can not only reduce the learning and development cost, but also shorten the development period of the FPGA.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to an FPGA virtual platform and a method for realizing the FPGA virtual platform based on systemc and verilog.
Background
FPGA (Field-Programmable Gate Array), i.e., field programmable gate array. FPGA is a product developed on the basis of GAL, PAL, CPLD and other programmable devices, and is used as a semi-custom circuit in the field of integrated circuits (ASIC), so that the defects of the custom circuit are overcome, and the defect of limited gate circuits of the original editable device is overcome. From the chip perspective, an FPGA is a programmable digital logic chip, which can be programmed by HDL (hardware description language) language to achieve the desired digital functions. From a functional perspective, what digital functions we want an FPGA to implement, just like the building blocks of the music book, depends on our HDL code.
Verilog is an abbreviation for Verilog HDL, which is a hardware description language (HDL: hardware Description Language) that is a language for electronic system hardware behavior description, structure description, and data flow description. With this language, the design of digital circuitry can describe its design ideas layer by layer from top to bottom (from abstract to concrete), representing extremely complex digital systems with a series of hierarchical modules.
System C is a software/hardware collaboration, system level modeling design language. Briefly, system c is a c++ class library developed using the c++ programming language and provides an event-driven emulation core (Simulation Kernel) to schedule the execution order of various processes. The idea of the scheduling algorithm of Systemc is to divide continuous simulation time into a plurality of discrete simulation moments, divide a simulation moment into a plurality of delta-cycles, and update channel values after one delta-cycle or a plurality of delta-cycle periods (the channel design of the sistom is very smart and similar to the effect of shadow variables), so that the parallel behavior of hardware can be simulated by using programming languages sequentially executed in the delta-cycles. Enabling designers of emulation systems to simulate parallel processes with c++ grammar rules, especially in SoC systems.
There are many types of FPGA hardware products in the market at present, but the complexity problem of the hardware system and the cost problem of the hardware system bring many inconveniences to the user, and are inconvenient for the user to learn, develop, debug the FPGA, etc.
Disclosure of Invention
The invention provides an FPGA virtual platform, which comprises a TCP server component, a verilog adapter component, an FPGA core component, an FPGA resource component, an FPGA debugging component and a verilog component,
the TCP server component: the interaction function between the FPGA virtual platform and the outside is provided;
the verilog adapter component: analyzing the configuration file of the verilog component of the user, generating a verilog interface adaptation file, and finally converting the verilog interface component into a system c interface component;
the FPGA core component: initializing FPGA virtual peripheral resources, providing an FPGA virtual core clock, realizing an FPGA pin mapping function, packaging an FPGA state value and sending the FPGA state value to a TCP server component;
the FPGA resource component: the virtual peripheral function of the FPGA virtual platform is defined, and the virtual peripheral function comprises an FPGA virtual pin and a virtual pull-up resistor or pull-down resistor;
the FPGA debug component: the method is used for user debugging and comprises the steps of analyzing or packaging a TCP data packet, setting an FPGA excitation signal and setting waveform tracking;
the verilog component: the verilog interface component provided by the user is not only a component part of the FPGA virtual platform, but also a debugged user code block.
As a further improvement of the present invention, the TCP server component has the following functions: analyzing or packaging a TCP data packet, calling a verilog adapter component to convert a verilog interface component into a system c interface component, calling an FPGA debugging component to set an FPGA excitation signal or checking waveforms, and calling an FPGA core component to acquire an FPGA state value.
As a further improvement of the invention, the FPGA virtual pins comprise an led peripheral, an SEG peripheral, an RGB peripheral, a dial switch peripheral and a key peripheral.
The invention also provides a method for realizing the FPGA virtual platform based on the system c and the verilog, which comprises the following steps:
step 1: realizing a verilog component meeting the interface specification, verifying the correctness of the verilog component by using a physical hardware platform, and if the verilog component is correct, executing the step 2;
step 2: the system mc component meeting the interface specification is realized, and comprises an FPGA core component, an FPGA resource component, a tcp server component, a verilog adapter component and an FPGA debugging component;
step 3: verifying the correctness of the system c component by using the verified verilog component, wherein the functions required to be verified of the FPGA core component comprise initialization of FPGA virtual peripheral resources, FPGA virtual core clocks, FPGA pin mapping functions and sending of FPGA state values to the TCP server component; the functions of the FPGA resource component to be verified comprise definition of an FPGA virtual pin and realization of a virtual pull-up resistor or a pull-down resistor; the function of the tcp server component to be verified comprises an interaction function of the FPGA virtual platform and the outside; the functions to be verified of the FPGA debugging component comprise the processing of TCP data packets, the setting of FPGA excitation signals and waveform tracking; the functions of the verilog adapter component to be verified comprise analysis of a user's verilog component configuration file, generation of a verilog interface adaptation file, and conversion of the verilog component into a system c interface component; if all functions of the system component are correct, executing the step 4;
step 4: and building an FPGA virtual platform by using the verified system component and a verilog component provided by a user, and carrying out learning, development and debugging of the FPGA by the user through the virtual platform.
As a further improvement of the invention, in the step 2, verilog interface information is extracted to generate a verilog configuration file, a verilog adapter file is generated according to the verilog configuration file, and a verilog component is converted into a system c interface form; the FPGA virtual platform is built by converting the verilog component into a system c interface form and the system c component, and the platform is operated.
The beneficial effects of the invention are as follows: the invention is developed based on systemc, verilog design language, so that the user can not only reduce the learning and development cost, but also shorten the development period of the FPGA.
Drawings
FIG. 1 is a diagram of an FPGA virtual platform architecture of the present invention;
fig. 2 is a flow chart of the method of the present invention.
Detailed Description
The product with the FPGA virtual platform can replace an actual hardware platform, and needs to provide customized components with a certain scale, such as an FPGA core component, an FPGA resource component, a TCP server component, a verilog adapter component and other common equipment components. On the basis, the product can automatically generate the FPGA virtual platform containing the verilog functional components on the premise that the user designs the verilog functional components independently. The platform is convenient for the user to learn, develop and debug the FPGA. By using the product, the user can not only reduce the learning and development cost, but also shorten the development period of the FPGA.
The invention is based on systemc, verilog design language development, and users can use the product to develop and debug HDL (verilog) language and learn to master the development flow of FPGA. Nowadays, the popularity of the FPGA in universities is higher and higher, the waste of hardware resources and the inconvenience of carrying are caused in the traditional teaching, and the complexity of hardware operation makes students have a certain difficulty in use, so that the learning and exploration of the students are intangibly reduced. The product is convenient to use and is very suitable for teaching in high schools.
The invention relates to a method for realizing an FPGA virtual platform based on systems and verilog, which can realize the FPGA virtual platform with a simulation debugging function through the use of the method. The method comprises the following key points: 1) An implementation method of FPGA component interface specification. By applying the method, the FPGA virtual platform can be realized based on the systems and verilog.
The FPGA virtual platform component mainly comprises the contents of simulation of a pull-up/pull-down resistor, peripheral pin binding, FPGA clock source creation, FPGA co-programming scheduling, FPGA waveform tracking, FPGA excitation signal setting, TCP/IP communication and the like, and the structure diagram is shown in figure 1.
As shown in fig. 1, the overall software architecture includes several constituent components: TCP server component, verilog adapter component, FPGA core component, FPGA resource component, FPGA debug component, verilog to system component.
TCP server component: and providing an interaction function between the FPGA virtual platform and the outside. The assembly has the following functions: analyzing or packaging a TCP data packet, calling a verilog adapter component to convert the verilog interface component into a system c interface component, calling an FPGA debugging component to set an FPGA excitation signal or check waveforms, calling an FPGA core component to acquire FPGA state values and the like.
FPGA core component: initializing FPGA virtual peripheral resources, providing an FPGA virtual core clock, realizing an FPGA pin mapping function, and packaging an FPGA state value and sending the FPGA state value to a TCP server component.
FPGA resource component: the component defines the virtual peripheral function of the FPGA virtual platform, and comprises FPGA virtual pins (resources such as led peripheral, SEG peripheral, RGB peripheral, dial switch peripheral, key peripheral and the like), and virtual pull-up or pull-down resistors.
FPGA debugging component: the method is mainly used for user debugging and comprises the steps of analyzing or packaging a TCP data packet, setting an FPGA excitation signal and setting waveform tracking.
verilog component: the verilog interface component provided by the user is not only a component part of the FPGA virtual platform, but also a debugged user code block.
The above mentioned functions of the FPGA virtual platform, the interface specifications of which are summarized in tables 1, 2, 3, 4 and 5.
Table 1 FPGA resource component interface Specification for a virtual platform
Table 2 TCP server component interface specification
Table 3 verilog adapter component interface Specification
Table 4 FPGA core component interface Specification
Table 5 FPGA debug component interface Specification
As shown in table 1, table 2, table 3, table 4, and table 5, the specification constraints of the port and component interface functions of the FPGA virtual platform are described. These port, interface specification constraints are the core content of the method.
Through the realization of the interface specifications of all the components of the FPGA, the FPGA virtual platform can be realized based on the systems and verilog.
As shown in fig. 2, the invention discloses a method for realizing an FPGA virtual platform based on systemc and verilog, which comprises the following steps:
step 1: realizing a verilog component meeting the interface specification, verifying the correctness of the verilog component by using a physical hardware platform, and if the verilog component is correct, executing the step 2;
step 2: the system mc component meeting the interface specification is realized, and comprises an FPGA core component, an FPGA resource component, a tcp server component, a verilog adapter component and an FPGA debugging component;
step 3: verifying the correctness of the system c component by using the verified verilog component, wherein the functions required to be verified of the FPGA core component comprise initialization of FPGA virtual peripheral resources, FPGA virtual core clocks, FPGA pin mapping functions and sending of FPGA state values to the TCP server component; the functions of the FPGA resource component to be verified comprise definition of an FPGA virtual pin and realization of a virtual pull-up resistor or a pull-down resistor; the function of the tcp server component to be verified comprises an interaction function of the FPGA virtual platform and the outside; the functions to be verified of the FPGA debugging component comprise the processing of TCP data packets, the setting of FPGA excitation signals and waveform tracking; the functions of the verilog adapter component to be verified comprise analysis of a user's verilog component configuration file, generation of a verilog interface adaptation file, and conversion of the verilog component into a system c interface component; if all functions of the system component are correct, executing the step 4;
step 4: and building an FPGA virtual platform by using the verified system component and a verilog component provided by a user, and carrying out learning, development and debugging of the FPGA by the user through the virtual platform.
In the step 2, verilog interface information is extracted, a verilog configuration file is generated, a verilog adapter file is generated according to the verilog configuration file, and a verilog component is converted into a system mc interface form; the FPGA virtual platform is built by converting the verilog component into a system c interface form and the system c component, and the platform is operated.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (9)
1. The FPGA virtual platform is characterized by comprising a TCP server component, a verilog adapter component, an FPGA core component, an FPGA resource component, an FPGA debugging component and a verilog component, wherein the TCP server component is used for sending a message to the FPGA core component, and the message comprises a message control protocol (TCP) message control protocol (message control protocol) message control protocol: the interaction function between the FPGA virtual platform and the outside is provided;
the verilog adapter component: analyzing the configuration file of the verilog component of the user, generating a verilog interface adaptation file, and finally converting the verilog interface component into a system c interface component;
the FPGA core component: initializing FPGA virtual peripheral resources, providing an FPGA virtual core clock, realizing an FPGA pin mapping function, packaging an FPGA state value and sending the FPGA state value to a TCP server component;
the FPGA resource component: the virtual peripheral function of the FPGA virtual platform is defined, and the virtual peripheral function comprises an FPGA virtual pin and a virtual pull-up resistor or pull-down resistor;
the FPGA debug component: the method is used for user debugging and comprises the steps of analyzing or packaging a TCP data packet, setting an FPGA excitation signal and setting waveform tracking;
the verilog component: the verilog interface component provided by the user is not only a component part of the FPGA virtual platform, but also a debugged user code block.
2. The FPGA virtual platform of claim 1, wherein,
the TCP server component has the following functions: analyzing or packaging a TCP data packet, calling a verilog adapter component to convert a verilog interface component into a system c interface component, calling an FPGA debugging component to set an FPGA excitation signal or checking waveforms, and calling an FPGA core component to acquire an FPGA state value.
3. The FPGA virtual platform of claim 1, wherein the FPGA virtual pins comprise led peripherals, SEG peripherals, RGB peripherals, dial switch peripherals, key peripherals.
4. The FPGA virtual platform of claim 1, wherein,
table 1 FPGA resource component interface Specification for a virtual platform
5. The FPGA virtual platform of claim 1, wherein,
table 2 TCP server component interface specification
6. The FPGA virtual platform of claim 1, wherein,
table 3 verilog adapter component interface Specification
7. The FPGA virtual platform of claim 1, wherein,
table 4 FPGA core component interface Specification
8. The FPGA virtual platform of claim 1, wherein,
table 5 FPGA debug component interface Specification
9. A method for realizing an FPGA virtual platform based on system c and verilog is characterized by comprising the following steps:
step 1: realizing a verilog component meeting the interface specification, verifying the correctness of the verilog component by using a physical hardware platform, and if the verilog component is correct, executing the step 2;
step 2: the system mc component meeting the interface specification is realized, and comprises an FPGA core component, an FPGA resource component, a tcp server component, a verilog adapter component and an FPGA debugging component;
step 3: verifying the correctness of the system c component by using the verified verilog component, wherein the functions required to be verified of the FPGA core component comprise initialization of FPGA virtual peripheral resources, FPGA virtual core clocks, FPGA pin mapping functions and sending of FPGA state values to the TCP server component; the functions of the FPGA resource component to be verified comprise definition of an FPGA virtual pin and realization of a virtual pull-up resistor or a pull-down resistor; the function of the tcp server component to be verified comprises an interaction function of the FPGA virtual platform and the outside; the functions to be verified of the FPGA debugging component comprise the processing of TCP data packets, the setting of FPGA excitation signals and waveform tracking; the functions of the verilog adapter component to be verified comprise analysis of a user's verilog component configuration file, generation of a verilog interface adaptation file, and conversion of the verilog component into a system c interface component; if all functions of the system component are correct, executing the step 4;
step 4: building an FPGA virtual platform by using the verified system component and a verilog component provided by a user, and carrying out learning, development and debugging of the FPGA by the user through the virtual platform;
in the step 2, verilog interface information is extracted, a verilog configuration file is generated, a verilog adapter file is generated according to the verilog configuration file, and a verilog component is converted into a system mc interface form; the FPGA virtual platform is built by converting the verilog component into a system c interface form and the system c component, and the platform is operated.
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