CN111309668A

CN111309668A - On-track reconstruction implementation method of differentially injected erasing-free FPGA (field programmable Gate array)

Info

Publication number: CN111309668A
Application number: CN202010076713.1A
Authority: CN
Inventors: 呼红阳; 谢元禄; 张坤; 霍长兴; 刘璟; 张君宇; 毕津顺
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-01-23
Filing date: 2020-01-23
Publication date: 2020-06-19

Abstract

The invention provides an on-track reconstruction implementation method of an FPGA (field programmable gate array) with difference injection and erasing prevention, which comprises the following steps of: step S1: carrying out XOR processing on the new matched code and the original matched code on the ground to generate a difference matched code; step S2: transmitting the difference matching code generated in the step S1 to the satellite-borne single machine through ground-rail communication; step S3: storing the difference configuration code into a satellite-borne FPGA configuration memory; and step S4: and refreshing and configuring the FPGA through a storage controller to complete the on-track reconstruction of the FPGA with the difference injection and erasing-free performance. In the process of configuring the FPGA, the read matched data can be dynamically modified according to the difference matched data, so that the matched data output to the FPGA are new matched data, erasing operation on the storage array is avoided, and the time of on-track reconstruction is greatly saved.

Description

On-track reconstruction implementation method of differentially injected erasing-free FPGA (field programmable Gate array)

Technical Field

The disclosure relates to the technical field of satellite data transmission and processing, in particular to a difference erasing-free FPGA (field programmable gate array) on-track reconstruction implementation method.

Background

At present, with the continuous development of satellite technology, the continuous improvement of user technical indexes and the increasingly intense market competition, the integration and the light miniaturization of functionality have become a mainstream trend of satellite-borne electronic equipment. The adoption of the miniaturization technology can reduce the volume, the weight and the power consumption of the satellite-borne electronic equipment, and improve the capability of the spacecraft for bearing the effective load and the efficiency ratio. The size of the printed board can be reduced and the number of pads can be reduced by adopting a high-function integrated miniaturized device. The FPGA is an important implementation mode for realizing the miniaturization of a satellite-borne digital circuit, but in the existing satellite-borne FPGA application system, when a satellite is assembled and is transmitted by the satellite, the FPGA is difficult to reconstruct, the main bottleneck is that the data quantity of the FPGA is too large, the in-orbit signal transmission speed is very low, and for some satellite-borne single machines, the transmission of one-time complete FPGA code matching needs to be carried out for hundreds of in-orbit tasks theoretically, and the feasibility is lacked in the actual operation.

In order to solve the above problems, the proposed solution is to compress the original data, for example, by using zero-run algorithm, etc., to reduce the data size to 1/5-1/3, but still needs to perform an on-track whole erase and rewrite operation on the memory chip.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

Technical problem to be solved

Based on the above problems, the present disclosure provides an on-track reconstruction implementation method for an FPGA with no erasing and writing difference, so as to alleviate technical problems in the prior art that the data size of the FPGA configuration is too large, the on-track signal transmission speed is very slow, and the like.

(II) technical scheme

The invention provides an on-track reconstruction implementation method of an FPGA (field programmable gate array) with difference injection and erasing prevention, which comprises the following steps of:

step S1: carrying out XOR processing on the new matched code and the original matched code on the ground to generate a difference matched code;

step S2: transmitting the difference matching code generated in the step S1 to the satellite-borne single machine through ground-rail communication;

step S3: storing the difference configuration code into a satellite-borne FPGA configuration memory; and

step S4: and refreshing and configuring the FPGA through a storage controller to complete the on-track reconstruction of the FPGA with the difference injection and erasing-free performance.

In the embodiment of the present disclosure, the original configuration code is the configuration code stored in the configuration memory of the satellite-borne FPGA, that is, the configuration code to be replaced.

In the embodiment of the present disclosure, the original pairing code further includes a backup pairing code stored in another location.

In the embodiment of the present disclosure, the difference matching code is a byte record whose xor result is not 0.

In the embodiment of the present disclosure, the format of the differential code matching is: the address add-or result.

In the embodiment of the present disclosure, in step S3, the difference configuration code is transmitted to the difference code storage area in the on-board FPGA configuration memory through ground-rail communication.

In the embodiment of the present disclosure, the mode of storing the difference code into the difference code storage area is to write the difference code into the storage array or to store the difference code into the cache area.

In the embodiment of the present disclosure, the differential parity stored in the buffer is lost after power failure.

In the embodiment of the present disclosure, the method for implementing on-track FPGA reconfiguration without erasing/writing according to the difference of claim 1, step S4, includes:

substep S41: the storage controller can simultaneously read the original codes of the original code storage area and the differential codes of the differential code storage area in the satellite-borne FPGA configuration storage;

substep S42: when reading the byte with the same address as the differential configuration code, carrying out read-back decoding on the byte according to the XOR result to obtain a new configuration code; and

substep S43: and transmitting the new configuration code to the FPGA through a configuration interface to complete the reconfiguration of the FPGA.

(III) advantageous effects

According to the technical scheme, the method for realizing the on-track reconfiguration of the erasable-free FPGA has at least one or part of the following beneficial effects:

(1) the original configuration code does not need to be modified, so that the time required by the erasing and writing processes of the storage array on the track is saved;

(2) the erasing operation of the memory is effectively avoided, and the stability of the system is greatly improved.

Drawings

Fig. 1 is a schematic flow chart of an on-track reconfiguration implementation method of an FPGA with write-and-erase injection exemption according to the difference of the embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a reconstruction path of an on-track FPGA reconfiguration implementation method with erasure-free injection in difference according to an embodiment of the present disclosure.

Detailed Description

The invention provides a difference injection erasing-free FPGA (field programmable gate array) on-track reconstruction implementation method, which adopts a difference injection mode to reduce distributed data transmitted on-track to 0.3% -1.8% of the original data. The read-back decoding mode can dynamically modify the read matched data according to the difference matched codes in the process of configuring the FPGA, so that the matched codes output to the FPGA are new matched codes, erasing operation on the storage array is avoided, and the time of on-track reconstruction is greatly saved.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

In an embodiment of the present disclosure, a method for implementing on-rail reconstruction of an FPGA without erasing and writing in difference is provided, which is shown in fig. 1 to 2, and includes:

in the embodiment of the present disclosure, the original configuration code is the configuration code stored in the configuration memory of the satellite-borne FPGA, that is, the configuration code to be replaced, and may also be the backup configuration code stored in other positions and having a different address from the replacement configuration code. The method mainly aims at that the original configuration code and the new configuration code are completely the same in data quantity, most of data are the same, only a small part of byte data are different, byte records with the exclusive OR result not being 0 are recorded through exclusive OR processing and are transmitted to an orbit satellite as the difference configuration code. As shown in table 1 below, the principle of the method for obtaining the xor result by performing xor processing on the original configuration code and the new configuration code is as follows:

address information	00	01	02	03	04	05
							Original matching code	00	32	02	31	40	20
New code	00	31	02	30	40	20
							XOR result	00	03	00	01	00	00

Table 1

Because the differential code matching format is as follows: address + xor result. The difference codes obtained after the xor processing are shown in table 2 below:

table 2

The address refers to a complete address or a partial address corresponding to the difference byte in the memory, and the address only needs to be correctly mapped to a configuration position needing to be updated during decoding.

step S3: storing the difference configuration code into a satellite-borne FPGA configuration memory;

in the ground-rail transmission stage, the difference configuration codes are transmitted to a difference code storage area in a satellite-borne FPGA configuration memory through ground-rail communication; the data may be written to the memory array or saved to a cache area. The difference is that the differential code stored in the buffer is lost after power failure.

The data saving process means that if the difference code is saved in the memory array, the memory array needs to be erased and written. The erase and write process for the memory array may be omitted if only the differential data is saved to the cache.

Step S4: and refreshing and configuring the FPGA through a storage controller to complete the on-track reconstruction of the FPGA with the difference injection and erasing-free performance. Step S4, including:

substep S41: the storage controller can simultaneously read the original codes of the original code storage area and the difference codes of the difference code storage area in the satellite-borne FPGA configuration storage;

substep S42: when reading the byte with the same address as the differential configuration code, carrying out read-back decoding on the byte according to the XOR result to obtain a new configuration code;

in the embodiment of the present disclosure, the new configuration code may be obtained by decoding the address information, the original configuration code, and the xor result (negating the original configuration code corresponding to the bit with the xor result of 1) in the following table 3:

address information	00	01	02	03	04	05
							Original matching code	00	32	02	31	40	20
XOR result	00	03	00	01	00	00
							New code	00	31	02	30	40	20

Table 3

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

Based on the above description, those skilled in the art should clearly recognize that the implementation method of on-rail reconfiguration of FPGA is exempt from erasing and writing in the difference of the present disclosure.

In summary, the present disclosure provides a method for implementing on-track FPGA reconfiguration without erasing and writing on a difference, which is to output configuration codes through dynamic refreshing of the difference configuration codes in the FPGA configuration process, without modifying the original configuration codes, thereby saving processes of erasing and writing on a storage array on a track. Erasing and writing to the memory array often takes a lot of time, and the on-board device has a limited boot time or operating time. In addition, the erasing process of the chip is usually accompanied by large voltage and large current, and the chip is damaged or a system fault may occur due to long-time erasing of the chip in consideration of the unstable environment of the outer space. The method effectively avoids erasing operation on the satellite-borne FPGA configuration memory, and greatly improves the stability of the system.

It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.

And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. An on-track reconstruction implementation method of a differentially injection erasure-free FPGA (field programmable gate array), comprising the following steps of:

2. The on-track FPGA reconfiguration realization method of claim 1, wherein the original configuration code is the configuration code stored in the on-board FPGA configuration memory, namely the configuration code to be replaced.

3. The method of claim 1, wherein the original configuration code further comprises backup configuration code stored elsewhere.

4. The method of claim 1, wherein the difference parity is a byte record with an XOR result different from 0.

5. The method of claim 1, wherein the delta code format is: the address add-or result.

6. The method for realizing on-track reconfiguration of a differentially injection-erasable FPGA according to claim 1, wherein in step S3, the differential configuration code is transmitted to a differential code storage area in a configuration memory of the on-board FPGA through ground-track communication.

7. The method of claim 5, wherein the difference write-once FPGA on-track reconfiguration is stored in the difference code storage area by programming the FPGA on the memory array or by saving the FPGA on the buffer area.

8. The method of claim 6, wherein the difference code stored in the buffer is lost after power down.

9. The method for implementing on-track reconfiguration of a differentially injection-erasable FPGA according to claim 1, wherein the step S4 includes: