CN111309482A - Ore machine controller task distribution system, device and storable medium thereof - Google Patents
Ore machine controller task distribution system, device and storable medium thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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Abstract
The application discloses ore machine controller task distribution system, device and storable medium thereof includes: the task receiving unit is used for receiving task data through the CPU interface control module; the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of a corresponding channel; the task sending unit is used for acquiring task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task data is located; and the task output unit is used for receiving the task calculation result and writing the task calculation result into the memory of the corresponding port after each downlink port receives the data of the task sending unit, and acquiring the task calculation result in each memory as output content in a polling mode. In the embodiment of the application, by using the memory structure in the system, as long as the internal memory has the allowance, the task receiving and sending of a single channel can be simultaneously carried out, the waiting time of a CPU is reduced, and the work efficiency of the task issuing of the CPU is increased.
Description
Technical Field
The application relates to the technical field of software task allocation, in particular to an ore machine controller task allocation system, an ore machine controller task allocation device and a storable medium of the ore machine controller task allocation device.
Background
The blockchain is a novel application mode of computer technologies such as distributed data storage, point-to-point transmission, a consensus mechanism and an encryption algorithm. The block chain mining machine is a tool for performing fast hash calculation on a block chain; the mining machine controller is a control device for sending block chain calculation tasks and receiving calculation results.
In the prior art, for task allocation, especially in the process of allocating a large number of tasks, a large number of processes of a CPU are occupied, which easily causes the situation that the sending is not timely and even the background computing task is wrong.
Disclosure of Invention
In order to solve the technical problem, the embodiment of the application provides an ore controller task distribution system, an ore controller task distribution device and a storable medium thereof.
A first aspect of an embodiment of the present application provides a mining machine controller task allocation system, which may include:
the task receiving unit is used for receiving task data through the CPU interface control module;
the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of a corresponding channel;
the task sending unit is used for acquiring task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task data is located;
and the task output unit is used for receiving the task calculation result and writing the task calculation result into the memory of the corresponding port after each downlink port receives the data of the task sending unit, and acquiring the task calculation result in each memory as output content in a polling mode.
Furthermore, a plurality of attribution channels are arranged, and each attribution channel is provided with a memory unit;
the memory unit is used for storing task contents and slicing the memory of the corresponding channel according to the number of bytes of the task.
Further, when the memory unit is partitioned, a single task command does not exceed n bytes, the memory is divided into m chip select addresses, each chip has n bytes, and the memory space is allocated to m x n.
Further, each slice of the slice selection address comprises:
an address sequence number unit;
the storage address unit corresponds to the address serial number unit;
and a task content unit having task content therein and corresponding to the storage address unit.
Further, in the memory address unit, the sending mode of the command is stored in the memory address 0, the length of the command is stored in the memory address 1, and the contents of tasks are stored in other addresses.
Further, the task sending unit includes:
the updating unit reads the stored task data through the control module and distributes, sends and updates the tasks of the current address block;
the sending mode unit is used for sending task contents and comprises a single sending mode unit and an N _ TIME sending mode unit; the single-sending mode unit limits the task to be sent only once; the N _ TIME send mode element defines that this task needs to be sent N TIMEs.
Further, the single-sending mode unit sends the address sequence number unit which is read after one-time sending is completed plus 1, and then sends the task of the next address sequence number unit.
Further, when the N _ TIME sending mode unit sends a task each TIME, it determines whether recalculation is needed, if recalculation is needed, it replaces the specific byte of the task, adds 1 to the address sequence number unit read after sending N TIMEs, and then sends the task of the next address sequence number unit, otherwise, it sends directly.
In a second aspect, an embodiment of the present application provides an ore machine controller task allocation apparatus, including a memory and a processor, where the memory stores computer-executable instructions, and the processor implements the system of the first aspect when executing the computer-executable instructions on the memory.
In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the system of the first aspect is implemented.
In the embodiment of the application, by using the memory structure in the system, as long as the internal memory has the allowance, the task receiving and sending of a single channel can be simultaneously carried out, the waiting time of a CPU is reduced, and the work efficiency of the task issuing of the CPU is increased.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a system provided by an embodiment of the present application;
FIG. 2 is a flow chart of a system provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of memory allocation;
FIG. 4 is a flowchart of a task sending unit;
FIG. 5 is a task send byte processing flow diagram;
fig. 6 is a schematic structural diagram of a dispensing device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The application provides an implementation method for task allocation of an ore machine controller based on an FPGA (field programmable gate array). the whole method comprises four parts, namely task receiving, task storage and allocation, task sending and task calculation result receiving and returning.
The FPGA receives task data through a CPU interface control module, judges a task attribution channel through the control module and writes the task attribution channel into a memory of a corresponding channel; each channel sending module reads task data in a corresponding memory and sends the task data to a corresponding downlink port according to the sending module; and each downlink port receives the task calculation result and writes the task calculation result into the memory of the corresponding port, and the CPU reads the task calculation result in each memory in a polling mode through the CPU interface control module.
To implement the above method, as shown in fig. 1, embodiments of the present application provide an ore controller task allocation system comprising: a task receiving unit 310, a task storage unit 320, a task sending unit 330, and a task output unit 340.
The task receiving unit 310 is configured to receive task data through the CPU interface control module by using the FPGA.
The task storage unit 320 is configured to determine a channel to which the task belongs through the control module, and write the channel into the memory of the corresponding channel.
In the whole system, a plurality of attribution channels are arranged, and each attribution channel is provided with a memory unit. And the memory unit is used for storing task contents and slicing the memory of the corresponding channel according to the number of bytes of the task.
Specifically, when the memory unit is partitioned, a single task command does not exceed n bytes, the memory is divided into m chip select addresses, each chip has n bytes, and the memory space is allocated to m x n.
As shown in fig. 3, each chip select address includes:
an address sequence number unit 321;
a storage address unit 322 corresponding to the address number unit;
the memory address 0 stores the sending mode and the sending times of the command, the memory address 1 stores the length of the command, and other addresses of the memory address store the content of the task.
Task content section 323 contains task content and corresponds to storage address section 322.
As long as the structure is used, the task receiving and sending of a single channel can be carried out simultaneously, the waiting time of the CPU is reduced, and the work efficiency of the task issuing of the CPU is increased.
After receiving the task data, the task storage unit 320 needs to select the corresponding channel and the chip select address corresponding to the channel according to the received content.
The task sending unit 330 is configured to obtain task data in a corresponding memory, and send the task data to a corresponding downlink port according to a sending module where the task data is located.
As a specific embodiment, the task sending unit 330 is provided with an updating unit 331 for reading the stored task data through the control module and performing allocation sending updating on the task of the current address block;
a transmission mode unit 332 for transmitting task content, including a single transmission mode unit and an N _ TIME transmission mode unit; the single sending mode unit limits the task to be sent only once, the single sending mode unit adds 1 to the address sequence number unit read after sending the completion once, and then sends the task of the next address sequence number unit.
The N _ TIME sending mode unit limits that the task needs to be sent for N TIMEs, judges whether recalculation is needed or not when the N _ TIME sending mode unit sends the task each TIME, replaces specific bytes of the task if recalculation is needed, adds 1 to an address sequence number unit read after the sending is completed for N TIMEs, and then sends the task of the next address sequence number unit, otherwise, directly sends the task.
The sending task is generated by the FPGA through a specific algorithm based on the initial task and is sent to the downlink chip, and each task does not need to be sent to the FPGA by a CPU and then sent to the downlink chip by the FPGA; the mode accelerates the task allocation and sending, simultaneously releases the CPU process, greatly reduces the sending time of the tasks under the condition of N channels, and avoids the calculation error and repeated calculation caused by the overtime of the task sending of the downlink calculation chip, thereby influencing the efficiency; meanwhile, the time for receiving and processing the task calculation result by the CPU is also increased, and the condition that the task result is lost due to insufficient time for processing the calculation result is avoided;
the task output unit 340 is configured to receive the task calculation result and write the task calculation result into the memory of the corresponding port after each downlink port receives the task sending unit data, and obtain the task calculation result in each memory as output content in a polling mode.
Fig. 6 is a schematic structural diagram of a dispensing device according to an embodiment of the present application. The object detection apparatus 4000 comprises a processor 41 and may further comprise an input device 42, an output device 43 and a memory 44. The input device 42, the output device 43, the memory 44, and the processor 41 are connected to each other via a bus.
The memory includes, but is not limited to, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), which is used for storing instructions and data.
The input means are for inputting data and/or signals and the output means are for outputting data and/or signals. The output means and the input means may be separate devices or may be an integral device.
The processor may include one or more processors, for example, one or more Central Processing Units (CPUs), and in the case of one CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor may also include one or more special purpose processors, which may include GPUs, FPGAs, etc., for accelerated processing.
The memory is used to store program codes and data of the network device.
The processor is used for calling the program codes and data in the memory and executing the steps in the method embodiment. Specifically, reference may be made to the description of the method embodiment, which is not repeated herein.
It will be appreciated that fig. 6 only shows a simplified design of the object detection device. In practical applications, the motion recognition devices may also respectively include other necessary components, including but not limited to any number of input/output devices, processors, controllers, memories, etc., and all motion recognition devices that can implement the embodiments of the present application are within the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the division of the unit is only one logical function division, and other division may be implemented in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. The shown or discussed mutual coupling, direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are wholly or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on or transmitted over a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)), or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The usable medium may be a read-only memory (ROM), or a Random Access Memory (RAM), or a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape, a magnetic disk, or an optical medium, such as a Digital Versatile Disk (DVD), or a semiconductor medium, such as a Solid State Disk (SSD).
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and the equivalents are protected by the present invention.
Claims (10)
1. A mining machine controller task allocation system, comprising:
the task receiving unit is used for receiving task data through the CPU interface control module;
the task storage unit is used for judging a task attribution channel through the control module and writing the task attribution channel into a memory of a corresponding channel;
the task sending unit is used for acquiring task data in the corresponding memory and sending the task data to the corresponding downlink port according to the sending module where the task data is located;
and the task output unit is used for receiving the task calculation result and writing the task calculation result into the memory of the corresponding port after each downlink port receives the data of the task sending unit, and acquiring the task calculation result in each memory as output content in a polling mode.
2. A ore controller task distribution system as claimed in claim 1,
the number of the attribution channels is multiple, and each attribution channel is provided with a memory unit;
the memory unit is used for storing task contents and slicing the memory of the corresponding channel according to the number of bytes of the task.
3. A ore controller task distribution system as claimed in claim 2,
when the memory unit is partitioned, a single task command does not exceed n bytes, the memory is divided into m chip selection addresses, and the memory space is allocated to m x n in each n bytes.
4. A ore controller task distribution system as claimed in claim 3,
each piece of the chip selection address comprises:
an address sequence number unit;
the storage address unit corresponds to the address serial number unit;
and a task content unit having task content therein and corresponding to the storage address unit.
5. A ore controller task distribution system as claimed in claim 4,
in the memory address unit, the sending mode of the command is stored in the memory address 0, the length of the command is stored in the memory address 1, and the content of tasks is stored in other addresses.
6. A ore controller task distribution system as claimed in claim 2,
the task sending unit includes:
the updating unit reads the stored task data through the control module and distributes, sends and updates the tasks of the current address block;
the sending mode unit is used for sending task contents and comprises a single sending mode unit and an N _ TIME sending mode unit; the single-sending mode unit limits the task to be sent only once; the N _ TIME send mode element defines that this task needs to be sent N TIMEs.
7. A ore controller task distribution system as claimed in claim 6,
and the single-time sending mode unit sends the address sequence number unit which is read after one time of sending plus 1 and then sends the task of the next address sequence number unit.
8. A ore controller task distribution system as claimed in claim 6,
and the N _ TIME sending mode unit judges whether recalculation is needed or not when sending the task every TIME, if the recalculation is needed, a specific byte of the task is replaced, the address sequence number unit which is read after sending is finished for N TIMEs is added with 1, and then the task of the next address sequence number unit is sent, otherwise, the task is directly sent.
9. A mining machine controller task allocation apparatus comprising a memory having stored thereon computer executable instructions and a processor which when executing the computer executable instructions on the memory implements the system of any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the system of any one of the preceding claims 1 to 8.
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| CN202010110301.5A CN111309482B (en) | 2020-02-20 | 2020-02-20 | Hash algorithm-based block chain task allocation system, device and storable medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111817838A (en) * | 2020-07-16 | 2020-10-23 | 浙江亿邦通信科技有限公司 | Data cross processing system and method thereof |
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