CN111294035A - Level selection circuit, level selection method, chip and electronic equipment - Google Patents

Level selection circuit, level selection method, chip and electronic equipment Download PDF

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CN111294035A
CN111294035A CN202010074441.1A CN202010074441A CN111294035A CN 111294035 A CN111294035 A CN 111294035A CN 202010074441 A CN202010074441 A CN 202010074441A CN 111294035 A CN111294035 A CN 111294035A
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level
selection
mos tube
level signal
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CN111294035B (en
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余东升
何永强
刘珍超
李念龙
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Wuxi Aiwei Integrated Circuit Technology Co Ltd
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Wuxi Aiwei Integrated Circuit Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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Abstract

The invention provides a level selection circuit, a level selection method, a chip and electronic equipment, wherein when a first level signal and a second level signal meet a first preset condition, a first selection branch circuit is conducted, a signal selection module outputs a first intermediate signal, and a signal transmission module converts the first intermediate signal into a first level signal; when the first level signal and the second level signal meet a second preset condition, the second selection branch is conducted, the signal selection module outputs a second intermediate signal, and the signal transmission module converts the second intermediate signal into a second level signal; when the first preset condition is switched to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, and the signal transmission module converts the third intermediate signal into a level transition signal. Since the level transition signal has a linear relationship with the first level signal and the second level signal, smooth switching of the first level signal and the second level signal can be achieved.

Description

Level selection circuit, level selection method, chip and electronic equipment
Technical Field
The present invention relates to the field of analog circuit technologies, and in particular, to a level selection circuit, a level selection method, a chip, and an electronic device.
Background
Analog circuits have found wide application in signal transmission, where comparison of signals at different levels is most common. For example, the level selection circuit compares signals with different levels, for example, two level signals, and then transfers the level signal satisfying a predetermined level condition (e.g., the highest or the lowest level) to the next module or chip for processing. However, when the conventional level selection circuit switches between two level signals satisfying the preset level condition, it is difficult to realize smooth switching of the level signals.
Disclosure of Invention
In view of the above, the present invention provides a level selection circuit, a level selection method, a chip and an electronic device, so as to solve the problem that level signals cannot be smoothly switched.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a level selection circuit comprises a signal selection module and a signal transmission module connected with the signal selection module;
the signal selection module comprises a plurality of parallel selection branches, control ends of the plurality of selection branches are connected with a plurality of signal input ends in a one-to-one correspondence mode, the plurality of signal input ends at least comprise a first signal input end and a second signal input end, a first level signal is input into the first signal input end, and a second level signal is input into the second signal input end;
the plurality of selection branches at least comprise a first selection branch and a second selection branch, the control end of the first selection branch is connected with the first signal input end, and the control end of the second selection branch is connected with the second signal input end;
when the first level signal and the second level signal meet a first preset condition, the first selection branch circuit is conducted, the signal selection module outputs a first intermediate signal, and the first intermediate signal and the first level signal have a linear relation;
when the first level signal and the second level signal meet a second preset condition, the second selection branch is conducted, the signal selection module outputs a second intermediate signal, and the second intermediate signal and the second level signal have a linear relation;
in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, and the third intermediate signal has a linear relationship with the first level signal and the second level signal;
the signal transmission module is used for converting the first intermediate signal into a first level signal and outputting the first level signal when the signal selection module outputs the first intermediate signal, converting the second intermediate signal into a second level signal and outputting the second level signal when the signal selection module outputs the second intermediate signal, and converting the third intermediate signal into a level transition signal and outputting the level transition signal when the signal selection module outputs the third intermediate signal, wherein the level transition signal has a linear relation with the first level signal and the second level signal.
Optionally, the selection branch comprises a first MOS transistor, and the signal selection module further comprises a first current source and a first output end;
the grid electrode of each first MOS tube is connected with one signal input end;
the first ends of all the first MOS tubes are connected, the second ends of all the first MOS tubes are connected, the first ends are grounded, and the second ends are connected with the first output end;
the input end of the first current source is connected with a power supply end, and the output end of the first current source is connected with the first output end.
Optionally, the signal transmission module includes a second current source, a third current source, a fourth current source, a first resistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second input terminal, and a second output terminal;
the second input end is connected with the first output end, the second input end is connected with the grid electrode of the second MOS tube, the first end of the second MOS tube is connected with the second end of the third MOS tube, the second end of the second MOS tube is connected with the input end of the second current source, and the output end of the second current source is grounded; the first end of the third MOS tube is connected with a power supply end, the second end of the third MOS tube is connected with the grid electrode of the third MOS tube, the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the first end of the fourth MOS tube is connected with the power supply end, the second end of the fourth MOS tube is connected with the input end of the third current source, and the output end of the third current source is grounded;
a first end of the fifth MOS tube is connected with the power supply end, a second end of the fifth MOS tube is connected with a second end of the second MOS tube, a grid electrode of the fifth MOS tube is connected with an output end of the fourth current source, and an input end of the fourth current source is connected with the power supply end;
the grid electrode of the fifth MOS tube is connected with the first end of the sixth MOS tube, the second end of the sixth MOS tube is grounded, the grid electrode of the sixth MOS tube is connected with the first end of the first resistor, the second end of the first resistor is grounded, and the second output end of the first MOS tube is connected with the grid electrode of the sixth MOS tube;
the second end of the seventh MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the seventh MOS tube is connected with the second end of the fourth MOS tube, the first end of the seventh MOS tube is connected with the second end of the eighth MOS tube, the first end of the eighth MOS tube is connected with the power supply end, and the second end of the eighth MOS tube is connected with the grid electrode of the eighth MOS tube.
Optionally, the width-to-length ratios of the first MOS transistor and the sixth MOS transistor are the same;
the width-length ratio of the second MOS tube is the same as that of the fifth MOS tube;
the width-length ratio of the third MOS tube is the same as that of the fourth MOS tube.
Optionally, the first MOS transistor is a PMOS transistor;
when the level of the first level signal is less than a first threshold level and the level of the second level signal is greater than the first threshold level, the first level signal and the second level signal meet a first preset condition;
when the level of the first level signal is greater than the first threshold level and the level of the second level signal is less than the first threshold level, the first level signal and the second level signal meet a second preset condition, and the first threshold level is the conduction level of the PMOS transistor.
Optionally, the first MOS transistor is an NMOS transistor;
when the level of the first level signal is greater than a second threshold level and the level of the second level signal is less than the second threshold level, the first level signal and the second level signal meet a first preset condition;
when the level of the first level signal is smaller than the second threshold level and the level of the second level signal is greater than the second threshold level, the first level signal and the second level signal meet a second preset condition, and the second threshold level is the conduction level of the NMOS transistor.
Optionally, the second MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are NMOS transistors, and the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are PMOS transistors.
A level selection chip comprising a level selection circuit as claimed in any one of the preceding claims.
An electronic device comprising a level selecting chip as described above.
A method of level selection, comprising:
receiving a plurality of input level signals, wherein the plurality of level signals at least comprise a first level signal and a second level signal;
when the first level signal and the second level signal meet a first preset condition, a first selection branch circuit is conducted, a signal selection module outputs a first intermediate signal, and a signal transmission module converts the first intermediate signal into a first level signal and outputs the first level signal;
when the first level signal and the second level signal meet a second preset condition, a second selection branch circuit is conducted, a signal selection module outputs a second intermediate signal, and a signal transmission module converts the second intermediate signal into a second level signal and outputs the second level signal;
in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, the signal transmission module converts the third intermediate signal into a level transition signal and outputs the level transition signal, and the level transition signal has a linear relationship with the first level signal and the second level signal.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the level selection circuit, the level selection method, the chip and the electronic device, when the first level signal and the second level signal meet the first preset condition, the signal selection module outputs the first intermediate signal, and the signal transmission module can obtain and output the first level signal according to the first intermediate signal because the first intermediate signal and the first level signal have a linear relation signal input end; when the first level signal and the second level signal meet a second preset condition, the signal selection module outputs a second intermediate signal, and the second intermediate signal and the second level signal have a linear relation, so that the signal transmission module can obtain and output the second level signal according to the second intermediate signal; in the process of switching the first preset condition to the second preset condition, the signal selection module outputs a third intermediate signal, and since the third intermediate signal has a linear relationship with the first level signal and the second level signal, the signal transmission module can obtain and output a level transition signal according to the third intermediate signal, and since the level transition signal has a linear relationship with the first level signal and the second level signal, smooth switching of the first level signal and the second level signal can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a conventional level selection circuit;
FIG. 2 is a signal waveform diagram of the level selection circuit shown in FIG. 1;
fig. 3 is a schematic structural diagram of a level selection circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a level selection circuit according to another embodiment of the present invention;
FIG. 5 is a signal waveform diagram of a level selection circuit according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating a level selection method according to an embodiment of the present invention.
Detailed Description
As described in the background art, when switching between two level signals satisfying a predetermined level condition in the prior art, it is difficult to achieve smooth switching of the level signals. As shown in fig. 1, a conventional level selection circuit includes a level signal line VA, a level signal line VB, a comparator, and a single-pole double-set switch S1And a level signal line VY having a level signal V on a level signal line VAAThe level signal on the level signal line VB is VB。
When V isA≥VBThe comparator outputs high level, the single-pole double-set switch S1A level signal line VY connected to a level signal line VA for outputting a level signal VA(ii) a When V isA＜VBThe comparator outputs low level, single-pole double-set switch S1Will level informationThe signal line VY is connected to a level signal line VB, and the level signal line VY outputs a level signal VB。
However, the inventor has found that, as shown in fig. 2, most of the signals output by the level signal line VY are V, because the comparator itself has a large mismatch, that is, the comparator cannot realize complete symmetry between the input pair transistor and the symmetric branch circuitY1And VY2In both cases, i.e. at level signal VASum level signal VBHas a step, that is, the signal on the level signal line VY is at the level signal VASum level signal VBWhen switching between them, smooth switching cannot be realized.
Based on this, the invention provides a level selection circuit, a level selection method, a chip and an electronic device, so as to overcome the above problems in the prior art, wherein the level selection circuit comprises a signal selection module and a signal transmission module connected with the signal selection module;
the signal selection module comprises a plurality of parallel selection branches, control ends of the plurality of selection branches are connected with a plurality of signal input ends in a one-to-one correspondence mode, the plurality of signal input ends at least comprise a first signal input end and a second signal input end, a first level signal is input into the first signal input end, and a second level signal is input into the second signal input end;
the plurality of selection branches comprise a first selection branch and a second selection branch, the control end of the first selection branch is connected with the first signal input end, and the control end of the second selection branch is connected with the second signal input end;
when the first level signal and the second level signal meet a first preset condition, the first selection branch circuit is conducted, the signal selection module outputs a first intermediate signal, and the first intermediate signal and the first level signal have a linear relation;
when the first level signal and the second level signal meet a second preset condition, the second selection branch is conducted, the signal selection module outputs a second intermediate signal, and the second intermediate signal and the second level signal have a linear relation;
in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, and the third intermediate signal has a linear relationship with the first level signal and the second level signal;
the signal transmission module is used for converting the first intermediate signal into a first level signal and outputting the first level signal when the signal selection module outputs the first intermediate signal, converting the second intermediate signal into a second level signal and outputting the second level signal when the signal selection module outputs the second intermediate signal, and converting the third intermediate signal into a level transition signal and outputting the level transition signal when the signal selection module outputs the third intermediate signal, wherein the level transition signal has a linear relation with the first level signal and the second level signal.
According to the level selection circuit, the chip and the electronic device, the level transition signal has a linear relation with the first level signal and the second level signal, so that smooth switching of the first level signal and the second level signal can be achieved through the level transition signal.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a level selection circuit, configured to select a level signal and implement smooth switching between different level signals, as shown in fig. 3, where the level selection circuit includes a signal selection module 10 and a signal selection moduleThe signal selection module 10 comprises a plurality of parallel selection branches, and control ends of the plurality of selection branches are connected with the plurality of signal input ends in a one-to-one correspondence manner. The multiple signal input terminals at least comprise a first signal input terminal and a second signal input terminal, the first signal input terminal inputs a first level signal VAA second signal input terminal for inputting a second level signal VB。
The plurality of selection branches at least comprise a first selection branch 101a and a second selection branch 101b, the control end of the first selection branch 101a is connected with the first signal input end, and the control end of the second selection branch 101b is connected with the second signal input end;
when the first level signal VAAnd a second level signal VBWhen a first preset condition is satisfied, the first selection branch 101a is turned on, and the signal selection module 10 outputs a first intermediate signal, a first intermediate signal and a first level signal VAHas a linear relationship;
when the first level signal VAAnd a second level signal VBWhen the second preset condition is satisfied, the second selection branch 101b is turned on, and the signal selection module 10 outputs a second intermediate signal, the second intermediate signal and the second level signal VBHas a linear relationship;
in the process of switching the first preset condition to the second preset condition, the first selection branch 101a and the second selection branch 101b are turned on, and the signal selection module 10 outputs a third intermediate signal, the third intermediate signal and the first level signal VAAnd a second level signal VBHas a linear relationship;
the signal transmission module 11 is configured to convert the first intermediate signal into a first level signal V when the signal selection module 10 outputs the first intermediate signalAAnd outputs a first level signal VAWhen the signal selection module 10 outputs the second intermediate signal, the second intermediate signal is converted into a second level signal VBAnd outputs a second level signal VBWhen the signal selection module 10 outputs the third intermediate signal, the third intermediate signal is converted into a level transition signal, and the level transition signal, the level transition signal and the first signal are outputFlat signal VAAnd a second level signal VBHas a linear relationship.
That is, when the first level signal V is appliedAAnd a second level signal VBWhen the first preset condition is satisfied, the signal selection module 10 outputs the first intermediate signal, because the first intermediate signal and the first level signal VAHas a linear relationship with the signal input terminal, so that the signal transmission module 11 can obtain and output the first level signal V according to the first intermediate signalA(ii) a When the first level signal VAAnd a second level signal VBWhen the second preset condition is satisfied, the signal selection module 10 outputs the second intermediate signal, because the second intermediate signal and the second level signal VBHas a linear relationship, so that the signal transmission module 11 can obtain and output the second level signal V according to the second intermediate signalB(ii) a In the process of switching the first preset condition to the second preset condition, the signal selection module 10 outputs the third intermediate signal, which is the third intermediate signal and the first level signal VAAnd a second level signal VBHas a linear relationship, so that the signal transmission module 11 can obtain and output a level transition signal according to the third intermediate signal, since the level transition signal is in accordance with the first level signal VAAnd a second level signal VBHas a linear relationship, so that the first level signal V can be realizedAAnd a second level signal VBSmooth handover of the mobile terminal.
In addition, in the embodiment of the present invention, the comparator is not used for selecting the level signal, but the plurality of parallel selection branches are used for selecting the level signal, and any two selection branches of the plurality of selection branches are the same, that is, the selection branches are symmetrically arranged, so that the mismatch of the signal selection module 10 is small, and the first level signal V can be output in the process of switching the first preset condition to the second preset conditionAAnd a second level signal VBA level transition signal having a linear relationship so that a smooth switching between two level signals can be achieved.
In an embodiment of the present invention, as shown in fig. 4, each of the selection branches has a first MOS transistor, and each of the selection branches has the same first MOS transistor, for example, the first selection branch 101a has a first MOS transistor M1A, the second selection branch 101b has a first MOS transistor M1B, and the signal selection module 10 has two selection branches as an example in fig. 4, which is not limited thereto, and the signal selection module 10 further includes a first current source Y1 and a first output terminal.
The gate of each first MOS transistor is connected to a signal input terminal, for example, the gate of the first MOS transistor M1A is connected to the first signal input terminal, and the level signal at the first signal input terminal is the first level signal VAThe grid of the first MOS transistor M1B is connected to a second signal input terminal, and the level signal at the second signal input terminal is a second level signal VB(ii) a The first ends of all the first MOS tubes are connected, the second ends of all the first MOS tubes are connected, the first ends are grounded GND, and the second ends are connected with the first output end; an input terminal of the first current source Y1 is connected to the power supply terminal VDD, and an output terminal of the first current source Y1 is connected to the first output terminal.
As shown in fig. 4, the signal transmission module 11 includes a second current source Y2, a third current source Y3, a fourth current source Y4, a first resistor R1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a second input terminal, and a second output terminal.
The second input end is connected with the first output end, the second input end is connected with the grid of the second MOS tube M2, the first end of the second MOS tube M2 is connected with the second end of the third MOS tube M3, the second end of the second MOS tube M2 is connected with the input end of a second current source Y2, and the output end of the second current source Y2 is grounded;
the first end of the third MOS tube M3 is connected with a power supply end VDD, the second end of the third MOS tube M3 is connected with the grid electrode of the third MOS tube M3, the grid electrode of the third MOS tube M3 is connected with the grid electrode of the fourth MOS tube M4, the first end of the fourth MOS tube M4 is connected with the power supply end VDD, the second end of the fourth MOS tube M4 is connected with the input end of a third current source Y3, and the output end of the third current source Y3 is grounded;
a first end of the fifth MOS transistor M5 is connected to the power supply terminal VDD, a second end of the fifth MOS transistor M5 is connected to a second end of the second MOS transistor M2, a gate of the fifth MOS transistor M5 is connected to an output end of the fourth current source Y4, and an input end of the fourth current source Y4 is connected to the power supply terminal VDD;
the grid electrode of the fifth MOS tube M5 is connected with the first end of the sixth MOS tube M6, the second end of the sixth MOS tube M6 is grounded, the grid electrode of the sixth MOS tube M6 is connected with the first end of the first resistor R1, the second end of the first resistor R1 is grounded, and the second output end of the sixth MOS tube M6 is connected with the grid electrode of the sixth MOS tube M6;
the second end of the seventh MOS transistor M7 is connected to the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7 is connected to the second end of the fourth MOS transistor M4, the first end of the seventh MOS transistor M7 is connected to the second end of the eighth MOS transistor M8, the first end of the eighth MOS transistor M8 is connected to the power supply terminal VDD, and the second end of the eighth MOS transistor M8 is connected to the gate of the eighth MOS transistor M8.
The width-length ratios of the first MOS transistor M1 and the sixth MOS transistor M6 are the same; the width-length ratios of the second MOS transistor M2 and the fifth MOS transistor M5 are the same; the width-to-length ratios of the third MOS transistor M3 and the fourth MOS transistor M4 are the same.
In the embodiment of the present invention, the first MOS transistors, such as M1A and M1B, are PMOS transistors, the second MOS transistor M2, the fifth MOS transistor M5, and the seventh MOS transistor M7 are NMOS transistors, and the third MOS transistor M3, the fourth MOS transistor M4, the sixth MOS transistor M6, and the eighth MOS transistor M8 are PMOS transistors. And the first end of the MOS tube is a source electrode or a drain electrode, and the second end of the MOS tube is a drain electrode or a source electrode.
It should be noted that, when the first MOS transistor is a PMOS transistor, the first level signal V is set to be the first level signal VAIs less than a first threshold level, and a second level signal VBIs greater than a first threshold level, a first level signal VAAnd a second level signal VBMeeting a first preset condition; when the first level signal VAIs greater than a first threshold level, and a second level signal VBIs less than a first threshold level, a first level signal VAAnd a second level signal VBAnd the second preset condition is met, and the first threshold level is the conduction level of the PMOS tube.
Of course, the invention is not limited thereto, and in other embodiments, the first MOS transistors such as M1A and M1B may also be NMOS transistorsTube, and, at this time, when the first level signal VAIs greater than a second threshold level, and a second level signal VBIs less than the second threshold level, the first level signal VAAnd a second level signal VBMeeting a first preset condition; when the first level signal VAIs less than a second threshold level, and a second level signal VBIs greater than the second threshold level, the first level signal VAAnd a second level signal VBAnd a second threshold level is a conduction level signal of the NMOS tube when a second preset condition is met.
In the structure shown in FIG. 4, when VA<VTH<VBWhen the first level signal V is presentAAnd a second level signal VBWhen the first preset condition is satisfied, the first MOS transistor M1A is turned on, the first MOS transistor M1B is turned off, and at this time,
VC＝VA+VSG1(1)；
VY＝VC-VGS2+VGS5-VSG6(2)；
wherein, VCFor selecting the output signal, V, of the module 10YIs the output signal of the signal transmission module 11. Since the width-to-length ratios of the first MOS transistors M1A and M1B to the sixth MOS transistor M6 are the same, the currents flowing through the first MOS transistors M1A and M1B to the sixth MOS transistor M6 are the same, the width-to-length ratios of the second MOS transistor M2 to the fifth MOS transistor M5 are the same, and the currents flowing through the second MOS transistor M2 and the fifth MOS transistor M5 are the same, the channel modulation effect is ignored, and the saturation region current formula of the MOS transistors is combined
Figure BDA0002378129700000121
Therefore, the following steps are carried out: vSG6＝VSG1(4)、VGS2＝VGS5(5) Thus, V can be knownY＝VC-VSG6Due to VA＝VC-VSG6Thus, VY＝VAAt this time, the level signal output by the level selection circuit and the level signal V on the first MOS transistor M1AAThe same is true.
Wherein, munIs electricityMobility, CoxIs the gate oxide capacitance per unit area, W is the gate width of the MOS, L is the gate length of the MOS, VTHIs the turn-on threshold voltage, V, of the MOS transistorGS、VSGIs the gate-source voltage of the MOS transistor.
When V isA>VTH>VBTime, i.e. first level signal VAAnd a second level signal VBWhen the second preset condition is met, the first MOS transistor M1B is conducted, the first MOS transistor M1A is not conducted, and at the moment, V isC＝VB+VSG1，VY＝VC-VGS2+VGS5-VSG6Due to VSG6＝VSG1、VGS2＝VGS5Thus, VY＝VC-VSG6，VY＝VBAt this time, the level signal output by the level selection circuit and the level signal V on the first MOS transistor M1BBThe same is true.
When V isAAnd VBLevels are close and VAAnd VBAre all less than VTHIn the process of switching from the first preset condition to the second preset condition, the first MOS transistor M1B and the first MOS transistor M1A are turned on, and the branches of the first MOS transistor M1B and the first MOS transistor M1A have currents, and at this time, it can be seen from the above analysis that V is a current flowing through the branches of the first MOS transistor M1B and the first MOS transistor M1AY＝VC-VSG6Assuming that the current flowing through the first MOS transistor M1A is λ × I1, the current flowing through the first MOS transistor M1B is (1- λ) × I1, and the current flowing through the saturation region of the MOS transistor is obtained by combining the formula:
Figure BDA0002378129700000131
Figure BDA0002378129700000132
the following equations (6) and (7) yield:
Figure BDA0002378129700000133
wherein λ is between 0 and 1, so VCAnd VA、VBIs a first order linear relationship between, VYAnd VA、VBThere is also a first order linear relationship between, therefore, VYCan be realized at VAAnd VBTo smoothly switch between.
When level signal VBConstant, level signal VAGradually rising from low over level signal VBWhen, VYThe corresponding level signal changes are shown in FIG. 5. the level selection circuit compares the level signal VAAnd VBWhen a first preset condition, namely V, is satisfiedA<VTH<VBWhile outputting a higher level VBWhen a second preset condition, namely V, is satisfiedA>VTH>VBWhile outputting a higher level VADuring the switching between the first preset condition and the second preset condition, i.e. VAAnd VBLevels are close and VAAnd VBAre all less than VTHThen, the level transition signal is output to realize two level signals VAAnd VBTo smoothly switch between.
The embodiment of the invention also provides a level selection chip, which comprises the level selection circuit provided by any one of the above embodiments.
The embodiment of the invention also provides electronic equipment which comprises the level selection chip provided by the embodiment.
An embodiment of the present invention further provides a level selection method, as shown in fig. 6, applied to the level selection circuit described in any one of the above, where the method includes:
s101: receiving a plurality of input level signals, wherein the plurality of level signals at least comprise a first level signal and a second level signal;
s102: when the first level signal and the second level signal meet a first preset condition, the first selection branch circuit is conducted, the signal selection module outputs a first intermediate signal, and the signal transmission module converts the first intermediate signal into a first level signal and outputs the first level signal;
s103: when the first level signal and the second level signal meet a second preset condition, the second selection branch circuit is conducted, the signal selection module outputs a second intermediate signal, and the signal transmission module converts the second intermediate signal into a second level signal and outputs the second level signal;
s104: in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, the signal transmission module converts the third intermediate signal into a level transition signal and outputs the level transition signal, and the level transition signal has a linear relation with the first level signal and the second level signal.
That is, as shown in FIG. 3, when the first level signal V is appliedAAnd a second level signal VBWhen the first preset condition is satisfied, the signal selection module 10 outputs the first intermediate signal, because the first intermediate signal and the first level signal VAHas a linear relationship with the signal input terminal, so that the signal transmission module 11 can obtain and output the first level signal V according to the first intermediate signalAA signal input terminal; when the first level signal VAAnd a second level signal VBWhen the second preset condition is satisfied, the signal selection module 10 outputs the second intermediate signal, because the second intermediate signal and the second level signal VBHas a linear relationship, so that the signal transmission module 11 can obtain and output the second level signal V according to the second intermediate signalB(ii) a In the process of switching the first preset condition to the second preset condition, the signal selection module 10 outputs the third intermediate signal, which is the third intermediate signal and the first level signal VAAnd a second level signal VBHas a linear relationship, so that the signal transmission module 11 can obtain and output a level transition signal according to the third intermediate signal, since the level transition signal is in accordance with the first level signal VAAnd a second level signal VBHas a linear relationship, so that the first level signal V can be realizedAAnd a second level signal VBSmooth handover of the mobile terminal.
In addition, because the embodiment of the invention does not adopt a comparator to select the level signal, a plurality of parallel selections are adoptedThe branch circuit selects the level signal, and any two of the multiple selection branch circuits are the same, that is, the selection branch circuits are symmetrically arranged, so that the mismatch of the signal selection module 10 is small, and the signal selection module can output the first level signal V in the process of switching the first preset condition to the second preset conditionAAnd a second level signal VBThe level transition signal with linear relation, the signal input end of the signal input end can realize smooth switching between two level signals.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A level selection circuit is characterized by comprising a signal selection module and a signal transmission module connected with the signal selection module;
the signal selection module comprises a plurality of parallel selection branches, control ends of the plurality of selection branches are connected with a plurality of signal input ends in a one-to-one correspondence mode, the plurality of signal input ends at least comprise a first signal input end and a second signal input end, a first level signal is input into the first signal input end, and a second level signal is input into the second signal input end;
the plurality of selection branches at least comprise a first selection branch and a second selection branch, the control end of the first selection branch is connected with the first signal input end, and the control end of the second selection branch is connected with the second signal input end;
when the first level signal and the second level signal meet a first preset condition, the first selection branch circuit is conducted, the signal selection module outputs a first intermediate signal, and the first intermediate signal and the first level signal have a linear relation;
when the first level signal and the second level signal meet a second preset condition, the second selection branch is conducted, the signal selection module outputs a second intermediate signal, and the second intermediate signal and the second level signal have a linear relation;
in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, and the third intermediate signal has a linear relationship with the first level signal and the second level signal;
the signal transmission module is used for converting the first intermediate signal into a first level signal and outputting the first level signal when the signal selection module outputs the first intermediate signal, converting the second intermediate signal into a second level signal and outputting the second level signal when the signal selection module outputs the second intermediate signal, and converting the third intermediate signal into a level transition signal and outputting the level transition signal when the signal selection module outputs the third intermediate signal, wherein the level transition signal has a linear relation with the first level signal and the second level signal.
2. The level selection circuit of claim 1, wherein the selection branch comprises a first MOS transistor, and the signal selection module further comprises a first current source and a first output terminal;
the grid electrode of each first MOS tube is connected with one signal input end;
the first ends of all the first MOS tubes are connected, the second ends of all the first MOS tubes are connected, the first ends are grounded, and the second ends are connected with the first output end;
the input end of the first current source is connected with a power supply end, and the output end of the first current source is connected with the first output end.
3. The level selection circuit of claim 2, wherein the signal transmission module comprises a second current source, a third current source, a fourth current source, a first resistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second input terminal, and a second output terminal;
the second input end is connected with the first output end, the second input end is connected with the grid electrode of the second MOS tube, the first end of the second MOS tube is connected with the second end of the third MOS tube, the second end of the second MOS tube is connected with the input end of the second current source, and the output end of the second current source is grounded; the first end of the third MOS tube is connected with a power supply end, the second end of the third MOS tube is connected with the grid electrode of the third MOS tube, the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the first end of the fourth MOS tube is connected with the power supply end, the second end of the fourth MOS tube is connected with the input end of the third current source, and the output end of the third current source is grounded;
a first end of the fifth MOS tube is connected with the power supply end, a second end of the fifth MOS tube is connected with a second end of the second MOS tube, a grid electrode of the fifth MOS tube is connected with an output end of the fourth current source, and an input end of the fourth current source is connected with the power supply end;
the grid electrode of the fifth MOS tube is connected with the first end of the sixth MOS tube, the second end of the sixth MOS tube is grounded, the grid electrode of the sixth MOS tube is connected with the first end of the first resistor, the second end of the first resistor is grounded, and the second output end of the first MOS tube is connected with the grid electrode of the sixth MOS tube;
the second end of the seventh MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the seventh MOS tube is connected with the second end of the fourth MOS tube, the first end of the seventh MOS tube is connected with the second end of the eighth MOS tube, the first end of the eighth MOS tube is connected with the power supply end, and the second end of the eighth MOS tube is connected with the grid electrode of the eighth MOS tube.
4. The level selection circuit of claim 3, wherein the width-to-length ratios of the first MOS transistor and the sixth MOS transistor are the same;
the width-length ratio of the second MOS tube is the same as that of the fifth MOS tube;
the width-length ratio of the third MOS tube is the same as that of the fourth MOS tube.
5. The level selection circuit of claim 3, wherein the first MOS transistor is a PMOS transistor;
when the level of the first level signal is less than a first threshold level and the level of the second level signal is greater than the first threshold level, the first level signal and the second level signal meet a first preset condition;
when the level of the first level signal is greater than the first threshold level and the level of the second level signal is less than the first threshold level, the first level signal and the second level signal meet a second preset condition, and the first threshold level is the conduction level of the PMOS transistor.
6. The level selection circuit of claim 3, wherein the first MOS transistor is an NMOS transistor;
when the level of the first level signal is greater than a second threshold level and the level of the second level signal is less than the second threshold level, the first level signal and the second level signal meet a first preset condition;
when the level of the first level signal is smaller than the second threshold level and the level of the second level signal is greater than the second threshold level, the first level signal and the second level signal meet a second preset condition, and the second threshold level is the conduction level of the NMOS transistor.
7. The level selection circuit of claim 3, wherein the second MOS transistor, the fifth MOS transistor and the seventh MOS transistor are NMOS transistors, and the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor and the eighth MOS transistor are PMOS transistors.
8. A level selection chip comprising the level selection circuit according to any one of claims 1 to 7.
9. An electronic device comprising the level selection chip of claim 8.
10. A method of level selection, comprising:
receiving a plurality of input level signals, wherein the plurality of level signals at least comprise a first level signal and a second level signal;
when the first level signal and the second level signal meet a first preset condition, a first selection branch circuit is conducted, a signal selection module outputs a first intermediate signal, and a signal transmission module converts the first intermediate signal into a first level signal and outputs the first level signal;
when the first level signal and the second level signal meet a second preset condition, a second selection branch circuit is conducted, a signal selection module outputs a second intermediate signal, and a signal transmission module converts the second intermediate signal into a second level signal and outputs the second level signal;
in the process of switching the first preset condition to the second preset condition, the first selection branch and the second selection branch are conducted, the signal selection module outputs a third intermediate signal, the signal transmission module converts the third intermediate signal into a level transition signal and outputs the level transition signal, and the level transition signal has a linear relationship with the first level signal and the second level signal.
CN202010074441.1A 2020-01-22 2020-01-22 Level selection circuit, level selection method, chip and electronic equipment Active CN111294035B (en)

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CN204794953U (en) * 2015-07-21 2015-11-18 上海与德通讯技术有限公司 Switch circuit and radio frequency circuit
CN106656164A (en) * 2016-11-16 2017-05-10 上海艾为电子技术股份有限公司 High-level selection circuit and electronic system
CN108988850A (en) * 2018-08-31 2018-12-11 重庆西南集成电路设计有限责任公司 Double mode for phaselocked loop linearizes charge pump circuit and mode selection circuit
CN110620424A (en) * 2019-09-26 2019-12-27 北京智芯微电子科技有限公司 Power supply switching circuit and method for backup power supply domain

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Publication number Priority date Publication date Assignee Title
CN101989755A (en) * 2009-07-30 2011-03-23 立锜科技股份有限公司 Hybrid charger as well as control circuit and method thereof
CN103716035A (en) * 2012-09-28 2014-04-09 华润矽威科技（上海）有限公司 Signal selection circuit and secondary comparator including same
CN202931272U (en) * 2012-10-29 2013-05-08 Tcl通力电子（惠州）有限公司 Electronic device and signal one-out-of-two circuit thereof
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