CN111293890A - Method for dynamically adjusting switching speed of switching device and switching device circuit - Google Patents

Method for dynamically adjusting switching speed of switching device and switching device circuit Download PDF

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Publication number
CN111293890A
CN111293890A CN202010075295.4A CN202010075295A CN111293890A CN 111293890 A CN111293890 A CN 111293890A CN 202010075295 A CN202010075295 A CN 202010075295A CN 111293890 A CN111293890 A CN 111293890A
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China
Prior art keywords
switching device
time
current
turn
delay time
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CN202010075295.4A
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Chinese (zh)
Inventor
郑俊杰
张程龙
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Huayuan Zhixin Semiconductor Shenzhen Co Ltd
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Huayuan Zhixin Semiconductor Shenzhen Co Ltd
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Priority to CN202010075295.4A priority Critical patent/CN111293890A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

Abstract

The embodiment of the application discloses a method for dynamically adjusting the switching speed of a switching device and a switching device circuit. The method comprises the following steps: calculating real-time turn-off delay time from a falling edge of a driving signal of a switching device to turn-off of the switching device; comparing the real-time turn-off delay time with a reference turn-off delay time to obtain a first comparison result; and adjusting the gate drive voltage of the switching device, the gate drive current of the switching device and the gate discharge current of the switching device based on the first comparison result, so that the real-time turn-off delay time is within the range of the reference turn-off delay time. The circuit includes a switching device, a gate drive voltage regulation circuit, a gate drive current regulation circuit, and a gate discharge current regulation circuit. The embodiment of the application can rapidly reduce the time required by the recombination of the n-region excess carriers of the switching device.

Description

Method for dynamically adjusting switching speed of switching device and switching device circuit
Technical Field
The present disclosure relates to switching devices, and particularly to a method for dynamically adjusting a switching speed of a switching device and a switching device circuit.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite device of a Bipolar Junction Transistor (BJT) and a Field Effect Transistor (MOSFET), and has the advantages of both a power Transistor and a Field Effect Transistor. The IGBT introduces the conductance modulation effect of the BJT into a high-resistance drift region of a VDMOS (vertical double-diffused metal oxide semiconductor field effect transistor), greatly improves the conduction characteristic of the device, has the characteristics of high input impedance and high switching speed of an MOSFET (metal oxide semiconductor field effect transistor), and has wide application in the occasions of electronic technology, electric transmission, switching power supply and the like. However, the IGBT has drift of the electronic device, and thus has a long current tail, a long dead time, and the like during use.
The above background disclosure is only for the purpose of assisting in understanding the inventive concepts and technical solutions of the present application and does not necessarily pertain to the prior art of the present application, and should not be used to assess the novelty and inventive step of the present application in the absence of explicit evidence to suggest that such matter has been disclosed at the filing date of the present application.
Disclosure of Invention
The application provides a method for dynamically adjusting the switching speed of a switching device and a switching device circuit, which can quickly reduce the time required by the recombination of n-region excess carriers of the switching device.
In a first aspect, the present application provides a method of dynamically adjusting a switching speed of a switching device, comprising:
a1, calculating the real-time turn-off delay time from the falling edge of the driving signal of the switching device to the turn-off of the switching device;
a2, comparing the real-time turn-off delay time with a reference turn-off delay time to obtain a first comparison result;
a3, based on the first comparison result, adjusting the gate drive voltage of the switching device, adjusting the gate drive current of the switching device, and adjusting the gate discharge current of the switching device, so that the real-time turn-off delay time is within the range of the reference turn-off delay time.
In some of the preferred embodiments of the present invention,
further comprising:
a4, calculating the real-time turn-on delay time from the rising edge of the driving signal of the switching device to the turn-on of the switching device;
a5, comparing the real-time opening delay time with a reference opening delay time to obtain a second comparison result;
the A3 is as follows:
and adjusting the gate drive voltage of the switching device, the gate drive current of the switching device and the gate discharge current of the switching device based on the first comparison result and the second comparison result, so that the real-time turn-off delay time is within the range of the reference turn-off delay time.
In some preferred embodiments, said a1 specifically comprises: determining that the switching device is turned off based on the on-current of the switching device.
In some preferred embodiments, said a4 specifically comprises: determining that the switching device is turned on based on the on-current of the switching device; the switching device is a transistor; the transistor is an insulated gate bipolar transistor.
In some preferred embodiments, the determining that the switching device is turned off based on the on-current of the switching device includes: converting the on-current of the switching device into a first voltage, comparing the first voltage with a first reference voltage, and if the first voltage is within the range of the first reference voltage, determining that the switching device is off.
In some preferred embodiments, the determining that the switching device is turned on based on the on-current of the switching device includes: and converting the conduction current of the switching device into a second voltage, comparing the second voltage with a second reference voltage, and judging that the switching device is on if the second voltage is within the range of the second reference voltage.
In some preferred embodiments, the a1 further comprises: and judging that the switching device is turned off when the switching device is turned off, and calculating the first time from the falling edge of the driving signal of the switching device to the falling edge of the first level signal, wherein the first time is the real-time turn-off delay time.
In some preferred embodiments, the a4 further comprises: and outputting a first level signal when the switching device is judged to be switched on, and calculating second time from the rising edge of the driving signal of the switching device to the rising edge of the first level signal, wherein the second time is the real-time switching-on delay time.
In some preferred embodiments, the switching device is an insulated gate bipolar transistor;
the adjusting of the gate drive voltage of the switching device is: outputting a first adjusting signal to adjust the grid driving voltage of the switching device;
the adjusting of the gate drive current of the switching device is: outputting a second adjusting signal to adjust the grid driving current of the switching device;
the adjusting of the gate discharge current of the switching device is as follows: and outputting a third adjusting signal to adjust the grid discharge current of the switching device.
In a second aspect, the present application provides a switching device circuit that can perform the above-described method.
In a third aspect, the present application also provides a switching device circuit comprising a switching device, a gate drive voltage regulation circuit, a gate drive current regulation circuit, and a gate discharge current regulation circuit;
the gate driving voltage adjusting circuit may adjust a gate driving voltage of the switching device;
the gate drive current regulating circuit can regulate the gate drive current of the switching device;
the gate discharge current adjustment circuit may adjust a gate discharge current of the switching device.
In some preferred embodiments, the circuit further comprises a delay comparison circuit; the delay comparison circuit is used for comparing the voltage corresponding to the conducting current of the switching device with a reference voltage.
In some preferred embodiments, the delay comparison circuit comprises a comparator and a sampling resistor; one input end of the comparator is connected with one end of the sampling resistor; one end of the sampling resistor is connected to the switching device to collect the conducting current of the switching device; the other end of the sampling resistor is connected to the ground.
In some preferred embodiments, the gate drive voltage regulating circuit comprises a transistor.
In some preferred embodiments, the gate drive current regulation circuit comprises a current regulation resistor.
In some preferred embodiments, the gate discharge current regulation circuit includes a discharge regulation resistor.
In some preferred embodiments, the switching device is an insulated gate bipolar transistor.
In some preferred embodiments, the switching device circuit is a flyback power adapter circuit.
In a fourth aspect, the present application provides a computer-readable storage medium comprising: the computer-readable storage medium has stored therein program instructions that, when executed by a processor of a computer, cause the processor to perform the above-described method.
Compared with the prior art, the beneficial effect of this application has:
the gate drive voltage, the gate drive current and the gate discharge current of the switching device are dynamically adjusted, so that the time required by n-region excess carrier recombination can be quickly reduced, the current tailing can be reduced, the dead time can be shortened, the working frequency can be improved, the loss can be reduced, and the working reliability and the switching speed can be improved.
Drawings
Fig. 1 shows an equivalent circuit of an IGBT;
fig. 2 shows a basic structure of an IGBT;
fig. 3 illustrates changes in the on-current and gate voltage of the switching device after the switching device is turned off;
fig. 4 illustrates a change in channel current after the channel of the switching device is turned off;
FIG. 5 is a schematic diagram of a switching device circuit according to an embodiment of the present application;
FIG. 6 is a timing diagram of control according to one embodiment of the present application;
fig. 7 is a flowchart illustrating a method for dynamically adjusting a switching speed of a switching device according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the embodiments of the present application more clearly apparent, the present application is further described in detail below with reference to fig. 1 to 7 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or be indirectly connected to the other element. The connection may be for fixation or for circuit connection.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description of the embodiments and simplifying the description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless specifically defined otherwise.
The structure of the IGBT is equal to a Darlington structure formed by an n-channel MOSFET and a pnp transistor; the drain of the MOSFET is connected to the base of the pnp transistor. The equivalent circuit and the basic structure of the IGBT are shown in fig. 1 and 2.
The turn-off waveform of the IGBT is roughly divided into three stages, as shown in fig. 3, ① turn-off delay time td (off), time Δ t from voltage rising to 10% to current falling to 90% in the turn-off process of ②, and ③ turn-off falling time tf., whereby the expression of the IGBT turn-off time toff is as follows (1).
toff＝td(off)+Δt+tf＝(t1-t0)+(t2-t1)+(t3-t2) (1)
The BJT is a current-controlled device whose emitter e and collector c conduct operating currents controlled by the small current drawn by base b. (1) The time td (off) and the time Δ t in the equation are determined by the intrinsic parameters of the MOSFET. Therefore, the time td (off) and the time Δ t are also determined to be constant for a certain IGBT. The variation of the turn-off time toff of the IGBT is determined by the current fall time tf. In order to shift the IGBT from the forward on state to the forward off state, the gate capacitance must first be discharged by an external circuit to drop the gate voltage below the turn-on voltage Vth of the MOSFET, at which time the channel inversion layer disappears and the channel current IMOS drops rapidly to zero.
Referring to fig. 4, after the channel is turned off, the current of the device IGBT almost instantaneously drops from I0 to I1, and this process is referred to as phase I; after phase I is over, the excess carrier holes in the n-region will disappear by recombination, a process called phase II. Therefore, after the IGBT is turned off, the current fall time tf is composed of two parts, which are the phase I current Δ I fall time and the phase II current I1 fall time, respectively. The stage I process takes place instantaneously, and the time is very short; in the stage II, the hole recombination process of the excessive carriers in the n-region is slow, and the trailing current phenomenon in the turn-off process of the IGBT can be caused, so the turn-off current reduction time tf of the IGBT is mainly determined by the current reduction time in the stage II. And the current falling time in the phase II is the time required by the recombination of the surplus carriers in the n-region.
The present embodiment provides a method for dynamically adjusting the switching speed of a switching device, which can reduce the current falling time in the phase II. The method may be performed by the switching device circuit of the present embodiment. Referring to fig. 5, the switching device circuit of the present embodiment is a typical flyback power adapter circuit, and includes a switching device S1, a gate driving voltage adjusting circuit 10, a gate driving current adjusting circuit 20, a gate discharge current adjusting circuit 30, and a dynamic gate level compensation driving circuit 40.
The switching device S1 of the present embodiment is an insulated gate bipolar transistor, that is, an IGBT. In other embodiments, the switching device may be other switching devices, as the case may be.
In the present embodiment, the gate driving voltage regulating circuit 10 is a circuit including a transistor T1, specifically, a linear Regulator (LDO); one end of the grid driving voltage regulating circuit 10 is connected with a device power supply Vcc; the gate driving voltage regulating circuit 10 may function as a voltage regulator, and may stabilize the output voltage Vcc _ g within a specified range. The gate drive current adjustment circuit 20 is a current adjustment resistor Rchz, and in particular, the current adjustment resistor Rchz is an adjustable charging resistor. The gate discharge current adjusting circuit 30 is a discharge adjusting resistor Rdis, and specifically, the discharge adjusting resistor Rdis an adjustable discharge resistor.
One end of the gate driving current adjusting circuit 20, that is, one end of the current adjusting resistor Rch is connected to one output end of the gate driving voltage adjusting circuit 10, and the other end of the current adjusting resistor Rch is connected to the gate of the switching device S1. That is, the current adjusting resistor Rch connects the gate of the switching device S1 to the output terminal of the gate drive voltage adjusting circuit 10, and can adjust the magnitude of the drive current flowing into the gate of the switching device S1.
One end of the gate discharge current adjusting circuit 30, that is, one end of the discharge adjusting resistor Rdis is connected to the gate of the switching device S1, and the other end of the discharge adjusting resistor Rdis connected to ground.
The dynamic gate level compensation driving circuit 40 is a digital logic control circuit, and can generate and send driving signals to the gate driving voltage adjusting circuit 10, the gate driving current adjusting circuit 20, and the gate discharge current adjusting circuit 30. Illustratively, the dynamic gate level compensation driving circuit 40 is connected to the gate driving voltage adjusting circuit 10, the gate driving current adjusting circuit 20, and the gate discharge current adjusting circuit 30, respectively.
This embodiment will be described with reference to the method of this embodiment. Referring to fig. 7, the method of the present embodiment includes steps a1 through A3.
Step a1, calculating the real-time turn-off delay time from the falling edge of the driving signal of the switching device to the turn-off of the switching device.
Referring to fig. 6, the driving signal PWM _ ctrl is used to control the switching device S1 to be turned on and off, having a rising edge and a falling edge. The rising edge of the driving signal PWM _ ctrl may turn on the switching device S1, and the falling edge may turn off the switching device S1.
The dynamic gate level compensation driving circuit 40 may determine whether the switching device S1 is turned off. For example, the switching device is determined to be off based on the on-current of the switching device S1; specifically, it may be determined that the switching device is turned off when the on current of the switching device S1 reaches a specified current value, or it may be determined that the switching device is turned off when the voltage corresponding to the on current of the switching device S1 reaches a specified voltage value, so that it may be detected when the switching device is turned off; for an insulated gate bipolar transistor, the on-current of the switching device S1 is the collector-emitter current Ice of its BJT transistor.
The dynamic gate level compensation driving circuit 40 starts timing from the occurrence of the falling edge of the driving signal PWM _ ctrl until the timing is stopped when the switching device S1 is detected to be turned off, so that the real-time off delay time Toff _ dly of the switching device S1 can be calculated.
And A2, comparing the real-time turn-off delay time with the reference turn-off delay time to obtain a first comparison result.
The reference off delay time Ton _ dly _ ref of the switching device circuit may be set for the actual situation of the application scenario. Of course, the reference off delay time Ton _ dly _ ref may be fixed or may be adjustable.
After the dynamic gate stage compensation driving circuit 40 calculates the real-time off delay time Toff _ dly of the switching device S1, the real-time off delay time Toff _ dly is compared with the reference off delay time Ton _ dly _ ref to obtain a first comparison result. The first comparison result may be a difference between the real-time turn-off delay time Toff _ dly and the reference turn-off delay time Ton _ dly _ ref, referred to as a turn-off delay difference Δ Toff _ dly. In the present embodiment, Δ Toff _ dly ═ (Toff _ dly-Ton _ dly _ ref).
Step a3, based on the first comparison result, adjusting the gate drive voltage, the gate drive current, and the gate discharge current of the switching device, so that the real-time turn-off delay time is within the range of the reference turn-off delay time.
The dynamic gate stage compensation driving circuit 40 generates a first regulation signal Vreg, a second regulation signal Vrc, and a third regulation signal Vrdis according to the first comparison result, i.e., the turn-off delay difference Δ ton _ dly. The first adjusting signal Vreg is a gate driving voltage adjusting signal; the second adjusting signal Vrc is a gate driving current adjusting signal; the third regulation signal Vrdis is a gate discharge current regulation signal.
The dynamic gate level compensation driving circuit 40 outputs the first adjusting signal Vreg to the gate driving voltage adjusting circuit 10, and adjusts a parameter of the gate driving voltage adjusting circuit 10, so as to change the gate driving voltage of the switching device S1, that is, change the voltage output from the gate driving voltage adjusting circuit 10 to the gate of the switching device S1. The dynamic gate compensation driving circuit 40 outputs the second adjusting signal Vrc to the gate driving current adjusting circuit 20, and adjusts a parameter of the gate driving current adjusting circuit 20, that is, a resistance value of the current adjusting resistor Rch, so as to change the gate driving current of the switching device S1. The dynamic gate compensation driving circuit 40 outputs the third adjusting signal Vrdis to the gate discharge current adjusting circuit 30, and adjusts a parameter of the gate discharge current adjusting circuit 30, that is, a discharge adjusting resistor Rdis, so as to change the gate discharge current of the switching device S1. The adjustment of the gate driving voltage adjusting circuit 10, the gate driving current adjusting circuit 20 and the gate discharging current adjusting circuit 30 by the dynamic gate stage compensation driving circuit 40 finally makes the real-time off delay time Toff _ dly within the range of the reference off delay time Ton _ dly _ ref, that is, makes the off time Toff of the switching device S1 within a specified range. The reference turn-off delay time Ton _ dly _ ref may be a value or a range; then, making the real-time off delay time Toff _ dly within the range of the reference off delay time Ton _ dly _ ref may be making the real-time off delay time Toff _ dly smaller than the reference off delay time Ton _ dly _ ref or making the real-time off delay time Toff _ dly fall within the reference off delay time Ton _ dly _ ref.
Adjusting the gate drive voltage of the switching device, adjusting the gate drive current of the switching device, and adjusting the gate discharge current of the switching device are a dynamic process, i.e., steps a1 through A3 are a cyclic process, and the objective of the adjustment is to gradually approach the final result so that the real-time off delay time Toff _ dly is within the range of the reference off delay time Ton _ dly _ ref.
The turn-off time of a switching device such as an IGBT increases monotonically with increasing voltage; decreases with increasing current. When the current is small, the turn-off time is long; the off time is rapidly shortened with increasing current. When the current is larger than a certain value, the turn-off time is restored to be close to a normal value of the product design (such as a normal value of an instruction manual), and is slowly reduced along with the increase of the current. Therefore, the method of the present embodiment can eventually reduce the off time of the switching device.
The on waveform of the gate voltage Vg of the switching device S1 has a miller plateau, and similarly, the off waveform of the gate voltage Vg also has a miller plateau. The length of time the miller plateau lasts will affect the turn-off time of switching device S1. If the duration of the miller plateau of the on waveform is shorter, then the duration of the miller plateau of the off waveform is also shorter, thereby causing the off time of switching device S1 to be shorter. That is, the on delay time of the switching device S1 becomes shorter, and the off delay time of the switching device S1 also becomes shorter. For this reason, the method of the present embodiment further includes step a4 and step a 5.
And step A4, calculating the real-time turn-on delay time from the rising edge of the driving signal of the switching device to the turn-on of the switching device.
The dynamic gate level compensation driving circuit 40 may determine whether the switching device S1 is turned on or off. Illustratively, the dynamic gate level compensation driving circuit 40 determines that the switching device is on based on the on-current of the switching device S1; specifically, it may be determined that the switching device is turned on when the on current of the switching device S1 reaches a specified current value, or determined that the switching device is turned on when the voltage corresponding to the on current of the switching device S1 reaches a specified voltage value, so that when the switching device is turned on may be detected.
The dynamic gate level compensation driving circuit 40 starts timing from the occurrence of the rising edge of the driving signal PWM _ ctrl until the timing is stopped when the switching device S1 is detected to be turned on, so that the real-time on delay time Ton _ dly of the switching device S1 can be calculated.
In the present embodiment, in the on waveform of the switching device S1, the end point of the miller plateau is the point in time when the switching device S1 is on.
And A5, comparing the real-time opening delay time with the reference opening delay time to obtain a second comparison result.
The reference on delay time Ton _ dly _ ref of the switching device circuit may be set for the actual case of the application scenario. Of course, the reference turn-on delay time Ton _ dly _ ref may be fixed or may be adjustable.
After the dynamic gate stage compensation driving circuit 40 calculates the real-time on delay time Ton _ dly of the switching device S1, the real-time on delay time Ton _ dly is compared with the reference on delay time Ton _ dly _ ref to obtain a second comparison result. The second comparison result may be the difference between the real-time on delay time Ton _ dly and the reference on delay time Ton _ dly _ ref, referred to as the on delay difference Δ Ton _ dly. In the present embodiment, Δ Ton _ dly ═ Ton _ dly — Ton _ dly _ ref.
Based on the presence of step a4 and step a5, step A3 specifically is: based on the first comparison result and the second comparison result, a first regulation signal Vreg is output to adjust the gate driving voltage of the switching device, a second regulation signal Vrc is output to adjust the gate driving current of the switching device, and a third regulation signal Vrdis is output to adjust the gate discharge current of the switching device, so that the real-time turn-off delay time Toff _ dly is within the range of the reference turn-off delay time Ton _ dly _ ref.
The signal magnitudes, i.e., voltage magnitudes, of the first regulation signal Vreg, the second regulation signal Vrc, and the third regulation signal Vrdis output are related to the first comparison result Δ ton _ dly and the second comparison result Δ toff _ dly, and are specifically expressed as expressions (2) to (4).
Vreg＝K1*f(Δton_dly,Δtoff_dly) (2)
Vrc＝K2*f(Δton_dly,Δtoff_dly) (3)
Vrdis＝K3*f(Δton_dly,Δtoff_dly) (4)
Wherein Vreg, Vrc, and Vrdis are voltage values that output a first regulation signal Vreg, a second regulation signal Vrc, and a third regulation signal Vrdis, respectively; k1, K2 and K3 are adjustment coefficients, are dynamically changed, and respectively determine adjustment degrees of a first adjustment signal Vreg, a second adjustment signal Vrc and a third adjustment signal Vrdis; f (Δ ton _ dly, Δ toff _ dly) is a function based on the first comparison result Δ ton _ dly and the second comparison result Δ toff _ dly. By continuously changing K1, K2 and K3, the final regulation objective can be achieved.
This embodiment will be further described.
The switching device circuit of the present embodiment further includes a delay time comparison circuit 50. The delay comparison circuit 50 is configured to compare a voltage corresponding to the on-current of the switching device with a reference voltage.
The delay comparison circuit 50 includes a comparator U1 and a sampling resistor Rc; one input terminal of the comparator U1 is connected to one terminal of the sampling resistor Rc. One end of the sampling resistor Rc is connected to one current output terminal, i.e., the source, of the switching device S1, and the other end of the sampling resistor Rc is connected to ground.
Determining that the switching device is turned on based on the on-current of the switching device includes: the on-current Ice of the switching device S1 is converted into a second voltage, the second voltage is compared with a second reference voltage, and if the second voltage is within the range of the second reference voltage, it is determined that the switching device is on.
Illustratively, the sampling resistor Rc of the delay comparison circuit 50 collects the on-current Ice of the switching device S1 and converts the on-current Ice into a second voltage; the second voltage is input to the comparator U1; the comparator U1 compares the second voltage with a second reference voltage, wherein the second reference voltage is 0.1V; if the second voltage exceeds 0.1V, for example, within the range of the second reference voltage, it is determined that the switching device S1 is on.
Step a4 further includes: and when the switching device S1 is judged to be switched on, outputting the first level signal Vcs _ delay, and calculating a second time from the rising edge of the driving signal PWM _ ctrl of the switching device S1 to the rising edge of the first level signal Vcs _ delay, wherein the second time is real-time switching-on delay time Ton _ dly.
The comparator U1 outputs the first level signal Vcs _ delay when determining that the switching device S1 is on. The first level signal Vcs _ delay is a comparison result of the on current Ice of the switching device S1 and the reference voltage 0.1V. The first level signal Vcs _ delay is a high-low level signal. The first level signal Vcs _ delay is input to the dynamic gate stage compensation driving circuit 40, and referring to fig. 6, a second time from the rising edge of the driving signal PWM _ ctrl of the switching device S1 to the rising edge of the first level signal Vcs _ delay, that is, a real-time on delay time Ton _ dly, is calculated by the dynamic gate stage compensation driving circuit 40.
Determining that the switching device is off based on the on-current of the switching device specifically includes: the on-current Ice of the switching device S1 is converted into a first voltage, the first voltage is compared with a first reference voltage, and if the first voltage is within a range of the first reference voltage, the switching device S1 is determined to be off.
Illustratively, the sampling resistor Rc of the delay comparison circuit 50 collects the on-current Ice of the switching device S1 and converts the on-current Ice into a first voltage; the first voltage is input to the comparator U1; the comparator U1 compares the first voltage with a first reference voltage, wherein the first reference voltage is also 0.1V; if the first voltage is within the range of the first reference voltage, for example, already less than 0.1V, it is determined that the switching device S1 is off.
Step a1 further includes: the first level signal Vcs _ delay is turned off when the determination switching device S1 is turned off, and the first time from the falling edge of the driving signal PWM _ ctrl of the switching device S1 to the falling edge of the first level signal Vcs _ delay is calculated as the real-time turn-off delay time Toff _ dly.
The comparator U1 stops outputting the first level signal Vcs _ delay when it determines that the switching device S1 is off. The first level signal Vcs _ delay is input to the dynamic gate stage compensation driving circuit 40, and referring to fig. 6, the first time from the falling edge of the driving signal PWM _ ctrl of the switching device S1 to the falling edge of the first level signal Vcs _ delay, that is, the real-time off delay time Toff _ dly, is calculated by the dynamic gate stage compensation driving circuit 40.
The present embodiment dynamically adjusts the gate driving voltage, the gate driving current and the gate discharging current of the switching device S1, so as to rapidly reduce the time required for n-region excess carrier recombination, reduce current tailing and shorten dead time, thereby improving the operating frequency, reducing loss and improving the operating reliability.
Those skilled in the art will appreciate that all or part of the processes of the embodiments methods may be performed by a computer program, which may be stored in a computer-readable storage medium and executed to perform the processes of the embodiments methods. And the aforementioned storage medium includes: various media capable of storing program codes, such as ROM or RAM, magnetic or optical disks, etc.
The foregoing is a further detailed description of the present application in connection with specific/preferred embodiments and is not intended to limit the present application to that particular description. For a person skilled in the art to which the present application pertains, several alternatives or modifications to the described embodiments may be made without departing from the concept of the present application, and these alternatives or modifications should be considered as falling within the scope of the present application.

Claims (10)

1. A method for dynamically adjusting switching speed of a switching device, comprising:
a1, calculating the real-time turn-off delay time from the falling edge of the driving signal of the switching device to the turn-off of the switching device;
a2, comparing the real-time turn-off delay time with a reference turn-off delay time to obtain a first comparison result;
a3, based on the first comparison result, adjusting the gate drive voltage of the switching device, adjusting the gate drive current of the switching device, and adjusting the gate discharge current of the switching device, so that the real-time turn-off delay time is within the range of the reference turn-off delay time.
2. The method of claim 1,
further comprising:
a4, calculating the real-time turn-on delay time from the rising edge of the driving signal of the switching device to the turn-on of the switching device;
a5, comparing the real-time opening delay time with a reference opening delay time to obtain a second comparison result;
the A3 is as follows:
and adjusting the gate drive voltage of the switching device, the gate drive current of the switching device and the gate discharge current of the switching device based on the first comparison result and the second comparison result, so that the real-time turn-off delay time is within the range of the reference turn-off delay time.
3. The method according to claim 1, wherein said a1 specifically comprises: determining that the switching device is turned off based on an on-current of the switching device; the switching device is a transistor; the transistor is an insulated gate bipolar transistor.
4. The method according to claim 2, wherein said a4 specifically comprises: determining that the switching device is turned on based on the on-current of the switching device.
5. The method of claim 3, wherein determining that the switching device is off based on the on-current of the switching device comprises: converting the on-current of the switching device into a first voltage, comparing the first voltage with a first reference voltage, and if the first voltage is within the range of the first reference voltage, determining that the switching device is off.
6. The method of claim 4, wherein determining that the switching device is on based on the on-current of the switching device comprises: and converting the conduction current of the switching device into a second voltage, comparing the second voltage with a second reference voltage, and judging that the switching device is on if the second voltage is within the range of the second reference voltage.
7. The method of claim 5, wherein said A1 further comprises: and judging that the switching device is turned off when the switching device is turned off, and calculating the first time from the falling edge of the driving signal of the switching device to the falling edge of the first level signal, wherein the first time is the real-time turn-off delay time.
8. The method of claim 6, wherein said a4 further comprises: and outputting a first level signal when the switching device is judged to be switched on, and calculating second time from the rising edge of the driving signal of the switching device to the rising edge of the first level signal, wherein the second time is the real-time switching-on delay time.
9. A switching device circuit, characterized by: the method according to any one of claims 1 to 8 may be performed.
10. A computer-readable storage medium, comprising: the computer-readable storage medium has stored therein program instructions which, when executed by a processor of a computer, cause the processor to carry out the method according to any one of claims 1 to 8.
CN202010075295.4A 2020-01-22 2020-01-22 Method for dynamically adjusting switching speed of switching device and switching device circuit Pending CN111293890A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111865054A (en) * 2020-06-23 2020-10-30 华源智信半导体(深圳)有限公司 Dynamic driving method and circuit based on grid voltage detection and switch converter
CN113067460A (en) * 2021-03-17 2021-07-02 合肥宏晶微电子科技股份有限公司 Switching signal generation circuit, method and direct current converter
WO2024041099A1 (en) * 2022-08-25 2024-02-29 新誉集团有限公司 Driving voltage control method, apparatus and device, and medium

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111865054A (en) * 2020-06-23 2020-10-30 华源智信半导体(深圳)有限公司 Dynamic driving method and circuit based on grid voltage detection and switch converter
CN111865054B (en) * 2020-06-23 2022-02-11 华源智信半导体(深圳)有限公司 Dynamic driving method and circuit based on grid voltage detection and switch converter
CN113067460A (en) * 2021-03-17 2021-07-02 合肥宏晶微电子科技股份有限公司 Switching signal generation circuit, method and direct current converter
CN113067460B (en) * 2021-03-17 2022-03-08 合肥宏晶微电子科技股份有限公司 Switching signal generation circuit, method and direct current converter
WO2024041099A1 (en) * 2022-08-25 2024-02-29 新誉集团有限公司 Driving voltage control method, apparatus and device, and medium

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