CN111293215A - Magnetic tunneling junction device based on two-dimensional free magnetic layer and manufacturing method thereof - Google Patents
Magnetic tunneling junction device based on two-dimensional free magnetic layer and manufacturing method thereof Download PDFInfo
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- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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Abstract
The invention provides a magnetic tunneling junction device based on a two-dimensional free magnetic layer and a manufacturing method thereof, wherein the device comprises the following components: the first metal connecting layer is formed on a CMOS circuit substrate and is connected with the drain electrode of the MOS tube; a first metal transition layer; a fixed magnetic layer; a tunneling layer; a free magnetic layer, the free magnetic layer being a two-dimensional ferromagnetic material layer; a second metal transition layer; and a second metal connection layer. After the tunneling layer is manufactured, the free magnetic layer is manufactured by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process, and compared with a sputtering process, the method can prevent the tunneling layer from being damaged by sputtering particles and improve the quality of the tunneling layer. The free magnetic layer is a two-dimensional ferromagnetic material layer, and the thickness of the free magnetic layer is small, so that the magnetization orientation speed of the magnetic tunneling junction device can be improved, and a light and thin magnetic tunneling junction device can be obtained.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a magnetic tunneling junction device based on a two-dimensional free magnetic layer and a manufacturing method thereof.
Background
As portable computing devices and wireless communication devices increase in use, memory devices may require higher density, lower power consumption, and/or non-volatility. The magnetic memory device may be capable of satisfying the above-mentioned technical requirements.
Many electronic devices contain electronic memory. The electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is capable of storing data when power is lost, whereas volatile memory is not capable of storing data when power is lost. Magnetoresistive Random Access Memory (MRAM) is a promising candidate for next generation electronic memory due to its advantages over current electronic memories. MRAM is generally faster and has better endurance than current non-volatile memories such as flash random access memory. MRAM generally has similar performance and density compared to current volatile memories, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), but MRAM has lower power consumption. Since the MTJ device has high operation speed and low power consumption and is used to replace a capacitor of a DRAM, the MTJ device can be applied to an image device and a mobile device having low power consumption and high speed.
The magnetoresistive device has a low resistance when the spin directions (i.e., the directions of magnetic fluxes) of the two magnetic layers are the same as each other, and a high resistance when the spin directions are opposite to each other. In this way, bit data can be written to the magnetoresistive memory device using a change in cell resistance that changes depending on the magnetization state of the magnetic layer. A magnetoresistive memory having an MTJ structure will be described by way of example. In an MTJ memory cell having a structure composed of a ferromagnetic layer/insulating layer/ferromagnetic layer, when electrons that have passed through a first ferromagnetic layer pass through an insulating layer serving as a tunneling barrier (tunneling barrier), the tunneling probability changes depending on the magnetization direction of a second ferromagnetic layer. That is, when the magnetization directions of the two ferromagnetic layers are parallel, the tunneling current is maximized, and when they are antiparallel, the tunneling current is minimized. For example, it can be considered that when the resistance is high, data "1" is written, and when the resistance is low, data "0" is written. When a current flows through the magnetic layer, the current will be polarized, forming a spin-polarized current. Spin electrons transfer spin momentum to a magnetic moment of a free magnetic layer, so that the magnetic moment of the spin magnetic layer obtains spin momentum and then changes direction, which is called spin transfer torque, and thus, the STT-MRAM realizes information writing by spin current.
The core of the STT-MRAM memory cell remains an MTJ, consisting of two ferromagnetic layers of different thickness and a nonmagnetic spacer layer of a few nanometers thick. Through external circuitry, current can pass through the MTJ from a direction perpendicular to the MJT surface. When a current passes through a thicker ferromagnetic layer (called the fixed magnetic layer), the electrons are spin polarized, with the spin direction being the magnetic moment direction of the fixed magnetic layer. If the thickness of the intermediate nonmagnetic spacer layer is small enough to ensure a high degree of polarization, spin-polarized electrons can transfer their spin angular momentum to the thinner ferromagnetic layer (called the free magnetic layer), changing the magnetization equilibrium state of the free magnetic layer. The fixed magnetic layer, which plays the role of the "polarizable layer", is generally thick (tens of nanometers), has a large saturation magnetization, and its equilibrium state is unchanged. In contrast, the free magnetic layer to be subjected to the spin torque effect is generally thin and has a small saturation magnetization, and therefore, its magnetic moment vector can freely change its orientation according to the polarization direction of the spin electron in the spin current.
The STT-MRAM memory unit has simple structure, no additional write information line with magnetic casing, minimized preparation process, reduced cross section area, high memory density and fast memory speed, and can meet the design requirement of high performance computer system.
In the MTJ spin valve of the STT-MRAM memory cell, the tunneling probability of the spin electrons is related to the material of each magnetic layer, the material and thickness of the tunneling layer. According to a tunneling probability formula, the thinner the tunneling layer is, the higher the tunneling probability is, and the higher the self quality requirement of the tunneling layer is.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a magnetic tunneling junction device based on a two-dimensional free magnetic layer and a method for manufacturing the same, which are used to solve the problems in the prior art that the growth quality of the tunneling layer is difficult to ensure, the tunneling layer has many defects, and the orientation of the free magnetic layer has a large thickness, which results in a slow change speed.
To achieve the above and other related objects, the present invention provides a method for fabricating a magnetic tunnel junction device based on a two-dimensional free magnetic layer, the method comprising the steps of: 1) forming a fixed magnetic layer on a substrate; 2) forming a tunneling layer on the fixed magnetic layer; 3) and depositing a free magnetic layer on the tunneling layer by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process, wherein the free magnetic layer is a two-dimensional ferromagnetic material layer.
Optionally, step 1) comprises: 1-1) providing a CMOS circuit substrate, forming a first metal connecting layer on the CMOS circuit substrate, and carrying out planarization treatment on the first metal connecting layer, wherein the first metal connecting layer is connected with a drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit; 1-2) forming a first metal transition layer on the first metal connecting layer; 1-3) depositing the fixed magnetic layer on the first metal transition layer by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process.
Optionally, the first metal transition layer has a flat surface, the fixed magnetic layer is closely combined with the first metal transition layer, the fermi level of the first metal transition layer is equal to or similar to the fermi level of the fixed magnetic layer to reduce the contact resistance of the fixed magnetic layer and the first metal transition layer, and the lattice constant of the fixed magnetic layer is similar to the lattice constant of the first metal transition layer to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
Optionally, the CMOS circuit substrate includes a CMOS circuit layer based on an SOI substrate and a planarized dielectric layer covering the CMOS circuit layer.
Optionally, step 3) further comprises: 3-1) forming a tunneling isolation top layer on the free magnetic layer, wherein the tunneling isolation top layer is a two-dimensional insulating material layer; 3-2) forming a second metal transition layer on the tunneling isolation top layer; 3-3) forming a second metal connecting layer on the second metal transition layer; and 3-4) patterning and etching the second metal connecting layer, the second metal transition layer, the free magnetic layer, the tunneling layer, the fixed magnetic layer, the first metal transition layer and the first metal connecting layer to form the magnetic tunneling junction device with the cylindrical structure.
Optionally, the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
Optionally, the material of the free magnetic layer comprises CrGeTe3And CrI3One kind of (1).
Optionally, the tunneling layer is a two-dimensional insulating material layer, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene.
The invention also provides a magnetic tunneling junction device based on the two-dimensional free magnetic layer, which comprises: the first metal connecting layer is formed on a CMOS circuit substrate and is connected with the drain electrode of an MOS tube of the CMOS circuit; the first metal transition layer is formed on the first metal connecting layer; a fixed magnetic layer formed on the first metal transition layer; a tunneling layer formed on the fixed magnetic layer; the free magnetic layer is formed on the tunneling layer and is a two-dimensional ferromagnetic material layer; a second metal transition layer formed on the free magnetic layer; and the second metal connecting layer is formed on the second metal transition layer.
Optionally, the first metal transition layer has a flat surface, the fixed magnetic layer is closely combined with the first metal transition layer, the fermi level of the first metal transition layer is equal to or similar to the fermi level of the fixed magnetic layer to reduce the contact resistance of the fixed magnetic layer and the first metal transition layer, and the lattice constant of the fixed magnetic layer is similar to the lattice constant of the first metal transition layer to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
Optionally, the CMOS circuit substrate includes a CMOS circuit layer based on an SOI substrate and a planarized dielectric layer covering the CMOS circuit layer.
Optionally, the shape of the magnetic tunnel junction device comprises a cylindrical structure, and the diameter of the cylindrical structure ranges from 10nm to 200 nm.
Optionally, the material of the free magnetic layer comprises CrGeTe3And CrI3One kind of (1).
Optionally, the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene.
Optionally, a tunneling isolation top layer is further included between the free magnetic layer and the second metal transition layer, the tunneling isolation top layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
As described above, the magnetic tunneling junction device based on the two-dimensional free magnetic layer and the manufacturing method thereof of the present invention have the following beneficial effects:
according to the invention, after the tunneling layer is manufactured, the free magnetic layer is manufactured by adopting the atomic layer deposition process, compared with the sputtering process, the tunneling layer can be prevented from being damaged by sputtering particles, and the quality of the tunneling layer is improved.
By adopting the atomic layer deposition process to manufacture the free magnetic layer, the two-dimensional insulating material layer with very thin thickness can be selected as the tunneling layer, the consistency of the tunneling layer is very good, and the tunneling probability can be greatly improved while the quality and the function of the tunneling layer are ensured.
The free magnetic layer is a two-dimensional ferromagnetic material layer, and the thickness of the free magnetic layer is small, so that the magnetization orientation speed of the magnetic tunneling junction device can be improved, and a light and thin magnetic tunneling junction device can be obtained.
The invention can directly prepare the magnetic tunneling junction device on the traditional silicon-based CMOS circuit, thereby reducing the preparation cost of the device.
Drawings
Fig. 1 to 8 show the structural schematic diagrams of the steps of the method for manufacturing the magnetic tunnel junction device according to the present invention.
Fig. 9 is a schematic structural diagram of a tunneling layer of the magnetic tunneling junction device according to the present invention.
FIG. 10 is a schematic diagram showing the structure of the free magnetic layer of the magnetic tunnel junction device of the present invention.
Fig. 11 is a schematic flow chart illustrating a method for fabricating a magnetic tunnel junction device according to the present invention.
Description of the element reference numerals
10 CMOS circuit substrate
101SOI substrate
102 CMOS circuit layer
103 dielectric layer
201 first metal connection layer
202 first metal transition layer
203 fixed magnetic layer
204 tunneling layer
205 free magnetic layer
206 second metal transition layer
207 second metal connection layer
208 tunneling isolation top layer
S11-S18
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to fig. 11, the present embodiment provides a method for manufacturing a magnetic tunnel junction device, where the method includes:
as shown in fig. 1 and 11, step 1) S11 is performed first, a CMOS circuit substrate 10 is provided, a first metal connection layer 201 is formed on the CMOS circuit substrate 10, and the first metal connection layer 201 is planarized, where the first metal connection layer 201 is connected to a drain of a MOS transistor of the CMOS circuit.
In the present embodiment, the CMOS circuit substrate 10 may be a CMOS circuit layer 102 based on an SOI substrate 101 and a planarized dielectric layer 103 covering the CMOS circuit layer 102, and is not limited to the examples listed herein.
The material of the first metal connection layer 201 may be one of W, Cu and Al.
The first metal connection layer 201 of this embodiment is formed on a flat dielectric layer 103, and the first metal connection layer 201 may be subjected to planarization processing to obtain the first metal connection layer 201 with a flat surface, so as to improve the flatness of the subsequent first metal transition layer 202.
As shown in fig. 2 and fig. 11, step 2) S12 is then performed to form a first metal transition layer 202 on the first metal connection layer 201.
For example, the first metal transition layer 202 has a flat surface, the fermi level of the first metal transition layer 202 is equal to or similar to the fermi level of the subsequently formed fixed magnetic layer 203 to reduce the contact resistance of the fixed magnetic layer 203 and the first metal transition layer 202, and the lattice constant of the fixed magnetic layer is similar to the first metal transition layer to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
As shown in fig. 3 and 11, step 3) S13 is then performed to deposit the fixed magnetic layer 203 on the first metal transition layer 202 by using an atomic layer deposition process, a chemical vapor deposition process or a thin film lift-off-transfer process.
Since the first metal transition layer 202 has a flat surface and the fermi level of the first metal transition layer 202 is equal to or close to the fermi level of the fixed magnetic layer 203, the fixed magnetic layer 203 and the first metal transition layer 202 can be tightly combined to reduce the contact resistance of the fixed magnetic layer 203 and the first metal transition layer 202, and the lattice constant of the fixed magnetic layer is close to the first metal transition layer to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
For example, the material of the fixed magnetic layer 203 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material.
The deposition quality of the fixed magnetic layer 203 can be effectively improved by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process, the surface of the fixed magnetic layer is smoother, and the quality of the subsequently manufactured tunneling layer 204 can be effectively improved.
As shown in fig. 4 and 11, step 4) S14 is performed to form a tunneling layer 204 on the fixed magnetic layer 203.
By way of example, the tunneling layer 204 may be Al2O3A single crystal layer or an amorphous layer, or a MgO single crystal layer or an amorphous layer, etc., and the tunneling layer 204 may have a thickness ranging from 1 to 2 nm. The tunneling layer 204 can be formed by a chemical vapor deposition process or an atomic layer deposition process, for example, to avoid sputtering particlesThe seed, etc. causes damage to the interface between the fixed magnetic layer 203 and the tunneling layer 204.
As shown in fig. 5 and 11, step 5) S15 is performed next, a free magnetic layer 205 is deposited on the tunneling layer 204 by using an atomic layer deposition process, a chemical vapor deposition process or a thin film strip-transfer process, the free magnetic layer 205 is a two-dimensional ferromagnetic material layer, the structure of the free magnetic layer is schematically shown in fig. 9, a tunneling isolation top layer 208 is formed on the free magnetic layer 205, and the tunneling isolation top layer 208 is a two-dimensional insulating material layer.
In this embodiment, after the tunneling layer 204 is fabricated, the free magnetic layer 205 is fabricated by using an atomic layer deposition process, which can prevent the tunneling layer 204 from being damaged by sputtered particles and improve the quality of the tunneling layer 204 compared with a sputtering process.
The free magnetic layer 205 may be CrGeTe3And CrI3One kind of (1). The free magnetic layer is a two-dimensional ferromagnetic material layer, and the thickness of the free magnetic layer is small, so that the magnetization orientation speed of the magnetic tunneling junction device can be improved, and a light and thin magnetic tunneling junction device can be obtained.
The two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene. The tunneling isolation top layer 208 can effectively isolate the subsequent second metal transition layer from the free magnetic layer, so that no interface state exists between the free magnetic layer and the second metal transition layer, thereby ensuring good ferromagnetic performance of the free magnetic layer. The second metal transition layer and the free magnetic layer conduct electricity through the tunneling effect of electrons. When the tunnel isolation top layer 208 is thin enough, for example, the tunnel isolation top layer 208 can be 1 atomic layer, the probability of tunneling of electrons becomes large enough, and the tunnel isolation top layer 208 exhibits a small series resistance.
As shown in fig. 6 and fig. 11, step 6) S16 is then performed to form a second metal transition layer 206 on the tunneling isolation top layer 208.
As shown in fig. 7 and 11, step 7) S17 is performed to form a second metal connection layer 207 on the second metal transition layer 206.
For example, the material of the second metal connection layer 207 may be one of W, Cu and Al.
As shown in fig. 8 and fig. 11, step 8) is finally performed to pattern and etch the second metal connection layer 207, the second metal transition layer 206, the tunneling isolation top layer 208, the free magnetic layer 205, the tunneling layer 204, the fixed magnetic layer 203, the first metal transition layer 202 and the first metal connection layer 201, so as to form the magnetic tunnel junction device with a pillar structure.
For example, the shape of the magnetic tunnel junction device comprises a cylindrical structure having a diameter ranging from 10nm to 200 nm.
As shown in fig. 9, the present embodiment further provides a magnetic tunnel junction device, including: the first metal connecting layer 201, the first metal connecting layer 201 is formed on a CMOS circuit substrate 10, the first metal connecting layer 201 is connected with the drain of the MOS transistor of the CMOS circuit; a first metal transition layer 202 formed on the first metal connection layer 201; a fixed magnetic layer 203 formed on the first metal transition layer 202; a tunneling layer 204 formed on the fixed magnetic layer 203; a free magnetic layer 205 formed on the tunneling layer 204, the free magnetic layer 205 being a two-dimensional ferromagnetic material layer; a second metal transition layer 206 formed on the free magnetic layer 205; and a second metal connection layer 207 formed on the second metal transition layer 206.
For example, the first metal transition layer 202 has a flat surface, the fixed magnetic layer 203 is tightly coupled to the first metal transition layer 202, and the fermi level of the first metal transition layer 202 is equal to or close to the fermi level of the fixed magnetic layer 203, so as to reduce the contact resistance between the fixed magnetic layer 203 and the first metal transition layer 202.
In the present embodiment, the CMOS circuit substrate 10 may be a CMOS circuit layer 102 based on an SOI substrate 101 and a planarized dielectric layer 103 covering the CMOS circuit layer 102, and is not limited to the examples listed herein.
For example, the shape of the magnetic tunnel junction device comprises a cylindrical structure having a diameter ranging from 10nm to 200 nm.
For example, the material of the fixed magnetic layer 203 includes one of CoFeB, simple substance ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer 205 includes CrGeTe3And CrI3One kind of (1). The free magnetic layer is a two-dimensional ferromagnetic material layer, and the thickness of the free magnetic layer is small, so that the magnetization orientation speed of the magnetic tunneling junction device can be improved, and a light and thin magnetic tunneling junction device can be obtained.
In this embodiment, a tunneling isolation top layer 208 is further included between the free magnetic layer 205 and the second metal transition layer 206, the tunneling isolation top layer 208 is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene. The tunneling isolation top layer 208 can effectively isolate the subsequent second metal transition layer from the free magnetic layer, so that no interface state exists between the free magnetic layer and the second metal transition layer, thereby ensuring good ferromagnetic performance of the free magnetic layer. The second metal transition layer and the free magnetic layer conduct electricity through the tunneling effect of electrons. When the tunnel isolation top layer 208 is thin enough, for example, the tunnel isolation top layer 208 can be 1 atomic layer, the probability of tunneling of electrons becomes large enough, and the tunnel isolation top layer 208 exhibits a small series resistance.
Example 2
As shown in fig. 1 to 11, the present embodiment provides a method for manufacturing a magnetic tunnel junction device, which includes the basic steps of embodiment 1, wherein the difference from embodiment 1 is that the tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure, as shown in fig. 9. For example, the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene. In the present embodiment, the free magnetic layer 205 is manufactured by using an atomic layer deposition process, a chemical vapor deposition process, or a thin film lift-off transfer process, the tunneling layer 204 of the present embodiment may be a two-dimensional insulating material layer with a very thin thickness, the uniformity of the tunneling layer 204 is very good, and the tunneling probability can be greatly improved while the quality and the function of the tunneling layer 204 are ensured.
As shown in fig. 8 to 10, the present embodiment further provides a magnetic tunnel junction device, wherein the basic structure of the magnetic tunnel junction device is as in embodiment 1, and the difference from embodiment 1 is that the tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure, as shown in fig. 9. For example, the two-dimensional insulating material layer includes one of two-dimensional boron nitride, fluorinated graphene, and oxidized graphene. The tunneling layer 204 of the present embodiment is selected as a two-dimensional insulating material layer with a very thin thickness, the uniformity of the tunneling layer 204 is very good, and the tunneling probability can be greatly improved while the quality and the function of the tunneling layer 204 are ensured.
As described above, the magnetic tunnel junction device and the manufacturing method thereof of the present invention have the following beneficial effects:
after the tunneling layer is manufactured, the free magnetic layer is manufactured by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process, and compared with a sputtering process, the method can prevent the tunneling layer from being damaged by sputtering particles and improve the quality of the tunneling layer.
By adopting the atomic layer deposition process, the chemical vapor deposition process or the film stripping-transferring process to manufacture the free magnetic layer, the two-dimensional insulating material layer with very thin thickness can be selected as the tunneling layer, the consistency of the tunneling layer is very good, and the tunneling probability can be greatly improved while the quality and the function of the tunneling layer are ensured.
The free magnetic layer is a two-dimensional ferromagnetic material layer, and the thickness of the free magnetic layer is small, so that the magnetization orientation speed of the magnetic tunneling junction device can be improved, and a light and thin magnetic tunneling junction device can be obtained.
The invention can directly prepare the magnetic tunneling junction device on the traditional silicon-based CMOS circuit, thereby reducing the preparation cost of the device.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A manufacturing method of a magnetic tunneling junction device based on a two-dimensional free magnetic layer is characterized by comprising the following steps:
1) forming a fixed magnetic layer on a substrate;
2) forming a tunneling layer on the fixed magnetic layer;
3) and depositing a free magnetic layer on the tunneling layer by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process, wherein the free magnetic layer is a two-dimensional ferromagnetic material layer.
2. The method of claim 1 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: the step 1) comprises the following steps:
1-1) providing a CMOS circuit substrate, forming a first metal connecting layer on the CMOS circuit substrate, and carrying out planarization treatment on the first metal connecting layer, wherein the first metal connecting layer is connected with a drain electrode of an MOS (metal oxide semiconductor) tube of the CMOS circuit;
1-2) forming a first metal transition layer on the first metal connecting layer;
1-3) depositing the fixed magnetic layer on the first metal transition layer by adopting an atomic layer deposition process, a chemical vapor deposition process or a thin film stripping-transferring process.
3. The method of claim 2 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: the first metal transition layer is provided with a flat surface, the fixed magnetic layer is tightly combined with the first metal transition layer, the Fermi level of the first metal transition layer is equal to or close to that of the fixed magnetic layer so as to reduce the contact resistance of the fixed magnetic layer and the first metal transition layer, and the lattice constant of the fixed magnetic layer is close to that of the first metal transition layer so as to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
4. The method of claim 2 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: the CMOS circuit substrate comprises a CMOS circuit layer based on an SOI substrate and a flattened dielectric layer covering the CMOS circuit layer.
5. The method of claim 2 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: step 3) also includes:
3-1) forming a tunneling isolation top layer on the free magnetic layer, wherein the tunneling isolation top layer is a two-dimensional insulating material layer;
3-2) forming a second metal transition layer on the tunneling isolation top layer;
3-3) forming a second metal connecting layer on the second metal transition layer;
and 3-4) patterning and etching the second metal connecting layer, the second metal transition layer, the free magnetic layer, the tunneling layer, the fixed magnetic layer, the first metal transition layer and the first metal connecting layer to form the magnetic tunneling junction device with the cylindrical structure.
6. The method of claim 5 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
7. The method of claim 1 wherein the two-dimensional free magnetic layer based magnetic tunnel junction device is characterized in that: the free magnetic layer is made of CrGeTe3And CrI3One kind of (1).
8. The method of fabricating a two-dimensional free magnetic layer based magnetic tunneling junction device according to claim 1, wherein: the tunneling layer is a two-dimensional insulating material layer, and the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
9. A two-dimensional free magnetic layer based magnetic tunneling junction device, comprising:
the first metal connecting layer is formed on a CMOS circuit substrate and is connected with the drain electrode of an MOS tube of the CMOS circuit;
the first metal transition layer is formed on the first metal connecting layer;
a fixed magnetic layer formed on the first metal transition layer;
a tunneling layer formed on the fixed magnetic layer;
the free magnetic layer is formed on the tunneling layer and is a two-dimensional ferromagnetic material layer;
a second metal transition layer formed on the free magnetic layer;
and the second metal connecting layer is formed on the second metal transition layer.
10. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: the first metal transition layer is provided with a flat surface, the fixed magnetic layer is tightly combined with the first metal transition layer, the Fermi level of the first metal transition layer is equal to or close to that of the fixed magnetic layer so as to reduce the contact resistance of the fixed magnetic layer and the first metal transition layer, and the lattice constant of the fixed magnetic layer is close to that of the first metal transition layer so as to reduce the thermal mismatch and lattice mismatch of the fixed magnetic layer and the first metal transition layer.
11. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: the CMOS circuit substrate comprises a CMOS circuit layer based on an SOI substrate and a flattened dielectric layer covering the CMOS circuit layer.
12. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: the shape of the magnetic tunneling junction device comprises a cylindrical structure, and the diameter range of the cylindrical structure is between 10nm and 200 nm.
13. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: the free magnetic layer is made of CrGeTe3And CrI3One kind of (1).
14. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
15. The two-dimensional free magnetic layer-based magnetic tunneling junction device of claim 9, wherein: and a tunneling isolation top layer is further arranged between the free magnetic layer and the second metal transition layer, the tunneling isolation top layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises one of two-dimensional boron nitride, fluorinated graphene and oxidized graphene.
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