CN111293180A - Photoelectric detection panel - Google Patents
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- 238000001514 detection method Methods 0.000 title claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 51
- 239000000969 carrier Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 387
- 230000003472 neutralizing effect Effects 0.000 claims description 27
- 238000003860 storage Methods 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 6
- 239000012780 transparent material Substances 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 description 34
- 239000002184 metal Substances 0.000 description 34
- 229920001721 polyimide Polymers 0.000 description 18
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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- 229910052750 molybdenum Inorganic materials 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
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Abstract
The application discloses a photoelectric detection panel, which comprises a low-voltage electrode layer, a high-voltage electrode layer and an amorphous silicon layer; the amorphous silicon layer comprises a conductive part and an insulating part along the vertical direction, the conductive part is configured to generate photo carriers when the amorphous silicon layer is illuminated, and the insulating part of the amorphous silicon layer is filled in a gap between the low-voltage electrode layer and the high-voltage electrode layer and covers the upper surfaces of the low-voltage electrode layer and the high-voltage electrode layer. Through the setting, the amorphous silicon layer can better cover the low-voltage electrode layer and the high-voltage electrode layer, the stability of signal transmission is guaranteed, and meanwhile, the uniformity of the amorphous silicon layer is better, and the problem that the display brightness of the photoelectric detection panel is not uniform can be avoided.
Description
Technical Field
The application relates to the field of photoelectric detection, in particular to a photoelectric detection panel.
Background
The photoelectric detection panel with the interdigital electrode structure has the advantages of simple preparation process, low cost, compatibility with the manufacturing processes of a thin film transistor, a field effect transistor and the like, easy integration, high response speed, small dark current, high filling rate and the like, and occupies a great position in the fields of medical imaging and industrial detection.
The photoelectric detection panel generally adopts deposited metal as an interdigital electrode, for example: molybdenum or aluminum, and a PI layer is covered on the interdigital electrode, and the material of the PI layer is a polyimide film (PI for short). However, the photodetection panel has problems of unstable signal transmission and uneven display brightness of the photodetection panel.
Disclosure of Invention
The application provides a photoelectric detection panel, which can improve the detection performance of the photoelectric detection panel as much as possible.
The application provides a photoelectric detection panel, which comprises a low-voltage electrode layer, a high-voltage electrode layer and an amorphous silicon layer; the low-voltage electrode layer and the high-voltage electrode layer are arranged at intervals in the horizontal direction, and the amorphous silicon layer covers the low-voltage electrode layer and the high-voltage electrode layer;
the amorphous silicon layer comprises a conductive part and an insulating part along the vertical direction, the conductive part is configured to generate photo carriers when the amorphous silicon layer is illuminated, and the insulating part of the amorphous silicon layer is filled in a gap between the low-voltage electrode layer and the high-voltage electrode layer and covers the upper surfaces of the low-voltage electrode layer and the high-voltage electrode layer.
Furthermore, the photoelectric detection panel further comprises a gate insulating layer, the gate insulating layer covers the low-voltage electrode layer and the high-voltage electrode layer, and at least part of the gate insulating layer is filled in a gap between the low-voltage electrode layer and the high-voltage electrode layer;
the amorphous silicon layer is arranged above the gate insulating layer.
Further, the photoelectric detection panel further comprises a neutralization electrode layer, and the voltage of the neutralization electrode layer is negative voltage or the neutralization electrode layer is grounded;
the low-voltage electrode layer extends along the vertical direction to form a low-voltage area, and the neutralizing electrode layer is far away from the low-voltage area.
Further, the photoelectric detection panel comprises a first buffer layer, and the low-voltage electrode layer and the high-voltage electrode layer are both arranged above the first buffer layer;
the neutralizing electrode layer is arranged inside the first buffer layer.
Further, the photoelectric detection panel comprises a protective layer, and the protective layer is arranged above the amorphous silicon layer;
the neutralizing electrode layer is arranged inside the protective layer.
Further, the material of the neutralizing electrode layer is a transparent material.
Further, the photoelectric detection panel further comprises a storage layer;
the low-voltage electrode layer extends in the vertical direction to form a negative-pressure area, at least part of the storage layer is located in the low-voltage area, and the storage layer is arranged below the low-voltage electrode layer and the high-voltage electrode layer.
Further, a through groove is formed in the surface of the low-voltage electrode layer, and an opening is formed in the barrel groove;
the high-voltage electrode layer is provided with a protruding part, and the protruding part enters the through groove through the opening;
a gap exists between the surface of the protruding part and the wall surface of the through groove, and at least part of the amorphous silicon layer is filled in the gap.
Further, the thickness of the low-voltage electrode layer and/or the high-voltage electrode layer is greater than or equal to 100 nanometers and less than or equal to 200 nanometers.
Further, the thickness of the amorphous silicon layer is taken as a first value, and the first value is greater than or equal to 450 nanometers and less than or equal to 600 nanometers; and/or the presence of a gas in the gas,
and taking the thickness of the insulating part positioned above the low-voltage electrode layer and/or the high-voltage electrode layer as a second value, wherein the second value is greater than or equal to 10 nanometers and less than or equal to 20 nanometers.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
in the above arrangement, the amorphous silicon layer can better cover the low-voltage electrode layer and the high-voltage electrode layer, so that the stability of signal transmission is ensured, and meanwhile, the uniformity of the amorphous silicon layer is better, so that the problem of uneven display brightness of the photoelectric detection panel can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
Fig. 1 is a schematic cross-sectional view of a photodetection panel according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional view of a photodetection panel according to another embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of a photodetection panel according to another embodiment of the present application.
Fig. 4 is a schematic top view of the low voltage electrode layer and the high voltage electrode layer in an embodiment of the present application.
Description of the reference numerals
Low voltage electrode layer 100
Through groove 101
Second connecting part 110
Neutralizing electrode layer 120
High voltage electrode layer 200
Insulating part 320
Bottom insulating layer 460
First organic planarization layer 700
Light-shielding layer 820
First via 830
First connecting portion 840
Second via 850
Second organic planarization layer 920
Vertical direction H
Horizontal direction X
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The manner in which the following exemplary embodiments are described does not represent all manner of consistency with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that the terms "first," "second," and the like as used in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The embodiments of the present application will be described in detail below with reference to the accompanying drawings. Features in the embodiments described below may be combined with each other without conflict.
As shown in fig. 1 to 3, the present application discloses a photodetection panel 10, the photodetection panel 10 includes a low voltage electrode layer 100, a high voltage electrode layer 200, an amorphous silicon layer 300, and a transistor structure 400. The voltage applied to the low voltage electrode layer 100 is smaller than the voltage of the high voltage electrode layer 200, and the low voltage electrode layer 100 and the high voltage electrode layer 200 are disposed at an interval in the horizontal direction X. The amorphous silicon layer 300 covers the low voltage electrode layer 100 and the high voltage electrode layer 200. The transistor structure 400 is disposed under the low voltage electrode layer 100, the high voltage electrode layer 200, and the amorphous silicon layer 300. Which includes a gate metal layer 410, a source metal layer 420, a drain metal layer 430, and a semiconductor layer 440. The low voltage electrode layer 100 extends downward and is electrically connected to the source metal layer 420 or the drain metal layer 430 to transmit an electrical signal to the transistor structure 400. In the present embodiment, the low voltage electrode layer 100 is electrically connected to the drain metal layer 430.
The amorphous silicon layer 300 includes a conductive portion 310 and an insulating portion 320 along a vertical direction H, the conductive portion 310 is configured to generate photo carriers when light is applied, and the insulating portion 320 of the amorphous silicon layer 300 is filled in a gap between the low voltage electrode layer 100 and the high voltage electrode layer 200 and covers upper surfaces of the low voltage electrode layer 100 and the high voltage electrode layer 200.
When the environment around the photodetection panel 10 is converted from a dark state to an illuminated state, the conductive portion 310 of the amorphous silicon layer 300 receives illumination, photo carriers are generated inside the amorphous silicon layer, i.e., the conductive portion 310 generates charges, and the resistance is greatly reduced, so that the optical signal is converted into an electrical signal through the above-mentioned photovoltaic effect. Since the voltage of the low voltage electrode layer 100 is smaller than that of the high voltage electrode layer 200, most of the voltage is applied to the insulating portion 320 of the amorphous silicon layer 300 having a relatively high resistance. When the voltage is high enough, the insulating portion 320 may generate a tunneling effect along the longitudinal direction (height direction H), so as to conduct the low voltage electrode layer 100 and the conductive portion 310 along the longitudinal direction, and simultaneously conduct the high voltage electrode layer 200 and the conductive portion 310, thereby achieving communication between the high voltage electrode layer 200 and the low voltage electrode layer 100, and the high voltage electrode layer 200 may transmit charges to the low voltage electrode layer 100. Since the low voltage electrode layer 100 is connected to the transistor structure 400, when the environment around the photodetection panel 10 is converted from a dark state to an illuminated state, the electrical signal generated in the conductive portion 310 can be transmitted to the transistor structure 400 through the low voltage electrode layer 100 to turn on the transistor structure 400. Information reading and storage are realized through the on and off of the transistor structure 400, and the purpose of detection is further achieved.
In some designs, a PI layer is laid on the low voltage electrode layer 100 and the high voltage electrode layer 200, and the PI layer is made of polyimide film (PI), and the PI layer needs to completely cover the low voltage electrode layer 100 and the high voltage electrode layer 200 made of metal materials. Since the thickness of the PI layer is relatively thin, generally between 200 nm and 300 nm, in order to make the PI layer completely cover the low voltage electrode layer 100 and the high voltage electrode layer 200, the thicknesses of the low voltage electrode layer 100 and the high voltage electrode layer 200 need to be controlled, and generally the thickness is required to be controlled to be about 50 nm. Since the low voltage electrode layer 100 and the high voltage electrode layer 200 are both made of a metal material, when the metal material is too thin, it is easily oxidized in the manufacturing process, that is, the low voltage electrode layer 100 and the high voltage electrode layer 200 are easily oxidized. Once the low voltage electrode layer 100 and/or the high voltage electrode layer 200 are easily oxidized, the oxidation layer increases the difficulty of photo carrier tunneling, thereby increasing the resistance and affecting the yield. Meanwhile, the low-voltage electrode layer 100 and/or the high-voltage electrode layer 200 are too thin, so that the metal has poor climbing performance and poor deposition coverage performance in the process of depositing and forming the low-voltage electrode layer 100 and the high-voltage electrode layer 200, and phenomena such as fracture, signal transmission terminal and the like easily occur. Moreover, the low voltage electrode layer 100 and/or the high voltage electrode layer 200 made of metal materials are generally in a columnar structure, and when the thickness of the low voltage electrode layer is thin, the corners after etching are quite steep and have a large slope angle, which also affects the deposition coverage of subsequent film layers, and poor contact is easily generated at the corners. In other words, the deposition coverage of the PI layer is affected, so that it is difficult to achieve uniform film thickness of the PI layer in the manufacturing process. Through many experiments, the thickness difference between the maximum value and the minimum value of the thickness of the PI layer reaches 70 nm to 80 nm, and is particularly prominent near the low voltage electrode layer 100 and/or the high voltage electrode layer 200. However, when the film thickness uniformity of the PI layer as the dielectric layer cannot be controlled within 20 nm, that is, the thickness difference between the maximum value and the minimum value of the thickness of the PI layer cannot be controlled within 20 nm, the photodetection panel 10 has a problem of display luminance unevenness.
However, in the present design, the thickness of the amorphous silicon layer 300 is not limited, and it can better cover the low voltage electrode layer 100 and the high voltage electrode layer 200 to ensure the stability of signal transmission. Meanwhile, the amorphous silicon layer 300 has good uniformity, so that the problem of non-uniform display brightness of the photodetection panel 10 can be avoided. The detection performance of the photoelectric detection panel 10 is improved. The amorphous silicon layer 300 replaces the PI layer, so that the production difficulty of the photoelectric detection panel 10 is reduced, the production cost is reduced, and the productivity is improved.
Further, as shown in fig. 1, the thickness D1 of the amorphous silicon layer 300 is set as a first value, and the first value is greater than or equal to 450 nm and less than or equal to 600 nm. The thickness D1 of the amorphous silicon layer 300 is defined so that the amorphous silicon layer 300 with a larger thickness can better cover the low voltage electrode layer 100 and the high voltage electrode layer 200. Meanwhile, the thickness D2 of the portion of the insulating portion 320 located above the low voltage electrode layer 100 and/or the high voltage electrode layer 200 is set to a second value, which is 10 nm or more and 20 nm or less. When the PI layer is laid over the low voltage electrode layer 100 and the high voltage electrode layer 200, the voltage required to achieve the tunneling effect needs to be maintained at 200V or more, and power consumption is large. However, in the present design, by controlling the thickness of the insulating portion 320 to be kept within a small range, the voltage required to achieve the tunneling effect only needs to be 10-20v when the environment around the photodetection panel 10 is converted from the dark state to the light state, in other words, the voltage applied to the high voltage electrode layer 200 is greatly reduced.
Further, as shown in fig. 1, since the thickness of the amorphous silicon layer 300 is not limited, the thickness of the low voltage electrode layer 100 and the high voltage electrode layer 200 may be increased. In the present embodiment, the thickness D3 of the low voltage electrode layer 100 and/or the high voltage electrode layer 200 is equal to or greater than 100 nm and equal to or less than 200 nm. By limiting the thickness of the low-voltage electrode layer 100 and the high-voltage electrode layer 200, the problem of easy oxidation caused by too low thickness can be avoided, the difficulty of photo-carrier tunneling caused by an oxide layer is avoided, the resistance is ensured to be at a normal value, and the yield is improved. Meanwhile, by increasing the thicknesses of the low-voltage electrode layer 100 and the high-voltage electrode layer 200, the problems of steep corners and large slope angles can be improved, the influence on the deposition coverage of subsequent films can be avoided, the problems of poor contact and easy disconnection at the corners can be avoided, and the yield can be further improved.
Further, as shown in fig. 1 to 3, the photodetection panel 10 further includes a glass substrate layer 500, a ground layer 450, a bottom insulating layer 460, a second buffer layer 600, a first organic planarization layer 700, a third buffer layer 810, a second organic planarization layer 920, a first buffer layer 930, and a protective layer 950.
The glass substrate layer 500 serves as the bottom layer structure of the photodetection panel 10, and serves to support the film layer located above the bottom layer structure. Above the glass substrate layer 500 is deposited a ground layer 450 and a gate metal layer 410 of the transistor structure 400. The voltage of the ground plane 450 is zero. The gate metal layer 410 and the ground layer 450 are both disposed in the same layer and are formed simultaneously. For example: a metal layer may be deposited on the glass substrate layer 500, and then the gate metal layer 410 and the ground layer 450 may be formed by etching or the like. After the gate metal layer 410 and the ground layer 450 are manufactured, a bottom insulating layer 460 is formed above the gate metal layer 410 and the ground layer 450 by a deposition shaping manner, and at least a portion of the bottom insulating layer 460 enters a gap between the gate metal layer 410 and the ground layer 450. Then, the semiconductor layer 440, the gate metal layer 410, the source metal layer 420 and the drain metal layer 430 are formed on the bottom insulating layer 460, thereby forming the complete transistor structure 400. After the transistor structure 400 is formed, a second buffer layer 600, a first organic planarization layer 700 and a third buffer layer 810 are sequentially deposited and patterned on the transistor structure 400 and the bottom insulating layer 460 away from the transistor structure 400.
After that, a first through hole 830 is formed through the second buffer layer 600, the first organic planarization layer 700, and the third buffer layer 810, and one end of the first through hole 830 is connected to the drain metal layer 430. Of course, in other embodiments, one end of the first via 830 may also be connected to the source metal layer 420. Then, a metal is deposited on the third buffer layer 810, so that a portion of the metal flows to the source metal layer 420 or the drain metal layer 430 along the first via 830, and a first connection 840 is formed. After the first connection portion 840 is formed, a second organic planarization layer 920 and a first buffer layer 930 are sequentially formed over the third buffer layer 810 and the first connection portion 840.
After that, the second via 850 is formed on the second organic planarization layer 920 and the first buffer layer 930. One end of the second through hole 850 is connected to the first connection part 840. Then, a metal is deposited on the first buffer layer 930, so that a portion of the metal flows to the first connection portion 840 along the second via 850, and the second connection portion 110 is formed.
The high voltage electrode layer 200 and the low voltage electrode layer 100 are both disposed above the first buffer layer 930, and the high voltage electrode layer 200 and the low voltage electrode layer 100 are disposed in the same layer and are formed simultaneously. For example: a layer of metal may be deposited on the first buffer layer 930, and then the high voltage electrode layer 200 and the low voltage electrode layer 100 may be formed by etching or the like.
Wherein a portion of the metal of the low voltage electrode layer 100 enters the second via hole 850 to form the second connection portion 110. The low voltage electrode layer 100 is electrically connected to the source metal layer 420 or the drain metal layer 430 through the second connection portion 110 and the first connection portion 840 to enable transmission of an electrical signal to the transistor structure 400.
Finally, an amorphous silicon layer 300 and a protective layer 950 are sequentially formed over the high voltage electrode layer 200 and the low voltage electrode layer 100. In this process, a portion of the amorphous silicon layer 300 also enters the second via 850, however, the thickness D1 of the amorphous silicon layer 300 is the thickness of the amorphous silicon layer 300 away from the second via 850. The protection layer 950 is disposed above the amorphous silicon layer 300 to protect the structure between the glass substrate layer 500 and the protection layer 950.
In this embodiment, the protective layer 950, the first buffer layer 930, the second buffer layer 600, and the third buffer layer 810 are made of the same material and are made of silicon nitride.
Further, as shown in fig. 1 to 3, the photodetecting panel 10 further includes a light shielding layer 820. The light-shielding layer 820 is disposed inside the third buffer layer 810 and is made of an opaque material, in this embodiment, a metal. The light-shielding layer 820 is located above the transistor structure 400. When the environment around the photodetection panel 10 is in an illumination state, the light-shielding layer 820 can block the semiconductor layer 440 in the transistor structure 400 from being irradiated by external light. In this embodiment, the bottom structure of the third buffer layer 810 can be formed on the first organic planarization layer 700 by deposition and patterning, and then the light-shielding layer 820 can be formed on the bottom structure of the third buffer layer 810 by deposition and patterning. Finally, a top structure of the third buffer layer 810 is formed by depositing and patterning the light-shielding layer 820 and the bottom structure of the third buffer layer 810. In this way, the third buffer layer 810 wraps the light shielding layer 820.
Further, the photodetection panel 10 further includes a gate insulating layer 940. The gate insulating layer 940 covers the low voltage electrode layer 100 and the high voltage electrode layer 200, and at least a portion of the gate insulating layer 940 is filled in the gap between the low voltage electrode layer 100 and the high voltage electrode layer 200. The amorphous silicon layer 300 is disposed over the gate insulating layer 940. By providing the gate insulating layer 940, it is ensured that the low voltage electrode layer 100 and the high voltage electrode layer 200 are in an insulating state when the environment around the photodetection panel 10 is in a dark state, and leakage current caused by a transverse (horizontal direction X) electric field is reduced.
Further, the photodetection panel 10 further includes a neutralizing electrode layer 120, the voltage of the neutralizing electrode layer 120 is a negative voltage or the neutralizing electrode layer 120 is grounded, and the voltage of the neutralizing electrode layer 120 is always lower than the voltage of the low voltage electrode layer 100. When the environment around the photodetection panel 10 is in an illuminated state for a long time, a large amount of electric charges are transferred from the high voltage electrode layer 200 to the low voltage electrode layer 100, resulting in a large amount of electric charges accumulating in the low voltage electrode layer 100. Since the voltage of the neutralizing electrode layer 120 is low, a large amount of accumulated charges can be transferred to the neutralizing electrode layer 120, and accumulation of a large amount of charges at the low voltage electrode layer 100 is prevented by rapid release of accumulated charges. Moreover, through the quick release of the accumulated charges, the repeated display of the information at the previous moment caused by the accumulation of the charges at the next moment can be avoided, namely, the ghost phenomenon is avoided. Meanwhile, when the environment around the photodetection panel 10 is converted from the light state to the dark state, the charges can be transferred from the high voltage electrode layer 200 to the neutralizing electrode layer 120, thereby avoiding a path for transferring the charges from the high voltage electrode layer 200 to the low voltage electrode layer 100, forming current pinch-off, reducing the leakage current, and ensuring the accurate display of the photodetection panel 10.
The low voltage electrode layer 100 extends in a vertical direction to form a low voltage area AA, and the neutralizing electrode layer 120 is away from the low voltage area AA. With the above arrangement, the neutralization electrode layer 120 and the low-voltage electrode layer 100 are prevented from forming a coupling capacitance.
As shown in fig. 1, in an embodiment, the neutralizing electrode layer 120 is disposed inside the first buffer layer 930 to absorb charges and block leakage current.
In other embodiments, the neutralizing electrode layer 120 may also be disposed above the amorphous silicon layer 300. For example, the neutralizing electrode layer 120 may be disposed inside the protective layer 950. In another embodiment, as shown in FIG. 2, the neutralizing electrode layer 120 is disposed inside the protection layer 950 and directly above the high voltage electrode layer 200. Of course, as shown in fig. 3, the neutralizing electrode layer 120 may also be disposed at other positions in the protection layer 950, and only needs to be away from the low voltage area AA to avoid forming a coupling capacitance with the low voltage electrode layer 100.
Further, as shown in fig. 2 and 3, when the neutralizing electrode layer 120 is disposed above the amorphous silicon layer 300, the material of the neutralizing electrode layer 120 is a transparent material to avoid shielding of external light, and ensure the accuracy of detection of the photodetecting panel 10.
Further, as shown in fig. 1 to 3, the photodetecting panel 10 further includes a storage layer 130. At least a portion of the storage layer 130 is located in the low pressure area AA. The storage layer 130 is disposed below the low voltage electrode layer 100 and the high voltage electrode layer 200 to prevent the storage layer 130 made of a metal material from shielding light. In the above arrangement, the storage layer 130 and the low voltage electrode layer 100 may form a coupling capacitor to balance charges.
Further, as shown in fig. 4, the surface of the low voltage electrode layer 100 is provided with a through groove 101, and the barrel groove is provided with an opening 102, wherein the opening 102 faces the high voltage electrode layer 200. The high voltage electrode layer 200 has a protrusion 201, and the protrusion 201 enters the through-groove 101 through the opening 102. A gap exists between the surface 202 of the protrusion 201 and the wall surface 103 of the through-trench 101, and the gap is filled with at least a portion of the amorphous silicon layer 300 (shown with reference to fig. 1-3). Through the arrangement, the low-voltage electrode layer 100 and the high-voltage electrode layer 200 form an interdigital structure, which is beneficial to detection of optical signals and rapid transmission of the signals.
Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. The photoelectric detection panel is characterized by comprising a low-voltage electrode layer, a high-voltage electrode layer and an amorphous silicon layer; the low-voltage electrode layer and the high-voltage electrode layer are arranged at intervals in the horizontal direction, and the amorphous silicon layer covers the low-voltage electrode layer and the high-voltage electrode layer;
the amorphous silicon layer comprises a conductive part and an insulating part along the vertical direction, the conductive part is configured to generate photo carriers when the amorphous silicon layer is illuminated, and the insulating part of the amorphous silicon layer is filled in a gap between the low-voltage electrode layer and the high-voltage electrode layer and covers the upper surfaces of the low-voltage electrode layer and the high-voltage electrode layer.
2. The photodetection panel according to claim 1 further comprising a gate insulating layer covering the upper portions of the low voltage electrode layer and the high voltage electrode layer, and wherein at least a portion of the gate insulating layer is filled in a gap between the low voltage electrode layer and the high voltage electrode layer;
the amorphous silicon layer is arranged above the gate insulating layer.
3. The photodetection panel according to claim 1 wherein said photodetection panel further comprises a neutralizing electrode layer, a voltage of said neutralizing electrode layer is a negative voltage or said neutralizing electrode layer is grounded;
the low-voltage electrode layer extends along the vertical direction to form a low-voltage area, and the neutralizing electrode layer is far away from the low-voltage area.
4. The photodetection panel according to claim 3 wherein said photodetection panel comprises a first buffer layer, said low voltage electrode layer and said high voltage electrode layer being disposed above said first buffer layer;
the neutralizing electrode layer is arranged inside the first buffer layer.
5. The photodetection panel according to claim 3 wherein said photodetection panel comprises a protective layer disposed above an amorphous silicon layer;
the neutralizing electrode layer is arranged inside the protective layer.
6. The photodetection panel according to claim 5, wherein a material of the neutralizing electrode layer is a transparent material.
7. The photodetection panel according to claim 1 wherein said photodetection panel further comprises a storage layer;
the low-voltage electrode layer extends in the vertical direction to form a negative-pressure area, at least part of the storage layer is located in the low-voltage area, and the storage layer is arranged below the low-voltage electrode layer and the high-voltage electrode layer.
8. The photodetection panel according to claim 1 wherein a surface of said low voltage electrode layer is provided with a through groove, said barrel groove being provided with an opening;
the high-voltage electrode layer is provided with a protruding part, and the protruding part enters the through groove through the opening;
a gap exists between the surface of the protruding part and the wall surface of the through groove, and at least part of the amorphous silicon layer is filled in the gap.
9. The photodetection panel according to any one of claims 1 to 8, characterized in that the thickness of the low voltage electrode layer and/or the high voltage electrode layer is equal to or greater than 100 nm and equal to or less than 200 nm.
10. The photodetection panel according to any one of claims 1 to 8, characterized in that the thickness of the amorphous silicon layer is taken as a first value, the first value being 450 nm or more and 600 nm or less; and/or the presence of a gas in the gas,
and taking the thickness of the insulating part positioned above the low-voltage electrode layer and/or the high-voltage electrode layer as a second value, wherein the second value is greater than or equal to 10 nanometers and less than or equal to 20 nanometers.
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