CN111292667B - Time schedule controller and display panel - Google Patents
Time schedule controller and display panel Download PDFInfo
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- CN111292667B CN111292667B CN202010234674.3A CN202010234674A CN111292667B CN 111292667 B CN111292667 B CN 111292667B CN 202010234674 A CN202010234674 A CN 202010234674A CN 111292667 B CN111292667 B CN 111292667B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The application discloses a time schedule controller, which comprises a receiving module, a grouping module, a line storage module, an image processing module, a recombination module and an output module; according to the time schedule controller, the pixel data are divided into multiple sections according to the storage length through the grouping module, and then the multiple sections of pixel data are stored into the line storage module in a segmented and sequential mode, so that the requirement on the storage length in the line storage module is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to a time schedule controller and a display panel.
Background
In the display panel industry, a timing controller, which is one of the core control components of a display panel, mostly needs to use a line buffer for buffering pixel data, and the storage length of the line buffer is required to be able to buffer at least one pixel data, and a storage length of 30 bits is commonly used, that is, the storage length of each memory cell cannot be smaller than that of any pixel data.
As the size and resolution of the display panel are larger, the storage length required for each pixel data is also increased along with the improvement of the algorithm precision, and the storage length of the memory cell may need to be expanded to 36 bits or 42 bits, or even higher, so the storage length requirement for the memory cell in the line buffer is higher, and the use cost of the line buffer is increased along with the increase of the storage length of the memory cell.
Disclosure of Invention
The application provides a time schedule controller, has solved along with the size and the resolution ratio increase of display panel, leads to the problem that the storage length of line buffer increases in the time schedule controller.
In a first aspect, the present application provides a timing controller, which includes a receiving module, a grouping module, a line storage module, an image processing module, a recombination module, and an output module; the receiving module is used for accessing pixel data with the storage length of N bits in a video source; the grouping module is connected with the output end of the receiving module and used for accessing the pixel data, grouping the pixel data into X sections according to the storage length, wherein the adjacent sections of the pixel data at the grouping joint are provided with overlapping areas, and the storage length of the overlapping areas is M bits; the row storage module is connected with the output end of the grouping module and is used for sequentially storing the pixel data of the X sections in different storage subareas; the image processing module is connected with the line storage module and is used for sequentially reading and processing the pixel data of the X section; the recombination module is connected with the output end of the image processing module and is used for accessing the pixel data of the X section, erasing the superposition area at the tail end of each section of pixel data and recombining the pixel data of the X section; and the output module is connected with the output end of the recombination module and used for outputting the pixel data.
In a first embodiment of the first aspect according to the first aspect, X is a positive number greater than 1.
In a second implementation form of the first aspect, based on the first implementation form of the first aspect, M is smaller than N/X.
In a third implementation form of the first aspect, the image processing module comprises a control unit and an overdrive unit; the control unit is connected with the receiving module, the grouping module, the line storage module, the recombination module, the output module and the overdrive unit; the input end of the overdrive unit is connected with the output end of the row storage module; the output end of the overdrive unit is connected with the input end of the recombination module.
In a fourth implementation manner of the first aspect, based on the third implementation manner of the first aspect, the image processing module further comprises a white balance test unit; the white balance testing unit is connected with the control unit; the input end of the white balance test unit is connected with the output end of the overdrive unit; the output end of the white balance testing unit is connected with the input end of the recombination module.
In a fifth implementation form of the first aspect, M is a storage length of at least one bit.
In a sixth implementation form of the first aspect, based on the first implementation form of the first aspect, X is a positive integer not less than 2.
In a seventh implementation manner of the first aspect, based on the fifth implementation manner of the first aspect, M is a storage length of 8 bits.
In a second aspect, the present application provides a display panel, which includes the timing controller in any of the above embodiments.
In a first implementation form of the second aspect, the display panel further comprises a source driver; the output end of the time schedule controller is connected with the input end of the source driver.
The application provides a time schedule controller divides pixel data into the multistage through grouping module according to storage length, saves the pixel data segmentation of multistage in proper order the line storage module again, has reduced the requirement to the storage length of line storage module, then restores the pixel data after the segmentation through the reorganization module to normal output and the use that do not influence pixel data.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first structure of a timing controller according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a pixel data packet in a timing controller according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a second structure of a timing controller according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a third structure of a timing controller according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1 and 2, the present embodiment provides a timing controller including a receiving module 10, a grouping module 20, a line storage module 30, an image processing module 40, a reassembly module 50, and an output module 60; the receiving module 10 is configured to access pixel data output by a front-end video source, and may assume that a storage length required for each pixel data is N bits, and it can be understood that the storage length of the pixel data is related to an algorithm precision thereof, where the higher the algorithm precision is, the longer the storage length is, and the algorithm precision is improved along with an increase in line resolution; the grouping module 20 accesses the pixel data output by the receiving module 10, and it can be understood that the pixel data is sequentially grouped or cut into X segments of pixel data according to the storage length, and the adjacent segment of pixel data at the grouping joint has an overlapping area, the storage length of the overlapping area is M bits, for example, when any pixel data is grouped into 2 segments, the length of each segment of pixel data is N/2 bits, the tail end of the first segment of pixel data also has a first overlapping area with the storage length of M bits, meanwhile, the front end of the second segment of pixel data has a second overlapping area with the storage length of M bits, the pixel data in the first overlapping area and the pixel data in the second overlapping area are repeated, the pixel data in the first overlapping area is redundant, mainly for preventing the pixel data joint from easily losing data, and so on, the more the segments of any pixel data group are, the smaller the required storage length is, namely the minimum storage length is N/X + M bits; the grouping module 20 sequentially stores the grouped multiple segments of pixel data into different storage partitions of the line storage module 30, so that the storage length required for storing the pixel data is reduced; the image processing module 40 sequentially reads and processes the X segments of pixel data, and processes the pixel data in segments without changing the positions of the corresponding pixel data; the recombination module 50 accesses the processed X segments of pixel data from the output end of the image processing module 40, then erases the overlapping area at the tail end of each segment of pixel data, sequentially joins the head and the tail of each segment of pixel data, recombines the X segments of pixel data, and then restores the grouped segments of pixel data to the pixel data before grouping; the output module 60 then outputs the restored pixel data to the back end without affecting the use of the back end.
As shown in fig. 2, it can be understood that X is a positive number greater than 1, that is, the storage length of each piece of pixel data after grouping can be reduced, and it should be noted that the larger the value of X is, the shorter the storage length of each piece of pixel data is, and the arrangement can be performed according to the existing storage length.
As shown in fig. 2, in one embodiment, M is smaller than N/X, that is, the storage length of the overlapping area is smaller than the storage length of each segment of pixel data, and the smaller M, the smaller the storage length of the overlapping area is, so that the storage length of the line storage module 30 can be reduced.
As shown in fig. 3, in one embodiment, the image processing module 40 includes a control unit 41 and an overdrive unit 42; the control unit 41 is connected with the receiving module 10, the grouping module 20, the line storage module 30, the recombination module 50, the output module 60 and the overdrive unit 42; the input of the overdrive unit 42 is connected to the output of the row memory module 30; the output of the overdrive unit 42 is connected to the input of the recombination module 50. It will be appreciated that the control unit 41 performs a centrally scheduled operation to achieve an orderly operation of the timing controller, mostly at the associated clock frequency, which does not affect the transmission and storage of pixel data and is therefore not addressed.
As shown in fig. 4, in one embodiment, the image processing module 40 further includes a white balance test unit 43; the white balance test unit 43 is connected with the control unit 41; the input end of the white balance test unit 43 is connected with the output end of the overdrive unit 42; the output of the white balance test unit 43 is connected to the input of the recombination module 50.
In one embodiment, M may be, but is not limited to, a storage length of at least one bit, and may also be a storage length of 8 bits.
In one embodiment, X is a positive integer no less than 2.
In one embodiment, the present embodiment provides a display panel, which includes the timing controller in any one of the above embodiments.
In one embodiment, the display panel further comprises a source driver; the output end of the time schedule controller is connected with the input end of the source driver.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The timing controller provided in the embodiments of the present application is described in detail above, and the principle and the implementation of the present application are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A timing controller, comprising:
the receiving module is used for accessing pixel data with the storage length of N bits in a video source;
the grouping module is connected with the output end of the receiving module and used for accessing the pixel data and grouping the pixel data into X sections according to the storage length, the pixel data of the adjacent section positioned at the grouping joint part is provided with an overlapping area, and the storage length of the overlapping area is M bits;
the row storage module is connected with the output end of the grouping module and is used for sequentially storing the pixel data of X sections in different storage partitions;
the image processing module is connected with the line storage module and is used for sequentially reading and processing the pixel data of the X section;
the recombination module is connected with the output end of the image processing module and is used for accessing the pixel data of the X section, erasing the superposition area at the tail end of each section of the pixel data and recombining the pixel data of the X section; and
and the output module is connected with the output end of the recombination module and used for outputting the pixel data.
2. The timing controller of claim 1, wherein X is a positive number greater than 1.
3. The timing controller of claim 2, wherein M is less than N/X.
4. The timing controller according to claim 1, wherein the image processing module includes a control unit and an overdrive unit;
the control unit is connected with the receiving module, the grouping module, the line storage module, the recombination module, the output module and the overdrive unit; the input end of the overdrive unit is connected with the output end of the row storage module; and the output end of the overdrive unit is connected with the input end of the recombination module.
5. The timing controller of claim 4, wherein the image processing module further comprises a white balance test unit;
the white balance test unit is connected with the control unit; the input end of the white balance test unit is connected with the output end of the overdrive unit; and the output end of the white balance testing unit is connected with the input end of the recombination module.
6. The timing controller of claim 1, wherein M is a storage length of at least one bit.
7. The timing controller of claim 2, wherein X is a positive integer not less than 2.
8. The timing controller of claim 6, wherein M is a memory length of 8 bits.
9. A display panel comprising the timing controller according to any one of claims 1 to 8.
10. The display panel according to claim 9, further comprising a source driver; and the output end of the time schedule controller is connected with the input end of the source driver.
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| CN202010234674.3A CN111292667B (en) | 2020-03-30 | 2020-03-30 | Time schedule controller and display panel |
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| CN202010234674.3A CN111292667B (en) | 2020-03-30 | 2020-03-30 | Time schedule controller and display panel |
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| CN111292667B true CN111292667B (en) | 2022-08-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1929539A (en) * | 2002-07-19 | 2007-03-14 | 三星电子株式会社 | Image processing device and method |
| KR101319535B1 (en) * | 2006-12-26 | 2013-10-21 | 삼성전자주식회사 | Device of processing image and method thereof |
| CN101587676B (en) * | 2008-05-22 | 2012-10-17 | 联咏科技股份有限公司 | Data access method of time schedule controller for flat panel display |
| US8564522B2 (en) * | 2010-03-31 | 2013-10-22 | Apple Inc. | Reduced-power communications within an electronic display |
| US9633451B2 (en) * | 2014-02-12 | 2017-04-25 | Mediatek Singapore Pte. Ltd. | Image data processing method of multi-level shuffles for multi-format pixel and associated apparatus |
| US10614747B2 (en) * | 2017-01-31 | 2020-04-07 | Synaptics Incorporated | Device and method for driving display panel in response to image data |
| CN107274849B (en) * | 2017-08-10 | 2019-12-31 | 深圳市华星光电技术有限公司 | Time schedule controller, control method thereof and display device |
| CN107633477B (en) * | 2017-10-20 | 2021-04-20 | 上海兆芯集成电路有限公司 | Image processing method and device |
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