CN111289876A - Method for generating boundary scan interconnection test vector of large-scale circuit - Google Patents

Abstract

The invention discloses a method for generating a boundary scan interconnection test vector of a large-scale circuit, which comprises the steps of firstly extracting characteristic information of a circuit to be tested from a related report file of a circuit board, calculating the short-circuit fault probability of an interconnection network in the circuit to be tested, and establishing a fault limiting model; then constructing a fault set according to the fault model and determining a fitness function of a genetic algorithm; then randomly generating an initial test vector; and finally, injecting the faults in the fault set into a limited model of the tested circuit, evaluating whether the faults in the fault set can be diagnosed by using a fitness function, and optimizing the current test vector by using a genetic algorithm if the faults in the fault set cannot be diagnosed by using the current test vector until the test vector meets the expectation.

Description

Method for generating boundary scan interconnection test vector of large-scale circuit

Technical Field

The invention belongs to the technical field of circuit fault testing, and particularly relates to a method for generating boundary scan interconnection testing vectors of a large-scale circuit.

Background

With the development of large-scale integrated circuit technology, the structure of a circuit is more and more complex, the physical size of a device is smaller and smaller, the testing and maintenance difficulty is increased, and the access to the internal nodes of a circuit system by a physical probe is difficult or even impossible in the traditional testing methods such as a needle bed test, a flying needle test and the like. The advent of boundary scan technology has provided a powerful means for solving the testing problem of complex circuits.

A hotspot and difficulty in the study of boundary scan technology is the algorithm for generating interconnection test vectors. Algorithms can be divided into four categories: a conventional test vector generation algorithm, a self-adaptive test vector generation algorithm, a structural test vector generation algorithm and a test vector generation algorithm based on fault simulation. With the increase of circuit scale, the number of measurable networks on a tested circuit board is rapidly increased, and the conventional vector generation algorithm has difficulty in considering the length of a test vector and the fault diagnosis capability at the time of testing. The test vector generation algorithm based on the fault simulation provides a new idea for the generation of the test vector, so that the genetic algorithm, the neural network and the like are applied to the interconnection test. The basic idea is to randomly generate an initial test vector set, inject the faults in a predetermined fault set into a circuit model to be tested, then verify whether the current test vector set can diagnose the faults, and if not, modify the current test vector set until the test vector set can cover all the faults in the fault set.

At present, a test vector generation algorithm based on fault simulation does not combine structural information of a circuit when a fault set is predetermined, and an unlimited fault model is adopted, namely, any two networks are assumed to be possible to be short-circuited, and actually, only networks with close physical positions are possible to be short-circuited. The preset fault set directly influences the fault diagnosis capability of the test vector set generated by the algorithm, and the fault set determined by using the unlimited fault model is obviously not superior enough, so that the improvement space is still provided.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a method for generating boundary scan interconnection test vectors of large-scale circuits, which utilizes a genetic algorithm to quickly generate the test vectors.

In order to achieve the above object, the present invention provides a method for generating a boundary scan interconnection test vector of a large-scale circuit, comprising the steps of:

(1) extracting characteristic information of the circuit to be tested

Analyzing a netlist file, a BOM file and a BSDL file of a circuit to be tested, and recording the total number of measurable networks in the circuit to be tested and the distance between any two objects on a circuit board in the circuit to be tested; wherein, the total number of measurable networks is recorded as N, the ith measurable network is recorded as N_i，i＝1,2,…,n；

(2) Constructing a test vector set MTV

In boundary scan testing, test vector STV loaded onto ith testable network_iI ═ 1,2, …, n; then STV is used_iForming a Boolean matrix as a row vector, which is called a test vector set MTV;

wherein,

a_nmthe element which represents the nth row and the mth column in the matrix MTV has a Boolean value;

(3) calculating the short-circuit fault probability of the interconnection network in the circuit to be tested

(3.1) calculating fault probability α (P) of short circuit between any two objects (such as welding spots, wires, etc.) on the circuit board_m,P_n)；

Wherein, P_mAnd P_nRepresenting two objects on a circuit board, α₀A represents a decay function of the probability of a short-circuit fault with respect to the distance between two objects, L₀As two objectsA minimum distance between two objects, L is the distance between two objects, L_MThe maximum physical distance when a short-circuit fault occurs between two objects;

(3.2) computing two networks N interconnected_iAnd N_jProbability of short-circuit failure β (N)_i,N_j)；

(4) Establishing a limited fault model P

(5) Structural failure set

(5.1) constructing a fault set H₁；

H₁＝{N_iN_j|β(N_i,N_j)≠0,β(N_i,N_j)∈P}，

Wherein N is_iN_jRepresentation network N_iAnd N_jShort-circuit fault occurring therebetween, short-circuit fault N_iN_jIs marked as a fault

(5.2) constructing a fault set H₂；

The fault probabilities in the P are sorted in a descending manner, two networks with the maximum short-circuit probability in the P are selected as a group of short-circuit faults, corresponding rows and columns of the two networks in the P are deleted, whether the maximum short-circuit probability in the current P is 0 or not is finally judged, and if not, the two selected networks are added to the H₂Then, continuously selecting two networks with the next highest short-circuit probability and judging again; otherwise, ending the circulation; thereby obtaining H₂Comprises the following steps:

H₂＝{N_i1N_j1,N_i2N_j2,…,N_ixN_jx,…,N_iqN_jq}

wherein q is H₂The total number of the short-circuit fault groups in two, x is 1,2, …, q, N_ixN_jxRepresenting the x-th group of networks N_ixAnd N_jxShort-circuit fault occurring therebetween, short-circuit fault N_ixN_jxIs marked as a fault

(6) Structural fitness function F

F＝{F0,F1,F2,F3}＝F0+F1+F2+F3

Wherein,

λ is a constant;

is a fault set H₁Medium network N_iAnd N_jThe fault symptom when the short circuit occurs, if the circuit occurs the line and the short circuit,

∩, indicates a bitwise AND operation, if a wired-OR circuit occurs,

∪ denotes a bitwise OR operation;

F3＝β(N_i1N_j1)+β(N_i2N_j2)+…，β(N_i1,N_j1)、β(N_i2,N_j2) .. is failure set H₂The short-circuit probability corresponding to the network in which the fault symptom is confused;

(7) generating a test vector using a genetic algorithm

(7.1) encoding with MTV as Individual

Splitting each line of the MTV and splicing the split lines into a line in order by adopting a binary coding mode to obtain an individual:

T＝[STV₁,STV₂,…,STV_n]＝[a₁₁,a₁₂,…,a₂₁,a₂₂,…,a_n1,…,a_nm]

(7.2) initializing genetic algorithm population

If the size of the population is M, then initializing the genetic algorithm population P ═ T₁,T₂,…,T_k,…T_M](ii) a The cross probability of initializing the genetic algorithm is P_cThe mutation probability is P_v(ii) a Setting the maximum iteration number as t_maxInitializing the current iteration time t to be 0; if the average fitness threshold of the individuals is F'_end；

(7.3) crossover, variation and population merging

Performing cross and variation treatment on the population, wherein the sequence of individual population is firstly disturbed during the cross treatment, and the population has a probability P_cPerforming analog binary cross processing, and then performing probability P_vPerforming polynomial variation treatment, and marking the population after crossing and variation treatment as Q;

merging the population P and the population Q to obtain a merged population C, wherein C is P ∪ Q, and the number of individuals in the merged population C is 2N;

(7.4) calculating the individual fitness value

Calculating the fitness value of each individual in the combined population C by using the fitness function constructed in the step (6);

(7.5) preferred individuals make up the next generation population

Adopting a championship selection algorithm, disordering the sequence of individuals in the combined population C, comparing fitness values F pairwise, retaining individuals with small F values, and eliminating individuals with large F values to obtain a next generation population;

(7.6) calculating the average fitness value F' of individuals in the next generation of population;

wherein, F_kThe fitness value of the kth individual in the next generation population;

(7.7) judging whether the current iteration time t reaches the maximum iteration time t_maxOr whether the individual average fitness value F 'is less than a set threshold value F'_endIf yes, entering the step (7.8), otherwise, adding 1 to the current iteration time t, and returning to the step (7.3);

and (7.8) sequencing the individuals in the next generation population in an ascending order according to the fitness value F, and selecting the individual with the minimum fitness value F as an optimal individual, wherein the optimal individual is the generated boundary scanning interconnection test vector.

The invention aims to realize the following steps:

the invention relates to a method for generating a boundary scan interconnection test vector of a large-scale circuit, which comprises the steps of firstly extracting characteristic information of a circuit to be tested from a related report file of a circuit board, calculating the short-circuit fault probability of an interconnection network in the circuit to be tested, and establishing a limited fault model; then constructing a fault set according to the fault model and determining a fitness function of a genetic algorithm; then randomly generating an initial test vector; and finally, injecting the faults in the fault set into a limited model of the tested circuit, evaluating whether the faults in the fault set can be diagnosed by using a fitness function, and optimizing the current test vector by using a genetic algorithm if the faults in the fault set cannot be diagnosed by using the current test vector until the test vector meets the expectation.

Meanwhile, the method for generating the boundary scan interconnection test vector of the large-scale circuit further has the following beneficial effects:

(1) the test vector is generated by utilizing the genetic algorithm, an approximate optimal solution can be obtained in a short time, the generated test vector has superior compactness index and low symptom misjudgment rate and symptom confusion rate, and the test time and the fault diagnosis capability can be considered;

(2) compared with the test vector generated by the improved counting sequence algorithm, the test vector generated by the method has the same PTV number, but the symptom misjudgment rate and the symptom confusion rate are far lower than those of the test vector generated by the improved counting sequence algorithm;

(3) the two algorithms of the test vector generation algorithm based on fault simulation and the structural test vector generation algorithm are combined, so that the number of concentrated faults is reduced, the fault diagnosis capability is ensured, the PTV number is reduced, and the test time is shortened;

(4) the fault simulation-based test vector generation algorithm does not combine the structural information of the circuit when constructing the fault set, and an unlimited fault model is adopted, namely, any two networks are assumed to be possible to be short-circuited, and only the networks with similar physical positions are possible to be short-circuited actually, so that the constructed fault set has a large number of faults, but many short-circuit faults are impossible to occur; according to the invention, the limited fault model is established by extracting the circuit information, and the limited fault model is applied to the construction of the fault set, so that the constructed fault set is more reasonable, and the finally generated test vector can take the test time and the fault diagnosis capability into consideration.

Drawings

FIG. 1 is a flow chart of a method for generating boundary scan interconnect test vectors for large scale circuits according to the present invention;

FIG. 2 is a fabric fault set H₂A flow chart of (1);

FIG. 3 is a schematic diagram of an interconnection network of circuits;

FIG. 4 is a plot of the average fitness value of individuals in a population as a function of the number of iterations.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Examples

FIG. 1 is a flowchart of a method for generating boundary scan interconnection test vectors for large-scale circuits according to the present invention.

In this embodiment, as shown in fig. 1, the method for generating boundary scan interconnection test vectors of a large-scale circuit according to the present invention includes the following steps:

s1, extracting characteristic information of the circuit to be tested

Analyzing a netlist file, a BOM file and a BSDL file of a circuit to be tested, and recording the total number of measurable networks in the circuit to be tested and the distance between any two objects on a circuit board in the circuit to be tested; wherein, the total number of measurable networks is recorded as N, the ith measurable network is recorded as N_i，i＝1,2,…,n；

S2, constructing a test vector set MTV

In boundary scan testing, test vector STV loaded onto ith testable network_iI ═ 1,2, …, n; then STV is used_iForming a Boolean matrix as a row vector, which is called a test vector set MTV;

wherein,

a_nmthe element which represents the nth row and the mth column in the matrix MTV has a Boolean value;

s3, calculating the short-circuit fault probability of the interconnection network in the circuit to be tested

S3.1, a lot of studies show that the probability of short circuit between any two objects (such as solder joints, wires, etc.) on the circuit board is significantly reduced with the distance between the two objects, so we can calculate the failure probability α (P) of short circuit between any two objects (such as solder joints, wires, etc.) on the circuit board by using the following formula_m,P_n)；

Wherein, P_mAnd P_nRepresenting two objects on a circuit board α₀The probability of short-circuit fault between two nearest objects is usually much less than 1; a represents a decay function of the probability of a short-circuit fault with respect to the distance between two objects; l is₀Is the minimum distance between two objects, depending on the manufacturing process of the circuit board; l is the distance between two objects, typically L₀Integer multiples of; l is_MThe maximum physical distance when a short-circuit fault occurs between two objects;

s3.2, the network on the circuit board is usually composed of a plurality of interconnected objects, the probability of short circuit between different networks is different, and the two interconnected networks N can be calculated by the following formula_iAnd N_jProbability of short-circuit failure β (N)_i,N_j)；

S4, establishing a limited fault model P

Calculating the short-circuit possibility among the networks by using the formula in the step S3 to obtain a short-circuit probability matrix P among the networks, namely the established limited fault model;

the matrix P being a symmetric matrix, the network N_i、N_jProbability of short circuit β (N)_i,N_j) And network N_j、N_iProbability of short circuit β (N)_j,N_i) Are the same. The elements on the diagonal of the matrix are all 1, indicating that the network itself is shorted to itself. If the calculated probability of the short circuit between two networks is 0, the element of the corresponding position in the matrix is 0, and the short circuit between the two networks in the fault model with the limitation does not occur. A large part of the inter-network short probability matrix of an actual circuit board has 0 elements because only the networks with close physical positions can be short-circuited. Thus electricityThe fault model of the way is greatly simplified.

S5, constructing fault set

S5.1, constructing a fault set H₁；

H₁＝{N_iN_j|β(N_i,N_j)≠0,β(N_i,N_j)∈P}，

Wherein N is_iN_jRepresentation network N_iAnd N_jShort-circuit fault occurring therebetween, short-circuit fault N_iN_jIs marked as a fault

Set H₁And the network pairwise short-circuit faults corresponding to all non-zero probabilities in the network short-circuit probability matrix P are contained.

S5.2, constructing a fault set H₂；

As shown in fig. 2, the failure probabilities in P are sorted in a descending order, two networks with the maximum short-circuit probability in P are selected as a group of short-circuit failures, the rows and columns corresponding to the two networks in P are deleted, and finally whether the maximum short-circuit probability in P is 0 or not is judged, if not, the two selected networks are added to H₂Then, continuously selecting two networks with the next highest short-circuit probability and judging again; otherwise, ending the circulation; thereby obtaining H₂Comprises the following steps:

H₂＝{N_i1N_j1,N_i2N_j2,…,N_ixN_jx,…,N_iqN_jq}

wherein q is H₂The total number of the short-circuit fault groups in two, x is 1,2, …, q, N_ixN_jxRepresenting the x-th group of networks N_ixAnd N_jxShort-circuit fault occurring therebetween, short-circuit fault N_ixN_jxIs marked as a fault

S6 construction fitness function F

The fitness function directly influences the quality of a test vector set finally obtained by the algorithm. In the embodiment, MTV is used as an individual in a genetic algorithm, and the fitness value of the individual is evaluated from the fault detection rate of a test vector, the symptom misjudgment which may occur to the test vector when a preset fault set is injected, and the symptom confusion condition, wherein the lower the fitness value is, the stronger the fault diagnosis capability of the individual is, and the more possible the individual is to be selected to enter the next generation of population during iteration.

The fitness function is designed as follows:

F＝{F0,F1,F2,F3}＝F0+F1+F2+F3

wherein,

lambda is a constant and takes a value between 0 and 1. According to the limited topology fault detection theorem: a sufficient requirement to be able to detect any constrained topology failure is that all STVs will not be all "0" or all "1" and that the STVs of neighboring networks are not identical. A larger value for F0 indicates that the greater the number of STVs in the test vector set in which all 0 s or all 1 s occur, the more likely the individual is to be eliminated.

A larger value of F1 represents more STVs among neighboring networks. If both the F0 and F1 values are 0, such individuals satisfy the conditions in the limited topology fault detection process, and the fault detection rate is 100%.

Is a fault set H₁Medium network N_iAnd N_jThe fault symptom when the short circuit occurs, if the circuit occurs the line and the short circuit,

∩, indicates a bitwise AND operation, if a wired-OR circuit occurs,

∪ represents bitwise OR operation, the larger the value of F2, the more the case of sign misjudgment between adjacent networks, if F2 of a certain individual is 0, any two networks N which may be short-circuited_i、N_jIs short-circuit fault sign

No misjudgment occurs with the SRV of any network adjacent to the two networks.

F3＝β(N_i1N_j1)+β(N_i2N_j2)+…，β(N_i1,N_j1)、β(N_i2,N_j2) … set of faults H₂The short circuit probability corresponding to the network in which all fault symptoms are subjected to symptom confusion; a larger value for F3 represents H for the fault set₂The larger the number of sign confusion among the sign faults corresponding to the test vectors. If the individual's F3 value is 0, then H is the set of failures₂The failure mode of (1), any symptom of failure of the individual

No sign confusion occurs between them.

S7, generating test vector by using genetic algorithm

S7.1 encoding with MTV as individual

Because the elements of the MTV are Boolean quantities, the invention adopts a binary coding mode, takes the MTV as an individual and takes the elements of the MTV as individual genes. Randomly generating n rows and m columns of Boolean matrixes as an initial test vector set MTV, splitting each row of MTV and then sequentially splicing the split rows into a row to obtain an individual example T:

T＝[STV₁,STV₂,…,STV_n]＝[a₁₁,a₁₂,…,a₂₁,a₂₂,…,a_n1,…,a_nm]

s7.2, initializing genetic algorithm population

If the size of the population is M, then initializing the genetic algorithm population P ═ T₁,T₂,…,T_k,…T_M](ii) a Setting crossover probability of genetic algorithm as P_cThe mutation probability is P_v(ii) a Setting the maximum iteration number as t_maxInitializing the current iteration time t to be 0; if the average fitness threshold of the individuals is F'_end；

S7.3 crossover, variation and population merging

Performing cross and variation treatment on the population, wherein the sequence of individual population is firstly disturbed during the cross treatment, and the population has a probability P_cPerforming analog binary cross processing, and then performing probability P_mPerforming polynomial variation treatment, and marking the population after crossing and variation treatment as Q;

merging the population P and the population Q to obtain a merged population C, wherein C is P ∪ Q, and the number of individuals in the merged population C is 2M;

s7.4, calculating individual fitness value

Calculating the fitness value of each individual in the combined population C by using the fitness function constructed in the step S6; in this embodiment, the fitness value F represents the fault diagnosis capability of the individual, and the smaller the fitness value F is, the stronger the fault diagnosis capability of the individual is.

S7.5, preferred individuals make up the next generation population

Adopting a championship selection algorithm, disordering the sequence of individuals in the combined population C, comparing the fitness values F pairwise, retaining the individuals with small F values in the two individuals, and eliminating the other individual to obtain a next generation population;

s7.6, calculating the average fitness value F' of individuals in the next generation of population;

wherein, F_kThe fitness value of the kth individual in the next generation population;

s7.7, judgment whenWhether the number of previous iterations t reaches the maximum number of iterations t_maxOr whether the individual average fitness value F 'is less than a set threshold value F'_endIf yes, step S7.8 is carried out, otherwise, the current iteration time t is added with 1, and then step S7.3 is carried out again;

s7.8, sequencing the individuals in the next generation population in an ascending order according to the fitness value F, and selecting the individual with the minimum fitness value F as an optimal individual, wherein the optimal individual is the generated boundary scanning interconnection test vector.

Examples of the invention

In order to better explain the technical scheme of the invention, the invention is explained in detail by using a specific example. Fig. 3 is a schematic diagram of an interconnection network of the circuits in this example. Firstly, extracting information of a circuit related file, then, establishing a limited fault model by calculating the short-circuit fault probability of the interconnection network, wherein if the total number n of the interconnection network is 9, m is 4, and a network short-circuit relation table is shown in table 1.

TABLE 1

Set of structural faults H₁: all possible pairwise short-circuit faults form a fault set 1, in this example H₁＝{N₁N₂,N₁N₃,N₁N₄,N₂N₃,N₂N₄,N₂N₅,N₂N₆,N₃N₈,N₄N₈,N₅N₆,N₅N₉,N₆N₇,N₆N₈,N₇N₈,N7₇N₉,N₈N₉In which N is₁N₂Representation network N₁And N₂A short circuit occurs therebetween. Set of faults H₁The fault in (2) is injected into MTV in turn and then measured by a fitness functionF2 values were calculated for individuals.

Building a failure set H₂: obtaining H according to the flow chart shown in FIG. 2₂In this example, H₂＝{N₁N₃,N₈N₉,N₆N₇,N₂N₅H is assumed₂The fault in (2) is simultaneously generated, and is injected into the MTV as a fault mode which is most likely to occur, whether symptom confusion occurs among fault symptoms corresponding to the STVs is judged, and the F3 value of each individual is calculated through a fitness function.

Setting the population size to be 50, randomly generating 50 MTVs with 9 rows and 4 columns by taking the MTVs as individuals, and initializing a genetic algorithm population. The test vector set portion represented by an individual is exemplified as follows:

in actual calculation, each row of the matrix in the example is split and then spliced into a row in sequence to serve as an individual, so that operations such as crossing, mutation and the like are performed.

In this example, when the average fitness value F' <0.001 of the individuals in the population is set or the maximum iteration number is 100 generations, the iteration is ended, and after the iteration is performed by the genetic algorithm defined by the present invention, the obtained test vector set MTV approximates to the optimal solution as follows:

the fitness value F of the MTV is 0, and the network N_iCorresponding test vector is STV_iI is 1,2, …, 9. Wherein, STV₁＝STV₅Network N, according to the constrained topology fault detection theorem, {0,0, 1}, is based on the constrained topology fault detection theorem₁And N₅Has a short-circuit probability of 0, and thus STV₁And STV₅May be the same. The MTV can detect any limited topology fault, and the fault detection rate is 100%. Network N₃And N₄Fault indication of short circuit

And network N₉STV of₉Similarly, under the unrestricted short-circuit fault model, the network N cannot be judged₉Whether a short circuit also occurs, but under a limited fault model, N₉And N₃、N₄The short-circuit probability of (2) is 0, so there is no symptom misjudgment.

The fitness value F of the MTV is 0, and under the limited fault model, the MTV does not have symptom misjudgment and confusion for the faults in the fault set 1 and the fault set 2. Individuals of the genetic algorithm use the improved count sequence algorithm for initialization, a compactness index

However, the MTV obtained by the improved counting sequence algorithm has serious symptom misjudgment and symptom confusion, and the fault diagnosis capability of the MTV finally obtained by the algorithm defined by the invention is far better than that of the MTV obtained by the improved counting sequence algorithm.

The average fitness value F' of the individuals in the population in the example as a function of the number of iterations t is shown in fig. 4. In the figure, the initial population F ' is 0.953, then F ' decreases rapidly with iteration, converging after about 20-30 iterations, and the final F ' value fluctuates in a small range towards 0.

The algorithm defined in the invention has fast convergence, the obtained test vector set has good compactness index and strong fault diagnosis capability, the technical advantages of the algorithm are obvious in boundary scan interconnection test of large-scale circuits, and the test time and the fault diagnosis capability can be taken into consideration.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (1)

1. A method for generating boundary scan interconnection test vectors of large-scale circuits is characterized by comprising the following steps:

(1) extracting characteristic information of the circuit to be tested

Analyzing a netlist file, a BOM file and a BSDL file of a circuit to be tested, and recording the total number of measurable networks in the circuit to be tested and the distance between any two objects on a circuit board in the circuit to be tested; wherein, the total number of measurable networks is recorded as N, the ith measurable network is recorded as N_i，i＝1,2,…,n；

(2) Constructing a test vector set MTV

In boundary scan testing, test vector STV loaded onto ith testable network_iI ═ 1,2, …, n; then STV is used_iForming a Boolean matrix as a row vector, which is called a test vector set MTV;

wherein,

a_nmthe element which represents the nth row and the mth column in the matrix MTV has a Boolean value;

(3) calculating the short-circuit fault probability of the interconnection network in the circuit to be tested

(3.1) calculating fault probability α (P) of any two objects on the circuit board short circuit_m,P_n)；

Wherein, P_mAnd P_nRepresenting two objects on a circuit board, α₀A represents a decay function of the probability of a short-circuit fault with respect to the distance between two objects, L₀Is the minimum distance between two objects, L is the distance between two objects, L_MAs two objectsThe maximum physical distance between the two when short-circuit fault occurs;

(3.2) two networks N interconnected by computational calculation_iAnd N_jProbability of short-circuit failure β (N)_i,N_j)；

(4) Establishing a limited fault model P

(5) Structural failure set

(5.1) constructing a fault set H₁；

H₁＝{N_iN_j|β(N_i,N_j)≠0,β(N_i,N_j)∈P}，

Wherein N is_iN_jRepresentation network N_iAnd N_jShort-circuit fault occurring therebetween, short-circuit fault N_iN_jIs marked as a fault

(5.2) constructing a fault set H₂；

The fault probabilities in the P are sorted in a descending manner, two networks with the maximum short-circuit probability in the P are selected as a group of short-circuit faults, corresponding rows and columns of the two networks in the P are deleted, whether the maximum short-circuit probability in the current P is 0 or not is finally judged, and if not, the two selected networks are added to the H₂Then, continuously selecting two networks with the next highest short-circuit probability and judging again; otherwise, ending the circulation; thereby obtaining H₂Comprises the following steps:

H₂＝{N_i1N_j1,N_i2N_j2,…,N_ixN_jx,…,N_iqN_jq}

wherein q is H₂Middle two short circuitTotal number of fault groups, x is 1,2, …, q, N_ixN_jxRepresenting the x-th group of networks N_ixAnd N_jxShort-circuit fault occurring therebetween, short-circuit fault N_ixN_jxIs marked as a fault

(6) Structural fitness function F

F＝{F0,F1,F2,F3}＝F0+F1+F2+F3

Wherein,

is a fault set H₁Medium network N_iAnd N_jThe fault symptom when the short circuit occurs, if the circuit occurs the line and the short circuit,

∩, indicates a bitwise AND operation, if a wired-OR circuit occurs,

∪ denotes a bitwise OR operation;

F3＝β(N_i1N_j1)+β(N_i2N_j2)+…，β(N_i1,N_j1)、β(N_i2,N_j2) .. is failure set H₂The short-circuit probability corresponding to the network in which the fault symptom is confused;

(7) generating a test vector using a genetic algorithm

(7.1) encoding with MTV as Individual

Splitting each line of the MTV and splicing the split lines into a line in order by adopting a binary coding mode to obtain an individual:

T＝[STV₁,STV₂,…,STV_n]＝[a₁₁,a₁₂,…,a₂₁,a₂₂,…,a_n1,…,a_nm]

(7.2) initializing genetic algorithm population

If the size of the population is M, then initializing the genetic algorithm population P ═ T₁,T₂,…,T_k,…T_M](ii) a Setting crossover probability of genetic algorithm as P_cThe mutation probability is P_v(ii) a Setting the maximum iteration number as t_maxInitializing the current iteration time t to be 0; if the average fitness threshold of the individuals is F'_end；

(7.3) crossover, variation and population merging

Performing cross and variation treatment on the population, wherein the sequence of individual population is firstly disturbed during the cross treatment, and the population has a probability P_cPerforming analog binary cross processing, and then performing probability P_vPerforming polynomial variation treatment, and marking the population after crossing and variation treatment as Q;

merging the population P and the population Q to obtain a merged population C, wherein C is P ∪ Q, and the number of individuals in the merged population C is 2N;

(7.4) calculating the individual fitness value

Calculating the fitness value of each individual in the combined population C by using the fitness function constructed in the step (6);

(7.5) preferred individuals make up the next generation population

Adopting a championship selection algorithm, disordering the sequence of individuals in the combined population C, comparing fitness values F pairwise, retaining individuals with small F values, and eliminating individuals with large F values to obtain a next generation population;

(7.6) calculating the average fitness value F' of individuals in the next generation of population;

wherein, F_kThe fitness value of the kth individual in the next generation population;

(7.7) judging whether the current iteration time t reaches the maximum iteration time t_maxOr whether the individual average fitness value F 'is less than a set threshold value F'_endIf yes, entering the step (7.8), otherwise, adding 1 to the current iteration time t, and returning to the step (7.3);

and (7.8) sequencing the individuals in the next generation population in an ascending order according to the fitness value F, and selecting the individual with the minimum fitness value F as an optimal individual, wherein the optimal individual is the generated boundary scanning interconnection test vector.

Images