Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for controlling frame loss in video extraction, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a method for controlling frame loss in video extraction, including:
monitoring the VGA to write video data into the memory;
acquiring a frame rate of video extraction;
judging whether the interval between the currently read image frame and the recently extracted image frame meets the frame rate:
if yes, extracting the currently read image frame and storing the image frame to a cache device;
and if not, discarding the currently read image frame.
Further, the monitoring VGA writes video data into the memory, including:
monitoring whether the VGA writes video data into the memory:
if yes, judging that the conditions for executing video extraction are met;
if not, the condition for executing the video extraction is judged not to be available.
Further, the method further comprises:
when the image frame reading signal is 0, writing a Header mark into the cache device;
and writing an End mark into the buffer device when the image frame reading signal is the frame rate number.
Further, the method further comprises:
setting a data storage range of a cache device;
acquiring the data volume currently stored by the cache equipment;
comparing the data volume with the data storage range:
if the data volume is higher than the maximum limit value of the data storage range, stopping reading the video data in the memory;
and if the data volume is lower than the minimum limit value of the data storage range, judging whether to stop video extraction, and if not, starting to read the video data in the memory.
In a second aspect, the present invention provides a video extraction frame loss control system, including:
the memory monitoring unit is configured for monitoring the VGA to write video data into the memory;
a frame rate acquisition unit configured to acquire a frame rate of video extraction;
the frame rate judging unit is configured to judge whether the interval between the currently read image frame and the recently extracted image frame meets the frame rate;
the image frame storage unit is configured to extract the currently read image frame and store the currently read image frame to the cache device if the interval between the currently read image frame and the recently extracted image frame meets the frame rate;
and the image frame discarding unit is configured to discard the currently read image frame if the interval between the currently read image frame and the recently extracted image frame does not meet the frame rate.
Further, the memory monitoring unit includes:
the memory monitoring module is configured for monitoring whether the VGA writes video data into the memory;
the extraction preparation module is configured for judging that a condition for executing video extraction is met if the VGA writes video data into the memory;
and the extraction negation module is configured to judge that the condition for executing the video extraction is not met if the VGA does not write the video data into the memory.
Further, the system further comprises:
the frame Header insertion unit is configured to write a Header mark into the cache device when the image frame reading signal is 0;
and the frame tail insertion unit is configured to write the End mark into the buffer device when the image frame reading signal is the frame rate number.
Further, the system further comprises:
the range setting unit is used for setting the data storage range of the cache equipment;
the quantity acquisition unit is configured to acquire the data quantity currently stored by the cache device;
the data comparison unit is configured to compare the data volume with the data storage range;
the reading stopping unit is configured to stop reading the video data in the memory if the data volume is higher than the maximum limit value of the data storage range;
and the reading starting unit is configured to judge whether to stop video extraction if the data volume is lower than the minimum limit value of the data storage range, and start to read the video data in the memory if the video extraction is not stopped.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the video extraction frame loss control method, the video extraction frame loss control system, the video extraction frame rate control terminal and the storage medium provided by the invention can be used for acquiring the frame rate of video extraction after monitoring that VGA writes video data into the memory, and determining to keep or discard the currently read image frame by judging whether the interval between the currently read image frame and the recently extracted image frame meets the frame rate. The invention realizes the effective control of active frame loss by controlling the frame loss of the video extraction according to the frame rate, and effectively prevents the blocking of video compression.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms used in the present invention are to be interpreted.
VGA: video graphics array Video image array
AXI: advanced eXtensible Interface high-performance expansion bus
FIFO: first Input First Output cache
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The implementation body in fig. 1 may be a video extraction frame loss control system.
As shown in fig. 1, the method 100 includes:
step 110, monitoring the VGA to write video data into the memory;
step 120, acquiring a frame rate of video extraction;
step 130, determining whether the interval between the currently read image frame and the recently extracted image frame satisfies the frame rate:
step 140, if yes, extracting the currently read image frame and storing the image frame in a cache device;
and 150, if not, discarding the currently read image frame.
In order to facilitate understanding of the present invention, the video extraction frame loss control method provided by the present invention is further described below by using the principle of the video extraction frame loss control method of the present invention and combining the process of performing frame loss control on video extraction in the embodiment.
Specifically, the video extraction frame loss control method includes:
and S1, the monitoring VGA writes the video data into the memory.
The video extraction process of the invention reads the video data in the memory through the AXI high-performance expansion bus, the memory end of the high-performance expansion bus is AXI slave, and the AXI master initiates active communication to the AXI slave through the AXI master end of the high-performance expansion bus, thereby reading the video data in the memory.
And monitoring whether the VGA writes video data into the memory or not, if the VGA starts to write data into the memory, receiving a cap _ start signal, indicating that a condition for executing video extraction is met, and starting to execute the video extraction, otherwise, not executing the video extraction.
And S2, acquiring the frame rate of video extraction.
And extracting the frame rate of video extraction from the received video extraction instruction. The AXI Master module starts to form an address according to the resolution information (resolution _ num/base _ address/size/frame _ rate) transmitted by the control module and initiates an AXI Read operation.
S3, judging whether the interval between the currently read image frame and the recently extracted image frame meets the frame rate: if yes, extracting the currently read image frame and storing the image frame in a buffer device (FIF 0); and if not, discarding the currently read image frame.
Each time one data is read, the read data number counter cap _ cnt is incremented by one, indicating the number of data currently read. Then, according to the frame rate frame _ rate extracted in step S2, it is determined whether the interval between the currently read image frame and the most recently extracted image frame satisfies the frame rate to determine whether the currently read frame is lost, and if so, the write enable signal FIFO _ wen of the FIFO is set to 0, and the writing of data into the FIFO is prohibited, but at this time, the AXI still performs the operation of reading the memory data. And if the current frame does not need to be dropped, storing the current frame into the FIFO.
And S4, inserting the frame head and the frame tail.
When the reading of the memory data is started, when the cap _ cnt is equal to 0, the operation of writing the FIFO is controlled, a Header flag is written into the FIFO to indicate the start of a frame, and then the data read by the AXI bus is written into the FIFO. When the cap _ cnt is equal to the resolution number (resolution _ num), the FIFO write is controlled to write an End flag into the FIFO, indicating the End of a frame. After inserting the frame head and tail mark into the FIFO, the AXI Master continues to read the memory data.
S5, writing data into the FIFO under the AXI clock domain, reading data from the FIFO under the system clock domain and inputting the read data to the video compression module. Let FIFO _ num indicate the amount of data present in the current output FIFO. Two thresholds are set at this time, Max _ throdhold and Min _ throdhold, representing the thresholds for FIFO _ num being full and empty immediately, respectively. When the data quantity FIFO _ num in the FIFO is larger than Max _ throdhold, which indicates that the FIFO reading speed of the subsequent module is slower than the data writing speed of the AXI Master to the FIFO, the memory reading action of the AXI Master is stopped at this time, and the data are not written into the FIFO. When the subsequent module continuously reads the data in the FIFO and the number of FIFO _ num in the current FIFO is less than Min _ throdhold, it indicates that the subsequent module is about to read the FIFO empty immediately, and at this time, the operation of reading the memory data by the AXI Master is restarted. And then, judging whether the operation of stopping video extraction is received or not, if the operation is stopped, ending the whole flow, and if the operation is not ended, continuing the operation of reading the memory of the AXI Master.
As shown in fig. 2, the system 200 includes:
the memory monitoring unit 210 is configured to monitor writing of video data into the memory by the VGA;
a frame rate obtaining unit 220 configured to obtain a frame rate of video extraction;
a frame rate determining unit 230 configured to determine whether an interval between the currently read image frame and the most recently extracted image frame satisfies the frame rate:
an image frame saving unit 240 configured to extract the currently read image frame and save the currently read image frame to a cache device if the interval between the currently read image frame and the most recently extracted image frame meets the frame rate;
the image frame dropping unit 250 is configured to drop the currently read image frame if the interval between the currently read image frame and the most recently extracted image frame does not satisfy the frame rate.
Optionally, as an embodiment of the present invention, the memory monitoring unit includes:
the memory monitoring module is configured to monitor whether the VGA writes video data into the memory:
the extraction preparation module is configured for judging that a condition for executing video extraction is met if the VGA writes video data into the memory;
and the extraction negation module is configured to judge that the condition for executing the video extraction is not met if the VGA does not write the video data into the memory.
Optionally, as an embodiment of the present invention, the system further includes:
the frame Header insertion unit is configured to write a Header mark into the cache device when the image frame reading signal is 0;
and the frame tail insertion unit is configured to write the End mark into the buffer device when the image frame reading signal is the frame rate number.
Optionally, as an embodiment of the present invention, the system further includes:
the range setting unit is used for setting the data storage range of the cache equipment;
the quantity acquisition unit is configured to acquire the data quantity currently stored by the cache device;
the data comparison unit is configured to compare the data volume with the data storage range;
the reading stopping unit is configured to stop reading the video data in the memory if the data volume is higher than the maximum limit value of the data storage range;
and the reading starting unit is configured to judge whether to stop video extraction if the data volume is lower than the minimum limit value of the data storage range, and start to read the video data in the memory if the video extraction is not stopped.
Fig. 3 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be used to execute the video extraction frame loss control method according to the embodiment of the present invention.
The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention acquires the frame rate of video extraction after monitoring that the VGA writes video data into the memory, and determines to keep or discard the currently read image frame by judging whether the interval between the currently read image frame and the recently extracted image frame meets the frame rate. According to the invention, the effective control of active frame loss is realized by controlling the frame loss of the video extraction according to the frame rate, and the blocking of video compression is effectively prevented.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.