CN111276538A

CN111276538A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN111276538A
Application number: CN201811474472.5A
Authority: CN
Inventors: 陈志谚
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2018-12-04
Filing date: 2018-12-04
Publication date: 2020-06-12
Anticipated expiration: 2038-12-04
Also published as: CN111276538B

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The channel layer, the first barrier layer and the second barrier layer are sequentially stacked on the substrate. The source electrode, the drain electrode, and the gate structure extend through at least a portion of the second barrier layer. The source electrode, the drain electrode, and the gate structure have respective bottom surfaces at substantially the same level and adjacent to the first barrier layer. The invention can avoid channel coupling effect and reduce channel resistance of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to semiconductor devices, and more particularly, to a high electron mobility transistor and a method of manufacturing the same.

Background

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap (band-gap), and high electron saturation rate. Therefore, the gallium nitride based semiconductor material is suitable for high speed and high temperature operation environment. In recent years, gallium nitride-based semiconductor materials have been widely used in Light Emitting Diode (LED) devices, high frequency devices such as High Electron Mobility Transistors (HEMTs) having a hetero-interface structure, and the like.

On-resistance (R)_on) The resistance value is positive as an important factor affecting the power consumption of the semiconductor deviceCompared to the power consumption of the semiconductor device. The on-resistance (Ron) includes a source/drain contact resistance (R)_contact) And channel resistance (R)_channel). A two-dimensional electron gas (2 DEG) having high electron mobility and high carrier density is formed on the hetero-interface, so that the High Electron Mobility Transistor (HEMT) has a low channel resistance. The magnitude of the source/drain contact resistance of the hemt will affect the overall performance of the on-resistance.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are applied in more severe operating environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, the process conditions for fabricating gallium nitride based semiconductor devices also face many new challenges.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device capable of preventing channel coupling effects and reducing channel resistance of the semiconductor device, the semiconductor device including a channel layer disposed on a substrate, a first barrier layer disposed on the channel layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device also includes a source electrode extending at least partially through the second barrier layer, a drain electrode, and a gate structure interposed between the source electrode and the drain electrode. The source electrode, the drain electrode, and the gate structure have respective bottom surfaces at substantially the same level and adjacent to the first barrier layer.

Some embodiments of the present invention provide methods of fabricating a semiconductor device that can avoid channel coupling effects and reduce channel resistance of the semiconductor device, the method comprising sequentially forming a channel layer, a first barrier layer, and a second barrier layer on a substrate, recessing the second barrier layer and the first barrier layer to form a source recess, a drain recess, and a gate recess between the source recess and the drain recess at least through a portion of the first barrier layer, and forming a source electrode, a drain electrode, and a gate structure in the source recess, the drain recess, and the gate recess, respectively. The source recess, the drain recess, and the gate recess have respective bottom surfaces located at substantially the same horizontal level.

In the embodiment of the invention, the source electrode recess, the drain electrode recess and the grid electrode recess are formed at the same time to have respective bottom surfaces which are positioned at the same horizontal height, so that the channel coupling effect is avoided, the channel resistance of the semiconductor device is reduced, and the difference of the channel resistance among the semiconductor devices in different regions is reduced.

In order to make the features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in detail below.

Drawings

Embodiments of the invention will be understood more fully from the detailed description and examples that follow, taken in conjunction with the accompanying drawings. In order to make the drawings clearly show, various elements in the drawings may not be drawn to scale, wherein:

FIG. 1 is a schematic cross-sectional view of a semiconductor device in different areas of a substrate according to some embodiments of the present invention;

FIGS. 2A-2G are schematic cross-sectional views illustrating the formation of a semiconductor device at various stages of processing, in accordance with some embodiments of the present invention;

fig. 3 and 4 are schematic cross-sectional views of semiconductor devices according to further embodiments of the present invention.

The symbols of the attached drawings:

10A, 10B, 100, 200, 300-semiconductor device;

12. 102-a substrate;

14. 104-a buffer layer;

16. 106-channel layer;

18. 110 to the second barrier layer;

20A, 20B, 114-source recess;

22A, 22B, 116-a drain recess;

24A, 24B, 118-Gate recesses;

26A, 26B, 122-source electrode;

28A, 28B, 124-drain electrode;

30A, 30B, 130-gate structure;

50A to a first zone;

50B to the second zone;

108 to the first barrier layer;

112 to a cover layer;

120 to a lining layer;

126 dielectric layer;

128-gate electrode;

132-interlayer dielectric layer;

134 to a contact element;

d1, D1' first etch depth;

d2, D2' to a second etch depth;

d3 and D4.

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing various components of the provided semiconductor devices. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional steps may be provided before, during, or after the method, and that some of the recited steps may be substituted or deleted for other embodiments of the method.

Referring to fig. 1, fig. 1 is a cross-sectional view of a semiconductor device 10A and a semiconductor device 10B in different areas of a substrate 12 according to some embodiments of the present invention. In this embodiment, the

semiconductor devices

10A and 10B are high electron mobility transistors.

Referring to fig. 1, a substrate 12 is provided, the substrate 12 including a plurality of regions, for example, a first region 50A and a second region 50B. Although not shown, the substrate 12 may include any other regions. A buffer layer 14, a channel layer 16, and a barrier layer 18 are sequentially formed on a substrate 12. The heterointerface between the channel layer 16 and the barrier layer 18 may generate a two-dimensional electron gas that serves as a conductive carrier for the

semiconductor devices

10A and 10B. In some embodiments, the material of the channel layer 16 may be a binary (binary) group III-V compound semiconductor, such as GaN. The material of barrier layer 18 may be a ternary group III-V compound semiconductor, such as AlGaN. In general, the two-dimensional electron gas exists in a lateral direction parallel to the hetero interface, and hardly exists in a longitudinal direction perpendicular to the hetero interface.

Next, a source recess 20A and a drain recess 22A are formed in the first region 50A, and a source recess 20B and a drain recess 22B are formed in the second region 50B by a first etching process. The source recesses 20A, 20B and

drain recesses

22A, 22B pass through the barrier layer 18 and extend into the channel layer 16. The source recess 20A and the drain recess 22A in the first region 50A have a first etch depth D1, while the source recess 20B and the drain recess 22B in the second region 50B have a first etch depth D1'. The etch depth in different regions of the substrate 12 may have a degree of variation (i.e., etch depth uniformity), for example, the first etch depth D1 in the first region 50A may not be equal to the first etch depth D1' in the second region 50B, depending primarily on the capabilities of the etch process.

Next, a source electrode 26A and a drain electrode 28A are formed in the source recess 20A and the drain recess 22A, respectively, and a source electrode 26B and a drain electrode 28B are formed in the source recess 20B and the drain recess 22B, respectively.

Next, a gate recess 24A is formed in the first region 50A and a gate recess 24B is formed in the second region 50B by a second etching process. Gate recesses 24A and 24B pass through barrier layer 18 and extend into channel layer 16. The gate recess 24A of the first region 50A has a second etch depth D2, and the gate recess 24B of the second region 50B has a second etch depth D2'. Similarly, the second etching depth D2 in the first region 50A may not be equal to the second etching depth D2' in the second region 50B.

Next, a gate structure 30A is formed in gate recess 24A, and a gate structure 30B is formed in gate recess 24B. After the

gate structures

30A and 30B are formed, the

semiconductor devices

10A and 10B are formed.

It is noted that when the semiconductor device is operating, a current E or E' flows from the drain electrode to the source electrode. The two-dimensional electron gas is hardly present on the longitudinal path of the current E or E' (indicated by a dotted line), which results in an increase in the contact resistance of the drain to the source of the semiconductor device, along with an increase in the overall on-resistance of the semiconductor device.

Furthermore, the source recess and the drain recess are formed by a first etching process, and the gate recess is formed by a second etching process, so that the bottom surfaces of the formed source and drain electrodes and the bottom surface of the gate electrode may not be located at the same level. The difference in the level of the bottom surface causes a channel coupling effect, which further increases the channel resistance of the semiconductor device. Furthermore, the two etching processes have respective etching uniformity, which results in an increased difference in channel resistance between the semiconductor devices (e.g., the semiconductor device 10A and the semiconductor device 10B) in different regions, thereby reducing the manufacturing stability of the semiconductor devices.

Fig. 2A-2G are schematic cross-sectional views illustrating the formation of the semiconductor device 100 shown in fig. 2G at various stages of processing, in accordance with some embodiments of the present invention. In the embodiment of fig. 2A-2G, the source recess, the drain recess, and the gate recess are formed simultaneously by an etching process to have respective bottom surfaces at substantially the same horizontal level. Therefore, the channel coupling effect is avoided, the channel resistance of the semiconductor device is reduced, and the difference in channel resistance between the semiconductor devices of different regions is reduced.

Referring to fig. 2A, a substrate 102 is provided. In some embodiments, the substrate 102 may be a doped (e.g., doped with P-type or N-type dopants) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or the like. In some embodiments, the substrate 102 may be a semiconductor-on-insulator substrate, such as a Silicon On Insulator (SOI) substrate. In some embodiments, the substrate 102 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Sapphire (Sapphire) substrate.

A buffer layer 104, a channel layer 106, a first barrier layer 108, a second barrier layer 110, and a cap layer 112 are sequentially formed on a substrate 102. In some embodiments, a seed layer (not shown) may be formed between the substrate 102 and the buffer layer 104.

The buffer layer 104 may relieve strain (strain) in the channel layer 106 subsequently formed over the buffer layer 104 to prevent defects from forming in the channel layer 106, the strain being caused by mismatch between the channel layer 106 and the substrate 102. In some embodiments, the material of the buffer layer 104 may comprise or be AlN, GaN, AlGaN, AlInN, combinations of the foregoing, or the like. The buffer layer 104 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like. Although the buffer layer 104 has a single-layer structure in the embodiment shown in fig. 2A, the buffer layer 104 may have a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 104 is determined by the material of the seed layer and the gas introduced during the epitaxial process.

In some embodiments, the material of the channel layer 106 may comprise a binary group III-V compound semiconductor material, such as a group III nitride. In some embodiments, the material of the channel layer 106 is GaN. In some embodiments, the thickness of the channel layer 106 may be in a range from about 0.01 micrometers (μm) to about 10 micrometers. In some embodiments, the channel layer 106 may have a dopant, such as an N-type dopant or a P-type dopant. The channel layer 106 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations thereof, or the like.

In some embodiments, the material of the first barrier layer 108 may comprise a binary group III-V compound semiconductor material, such as aluminum nitride. In some embodiments, the first barrier layer 108 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations thereof, or the like. In some embodiments, the thickness of the first barrier layer 108 is in a range from about 0.5 nanometers (nm) to about 10 nm, such as 2 nm. The first barrier layer 108 may also serve as an etch stop layer, as will be described in more detail below.

In some embodiments, the material of the second barrier layer 110 may comprise a ternary (ternary) group III-V compound semiconductor, such as a group III nitride. In some embodiments, the material of the second barrier layer 110 can be AlGaN, AlInN, or a combination thereof. In some embodiments, the second barrier layer 110 can have a dopant, such as an n-type dopant or a p-type dopant. The second barrier layer 110 can be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like. In some embodiments, the thickness of the second barrier layer 110 is greater than the thickness of the first barrier layer 108, and the thickness of the second barrier layer 110 is in the range of about 1 nanometer to about 80 nanometers.

Two-dimensional electron gas (not shown) is formed at the hetero-interface between the channel layer 106 and the first barrier layer 108 by spontaneous polarization and piezoelectric polarization effects induced by different energy bands between the channel layer 106 and the first and second barrier layers 108 and 110. The semiconductor device 100 shown in fig. 2G is a high electron mobility transistor using a two-dimensional electron gas as a conductive carrier. In addition, the material selection of the first barrier layer 108 for the binary iii-v compound semiconductor may cause lower alloy scattering (alloy scattering) than for the ternary iii-v compound semiconductor, and may form a two-dimensional electron gas with higher electron mobility, thereby reducing the channel resistance of the semiconductor device.

In some embodiments, the material of the cap layer 112 may comprise or be gallium nitride (GaN), such as undoped gallium nitride. In some embodiments, a cap layer 112 is disposed on the second barrier layer 110 to prevent oxidation of the surface of the second barrier layer 110 containing aluminum (Al). In some embodiments, the thickness of the cap layer 112 is in a range from about 1 nanometer to about 100 nanometers. In some embodiments, the cap layer 112 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations thereof, or the like.

In some embodiments, the buffer layer 104, the channel layer 106, the first barrier layer 108, the second barrier layer 110, and the cap layer 112 may be deposited in-situ (in-situ) in the same deposition chamber.

Next, a patterning process is performed on the cap layer 112, the second barrier layer 110, and the first barrier layer 108.

Referring to fig. 2B, the cap layer 112, the second barrier layer 110, and the first barrier layer 108 are etched back by a patterning process to form a source recess 114, a drain recess 116, and a gate recess 118 through the cap layer 112, the second barrier layer 110, and the first barrier layer 108, the gate recess 118 being between the source recess 114 and the drain recess 116. After the patterning process, the source recess 114, the drain recess 116, and the gate recess 118 expose an upper surface of a portion of the channel layer 106.

In some embodiments, the patterning process performed on the cap layer 112, the second barrier layer 110, and the first barrier layer 108 includes forming a patterned mask layer (not shown) over the cap layer 112, wherein the patterned mask layer has an opening exposing a portion of the upper surface of the cap layer 112, performing an etching process through the opening of the patterned mask layer on the cap layer 112, the second barrier layer 110, and the first barrier layer 108, removing the cap layer 112, the second barrier layer 110, and the portion of the first barrier layer 108 not covered by the patterned mask layer to simultaneously form the source recess 114, the drain recess 116, and the gate recess 118, and then removing the patterned mask layer, for example, by an ashing (ashing) process or a stripping process. In some embodiments, the etching process may be a dry etching process, such as Reactive Ion Etching (RIE), electron cyclotron resonance (ERC) etching, Inductively Coupled Plasma (ICP) etching, Neutron Beam Etching (NBE), a combination thereof, or the like.

In the embodiment of the present invention, the source recess 114, the drain recess 116, and the gate recess 118 are simultaneously formed through one etching process, so that the source recess 114, the drain recess 116, and the gate recess 118 may have respective bottom surfaces having substantially the same horizontal height.

Here, the term "substantially the same level" means that the level difference of the bottom surfaces of the

recesses

114, 116, 118 is in the range of 2 nm, or in the range of 1 nm, or in the range of 0.5 nm. Alternatively, the term "substantially the same level" means that the level difference of the bottom surfaces of the

recesses

114, 116, 118 is within 5% of the depth of the recess 114.

The first barrier layer 108 may act as an etch stop layer. For example, in some embodiments, the first barrier layer 108 comprises aluminum nitride (AlN) and the second barrier layer 110 comprises aluminum gallium nitride (AlGaN). In the etching process, the second barrier layer 110 has a higher etching rate than the first barrier layer 108. For example, in an etching process performed with Cl2 or SF6 as the etchant, the ratio of the etching rate of the second barrier layer 110 to the etching rate of the first barrier layer 108 is in the range of about 1.5 to about 50. The first barrier layer 108 slows the etch rate of the etching process to control the locations where the bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 stop. Thus, after the etching process, the source recess 114, the drain recess 116, and the gate recess 118 just pass through the first barrier layer 108, but do not extend into the channel layer 106. In other words, the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 have a level equal to that of the bottom surface of the first barrier layer 108.

Although the embodiment of fig. 2B shows the

recesses

114, 116, 118 to pass through the first barrier layer 108, but not extend into the channel layer 106, the embodiment of the invention is not limited thereto. In other embodiments, the

recesses

114, 116, 118 may extend slightly into the channel layer 106 (as shown in fig. 3). In other embodiments, the

recesses

114, 116, 118 may only penetrate a portion of the first barrier layer 108 without exposing the channel layer 106 (as shown in fig. 4).

Referring to fig. 2C, a liner 120 is conformally formed on the upper surface of the cap layer 112 and in the source recess 114, the drain recess 116, and the gate recess 118. Liner 120 is conformably formed on the bottom surfaces and sidewalls of source recess 114, drain recess 116, and gate recess 118, and partially fills source recess 114, drain recess 116, and gate recess 118. In some embodiments, the thickness of liner 120 may be in a range from about 0.5 nanometers to about 4 nanometers, such as 2 nanometers. In some embodiments, the material of the liner 120 may comprise or be a hexagonal crystal binary compound semiconductor, such as aluminum nitride (AlN), zinc oxide (ZnO), indium nitride (InN), combinations thereof, or the like, and the liner 120 may be formed globally over the substrate 102 by Atomic Layer Deposition (ALD) or epitaxial growth processes, such as metal organic chemical vapor deposition.

Referring to fig. 2D, a source electrode 122 and a drain electrode 124 are formed on the liner 120 in respective remaining portions of the source recess 114 and the drain recess 116. The source electrode 122 has an upper portion located above the upper surface of the cap layer 112 and a lower portion located in the source recess 114. The drain electrode 124 has an upper portion located above the upper surface of the cap layer 112. And a lower portion located in the drain recess 116.

In some embodiments, the material of the source and drain

electrodes

122 and 124 may comprise or be a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination of the foregoing. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), combinations of the foregoing, alloys of the foregoing, or multilayers of the foregoing. The semiconductor material may be polysilicon or poly-germanium. In some embodiments, the step of forming the source and drain

electrodes

122 and 124 may include depositing a conductive material (not shown) for the source and drain

electrodes

122 and 124 over the substrate 102 and filling the remaining portions of the source recess 114 and the drain recess 116, and performing a patterning process on the conductive material to form the source and drain

electrodes

122 and 124. The deposition process to form the conductive material may be atomic layer deposition, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), such as sputtering, combinations of the foregoing, or the like.

Referring to fig. 2E, a dielectric layer 126 is conformally formed on the liner 120 in the remaining portion of the gate recess 118 to serve as a gate dielectric layer. A dielectric layer 126 is also formed on the liner layer 120 over the upper surface of the cap layer 120. A dielectric layer 126 is also formed on the upper surface and sidewalls of the source electrode 122 and the upper surface and sidewalls of the drain electrode 124. In some embodiments, the material of the dielectric layer 126 may comprise or be silicon oxide (SiO)₂) Silicon nitride (SiN), aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) A combination thereof, multiple layers thereof, or the like, and the dielectric layer 126 may be formed globally over the substrate 102 by atomic layer deposition, chemical vapor deposition, physical vapor deposition, such as sputtering.

Referring to fig. 2F, a gate electrode 128 is formed on the dielectric layer 126 in the remaining portion of the gate recess 118. Gate electrode 128 has an upper portion located above the upper surface of cap layer 112 and a lower portion located in gate recess 118. The gate electrode 128 and the dielectric layer 126 together serve as a gate structure 130. In some embodiments, the material of the gate electrode 128 may comprise or be a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination of the foregoing. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), combinations of the foregoing, alloys of the foregoing, or multilayers of the foregoing. The semiconductor material may be polysilicon or poly-germanium. The step of forming the gate electrode 128 may include depositing a layer of conductive material (not shown) for the gate electrode 128 over the substrate 102 and performing a patterning process on the layer of conductive material to form the gate electrode 128. The deposition process to form the conductive material may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, such as sputtering, a combination of the foregoing, or the like.

Referring to fig. 2G, an interlayer dielectric (ILD) layer 132 is formed on the substrate 102, and the ILD layer 132 covers the gate structure 130, the source electrode 122, and the drain electrode 124. Next, a plurality of contacts 134 are formed in the interlayer dielectric layer 132, and the contacts 134 are electrically connected to the gate structure 130, the source electrode 122 and the drain electrode 124, respectively.

In some embodiments, the material of the interlayer dielectric layer 132 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a combination thereof, multiple layers thereof, or the like. The interlayer dielectric layer 132 may be formed globally over the substrate 102 by chemical vapor deposition, such as plasma-enhanced CVD (PECVD), atomic layer deposition, or the like.

In some embodiments, the material of the contact 134 may be a metal material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations thereof, or multilayers thereof. The step of forming the contact 134 may include forming a plurality of openings (not shown) through the interlayer dielectric layer 132 and the dielectric layer 126 over the source and drain

electrodes

122, 124 and exposing portions of the upper surfaces of the source, drain and

gate electrodes

122, 124 and 128 by a patterning process, depositing a metal material (not shown) on the interlayer dielectric layer 132 and filling the openings, and performing a planarization process such as Chemical Mechanical Polishing (CMP) to remove portions of the metal material over the interlayer dielectric layer 130.

After the interlayer dielectric layer 132 and the contact 134 are formed, the semiconductor device 100 is formed. The semiconductor device 100 may also be referred to as a metal-insulator-semiconductor field effect transistor (MIS-FET).

In the embodiment shown in fig. 2A-2G, the semiconductor device 100 includes a channel layer 106, a first barrier layer 108, and a second barrier layer 110 sequentially stacked on a substrate 102. The semiconductor device 100 also includes a source electrode 122, a drain electrode 124, and a gate structure 130 interposed between the source electrode 122 and the drain electrode 124. The source electrode 124, the drain electrode 124, and the gate structure 130 extend at least partially through the second barrier layer 110. The source electrode 124, the drain electrode 124, and the gate structure 130 have respective bottom surfaces that are located at substantially the same horizontal level. The semiconductor device 100 also includes a liner 120 conformally disposed on respective lower portions of the source electrode 122, the drain electrode 124, and the gate structure 130. The level of the bottom surface of the liner layer 120 is equal to the level of the bottom surface of the first barrier layer 108.

In the embodiment shown in fig. 2A-2G, the

recesses

114, 116, and 118 used to form the source electrode 122, the drain electrode 124, and the gate structure 130 penetrate the first and second barrier layers 108 and 110 such that the hetero-interface between the first barrier layer 108 and the channel layer 106 does not exist in this region, thereby reducing or eliminating the two-dimensional electron gas formed beneath the source electrode 122, the drain electrode 124, and the gate structure 130. It is noted that, since the liner 120 comprises the hexagonal binary compound semiconductor and the liner 120 is formed between the bottom of the source electrode 122, the drain electrode 124, and the gate structure 130 and the channel layer 106, spontaneous polarization and piezoelectric polarization effects can be induced between the liner 120 and the channel layer 106 to recover the two-dimensional electron gas reduced by the disappearance of the aforementioned heterointerface. Accordingly, the liner layer 120 may serve as a two-dimensional electron gas recovery (2 degreemerge) layer to improve contact resistance between the source and drain

electrodes

122 and 124 and the channel layer 106 and improve on-resistance under the gate structure 130.

In addition, in the embodiment shown in fig. 2A-2G, the source recess 114, the drain recess 116, and the gate recess 118 are formed simultaneously by an etching process, which reduces the difference in channel resistance between the semiconductor devices in different regions, thereby improving the manufacturing stability of the semiconductor devices. Furthermore, the gate recess formed by one patterning process is reduced, which not only improves the manufacturing efficiency of the semiconductor device, but also reduces the damage of chemicals (such as photoresist or developer in the patterning process) to the gate structure, thereby improving the performance of the semiconductor device 100.

Furthermore, the source recess 114, the drain recess 116, and the gate recess 118 have respective bottom surfaces that are at substantially the same level, which avoids the channel coupling effect described with reference to fig. 1, thereby reducing the channel resistance of the semiconductor device and thus enhancing the performance of the semiconductor device 100.

Further, the first barrier layer 108 is disposed between the channel layer 106 and the second barrier layer 110 to serve as an etch stop layer such that the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 have a level equal to that of the bottom surface of the first barrier layer 108. Therefore, when the semiconductor device 100 operates, the current E flowing from the drain electrode 124 to the source electrode 122 may be a horizontal path parallel to the hetero interface, and hardly have a vertical path perpendicular to the hetero interface, which further reduces the channel resistance of the semiconductor device 100.

The embodiments shown in fig. 2A-2G are exemplary, and the invention is not limited thereto. In addition to the embodiments shown in fig. 2A-2G, the methods of the embodiments of the present invention may also be applied to other semiconductor devices.

Fig. 3 is a cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention, wherein the same reference numerals are used for the same components as those in the embodiments of fig. 2A to 2G, and the description thereof is omitted. The difference between the embodiment shown in fig. 3 and the embodiment of fig. 2G is that the liner layer 120 in the source recess 114, the drain recess 116, and the gate recess 118 of fig. 3 has a lower bottom level than the first barrier layer 108.

Referring to fig. 3, the cap layer 112, the second barrier layer 110, the first barrier layer 108, and the channel layer 106 are recessed by a patterning process similar to that described above with reference to fig. 2B to form a source recess 114, a drain recess 116, and a gate recess 118 that pass through the cap layer 112, the second barrier layer 110, and the first barrier layer 108 and further extend into the channel layer 106 to a dimension D3, for example, in a range from about 1 nm to about 50 nm.

In the embodiment of fig. 3, the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 have a level slightly lower than the level of the bottom surface of the first barrier layer 108. Therefore, when the semiconductor device 200 operates, the current E flowing from the drain electrode 124 to the source electrode 122 has a longitudinal path perpendicular to the hetero interface, so that the channel resistance (Rchannel) of the semiconductor device 200 is slightly higher than that of the semiconductor device 100 shown in fig. 2G. However, the etching process extends the

recesses

116, 118, and 120 into the channel layer 106 to generate a deeper etching depth, so that the

recesses

116, 118, and 120 in different regions of the substrate 102 may have better etching depth uniformity (i.e., a lower uniformity value). The better uniformity of the etch depth reduces the difference in channel resistance between different regions of the substrate 102 for the semiconductor device, thereby improving the manufacturing stability of the semiconductor device.

Fig. 4 is a cross-sectional view of a semiconductor device 300 according to another embodiment of the present invention, wherein the same reference numerals are used for the same components as those in the embodiments of fig. 2A to 2G, and the description thereof is omitted. The difference between the embodiment shown in fig. 4 and the embodiment of fig. 2G is that the liner layer 120 in the source recess 114, the drain recess 116, and the gate recess 118 of fig. 4 has a bottom surface with a height level higher than that of the first barrier layer 108. In detail, the bottom surfaces of the

recesses

114, 116 and 118 have a horizontal height between the bottom surface and the top surface of the first barrier layer 108.

Referring to fig. 4, the cap layer 112, the second barrier layer 110, and the first barrier layer 108 are etched back by a patterning process similar to that described above with reference to fig. 2B to form a source recess 114, a drain recess 116, and a gate recess 118 through the cap layer 112, the second barrier layer 110, and a portion of the first barrier layer 108. The bottom surfaces of the

recesses

114, 116, and 118 stop in the first barrier layer 108, and the portion of the first barrier layer 108 under the

recesses

114, 116, and 118 has a dimension D4, for example, in a range of about 0.5 nanometers to about 5 nanometers. After the etching process of the patterning process, the bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 are higher than the bottom surface of the first barrier layer 108 in level.

In summary, in the embodiments of the invention, the source recess, the drain recess, and the gate recess are formed simultaneously by an etching process to have respective bottom surfaces at substantially the same horizontal height. Therefore, the channel coupling effect is avoided, the channel resistance of the semiconductor device is reduced, and the difference in channel resistance between the semiconductor devices of different regions is reduced.

In addition, in the embodiments of the present invention, the liner layer disposed on the bottom of the source, drain, and gate electrodes may recover or elevate the two-dimensional electron gas under the source, drain, and gate electrodes, thereby reducing the on-resistance and channel resistance of the semiconductor device.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising:

a channel layer disposed on a substrate;

a first barrier layer disposed on the channel layer;

a second barrier layer disposed on the first barrier layer; and

a source electrode, a drain electrode, and a gate structure between the source electrode and the drain electrode extending at least partially through the second barrier layer, wherein the source electrode, the drain electrode, and the gate structure have respective bottom surfaces at substantially the same level and adjacent to the first barrier layer.

2. The semiconductor device of claim 1, further comprising:

a liner layer conformally disposed on respective lower portions of the source electrode, the drain electrode, and the gate structure, wherein a bottom surface of the liner layer has a level equal to or lower than a level of a bottom surface of the first barrier layer.

3. The semiconductor device of claim 2, further comprising:

a liner conformally disposed on respective lower portions of the source electrode, the drain electrode, and the gate structure, wherein a bottom surface of the liner has a height greater than a height of a bottom surface of the first barrier layer.

4. The semiconductor device of claim 2, wherein the liner layer has a bottom surface with a level between the bottom surface and the top surface of the first barrier layer.

5. The semiconductor device of claim 2, wherein the liner layer is further formed on the upper surface of the second barrier layer.

6. The semiconductor device according to claim 2, wherein a material of the liner layer comprises a hexagonal binary compound semiconductor.

7. The semiconductor device according to claim 6, wherein the binary compound semiconductor comprises aluminum nitride, zinc oxide, or indium nitride.

8. The semiconductor device of claim 2, wherein the gate structure comprises:

a dielectric layer; and

a gate electrode disposed on the dielectric layer, wherein the dielectric layer is between the liner and the gate electrode.

9. The semiconductor device of claim 8, wherein said dielectric layer is further disposed on a top surface and sidewalls of said source electrode and a top surface and sidewalls of said drain electrode.

10. The semiconductor device of claim 1, wherein the material of the first barrier layer is aluminum nitride.

11. A method for manufacturing a semiconductor device, comprising:

forming a channel layer, a first barrier layer and a second barrier layer on a substrate in sequence;

recessing the second barrier layer and the first barrier layer to form a source recess, a drain recess, and a gate recess between the source recess and the drain recess at least partially through the first barrier layer, wherein the source recess, the drain recess, and the gate recess have respective bottom surfaces at substantially the same horizontal height; and

a source electrode, a drain electrode, and a gate structure are formed in the source recess, the drain recess, and the gate recess, respectively.

12. The method of claim 11, wherein the step of recessing the second barrier layer and the first barrier layer comprises: an etching process is performed on the second barrier layer and the first barrier layer to simultaneously form the source recess, the drain recess, and the gate recess.

13. The method of claim 11, wherein the respective bottom surfaces of the source recess, the drain recess, and the gate recess have a level equal to or lower than a level of a bottom surface of the first barrier layer.

14. The method of claim 11, wherein the respective bottom surfaces of the source recess, the drain recess, and the gate recess have a horizontal height between the bottom surface and the top surface of the first barrier layer.

15. The method of manufacturing a semiconductor device according to claim 11, further comprising:

a liner is conformally formed on the bottom and sidewalls of the source recess, on the bottom and sidewalls of the drain recess, and on the bottom and sidewalls of the gate recess.

16. The method for manufacturing a semiconductor device according to claim 15, wherein a material of the underlayer comprises a hexagonal binary compound semiconductor.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the binary compound semiconductor comprises aluminum nitride, zinc oxide, or indium nitride.

18. The method of claim 15, wherein forming the gate structure comprises:

conformably forming a dielectric layer over the liner in the gate recess; and

a gate electrode is formed in the gate recess over the dielectric layer.

19. The method of claim 18, wherein said dielectric layer is further formed on a top surface and sidewalls of said source electrode and a top surface and sidewalls of said drain electrode.

20. The method of claim 11, wherein the material of the first barrier layer is aluminum nitride.