CN111276384B - Semiconductor process reaction chamber - Google Patents
Semiconductor process reaction chamber Download PDFInfo
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- CN111276384B CN111276384B CN202010097883.8A CN202010097883A CN111276384B CN 111276384 B CN111276384 B CN 111276384B CN 202010097883 A CN202010097883 A CN 202010097883A CN 111276384 B CN111276384 B CN 111276384B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32853—Hygiene
- H01J37/32862—In situ cleaning of vessels and/or internal parts
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Abstract
The invention provides a semiconductor process reaction chamber, which comprises: the air outlet end is provided with an air outlet; and the gas purging pipeline is communicated with the side wall of the gas outlet and is used for inputting gas with a set pressure into the gas outlet from the side wall of the gas outlet, and the gas forms a gas layer on the surface of the side wall of the gas outlet. The gas layer is formed on the side wall of the gas outlet, and the gas layer can prevent the reaction byproducts from being accumulated on the side wall of the gas outlet, so that the accumulated substances are prevented from influencing a semiconductor process performed in the reaction chamber.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a semiconductor process reaction chamber.
Background
In an integrated circuit manufacturing process, a semiconductor manufacturing apparatus performs a process such as diffusion, vapor deposition, development, etching, and ion implantation selectively and repeatedly on a wafer. Wherein, the process gas is injected into the semiconductor process reaction chamber under the specified atmosphere, so as to generate the reaction on the wafer in the process chamber, and the residual gas or the gas generated by the reaction is discharged through the exhaust port of the semiconductor process reaction chamber.
Typically, purging of reaction byproducts inside the reaction chamber may be accomplished by a cleaning system to ensure process stability, however, there is typically a build-up of reaction byproducts at the gas outlet of the semiconductor process reaction chamber that can affect process stability.
Therefore, how to avoid the accumulation of reaction byproducts at the gas outlet of the semiconductor process reaction chamber is a problem that needs to be solved.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a semiconductor process reaction chamber, which can prevent reaction byproducts from accumulating at an air outlet of the semiconductor process reaction chamber.
In order to solve the above problems, the present invention provides a semiconductor process reaction chamber, comprising: the air outlet end is provided with an air outlet; and the gas purging pipeline is communicated with the side wall of the gas outlet and is used for inputting gas with a set pressure into the gas outlet from the side wall of the gas outlet, and the gas forms a gas layer on the surface of the side wall of the gas outlet.
Furthermore, the air outlet end comprises a body, and a through hole penetrates through the body to form the air outlet.
Further, the gas purge line passes through the body and extends to a sidewall of the gas outlet.
Furthermore, the semiconductor process reaction chamber comprises two gas purging pipelines, and the two gas purging pipelines are symmetrically arranged by taking the axis of the gas outlet as a symmetry axis.
Further, a liner is arranged on the side wall of the gas outlet, a gas storage space is formed between the liner and the side wall of the gas outlet, at least one through hole is formed in the liner, the gas purging pipeline is communicated with the gas storage space, gas enters the gas storage space through the side wall of the gas outlet and enters the gas outlet through the through hole, and the gas forms the gas layer on the surface of the liner.
Furthermore, the through hole and the gas purging pipeline are arranged at the outlet of the side wall of the gas outlet in a staggered manner.
Further, a plurality of through holes are uniformly distributed on the gasket.
Furthermore, a plurality of gas storage spaces are formed between the liner and the side wall of the gas outlet, and each gas storage space is communicated with at least one gas purging pipeline.
Furthermore, a plurality of liners are arranged on the side wall of the air outlet, and an air storage space is formed between each liner and the side wall of the air outlet.
Furthermore, a blocking pad is arranged on the liner and corresponds to the outlet of the gas purging pipeline so as to change the gas flow direction at the outlet of the gas purging pipeline.
Further, the sidewall of the air outlet is recessed for receiving the gasket.
Further, the liner is of a concave configuration, the concave configuration is provided with at least one groove, and at least one air storage space is formed between the groove and the side wall of the air outlet.
The gas layer is formed on the side wall of the gas outlet, and the gas layer can prevent the reaction byproducts from being accumulated on the side wall of the gas outlet, so that the accumulated substances are prevented from influencing a semiconductor process performed in the reaction chamber.
Drawings
FIG. 1 is a schematic diagram of a gas outlet end of a conventional semiconductor processing reaction chamber;
FIG. 2 is a schematic view of the outlet end of a first embodiment of a semiconductor processing reaction chamber of the present invention;
FIG. 3 is a schematic view of the outlet end of a second embodiment of a semiconductor processing reaction chamber of the present invention;
FIG. 4 is a schematic view of the outlet end of a third embodiment of a semiconductor processing reaction chamber of the present invention;
FIG. 5 is a schematic view of the outlet end of a fourth embodiment of a semiconductor processing reaction chamber of the present invention;
FIG. 6 is a schematic view of the outlet end of a fifth embodiment of a semiconductor processing reaction chamber of the present invention;
FIG. 7 is a schematic view of the outlet end of a sixth embodiment of a semiconductor processing reaction chamber of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a semiconductor processing reaction chamber according to the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a gas outlet of a conventional semiconductor processing chamber. Referring to fig. 1, a reaction chamber for semiconductor processing includes a reaction chamber 10 and an outlet 11. The gas outlet end 11 is provided with a gas outlet 110, and residual gas or reaction byproducts in the reaction chamber 10 are discharged through the gas outlet 110.
Reaction by-products accumulate in large quantities at the gas outlet 110 to form an accumulation 12. The build-up 12 not only affects the pumping rate, but also in the case of pressure disturbances, the reaction by-product powder may flow back into the reaction chamber 10, seriously affecting the reaction in the reaction chamber 10. The deposit 12 at the gas outlet 110 has become the biggest bottleneck factor in the extension of the cleaning cycle of the semiconductor processing reaction chamber as the process is upgraded. The bottleneck effect becomes more prominent as the silicon source gas amount is gradually increased.
In view of the foregoing, the inventors propose an improved scheme for a semiconductor processing reaction chamber.
FIG. 2 is a schematic view of the outlet end of a first embodiment of a semiconductor processing chamber according to the present invention. Referring to fig. 2, the semiconductor process chamber of the present invention includes a reaction chamber 20, an outlet port 21, and at least one gas purge line 22.
The air outlet end 21 is provided with an air outlet 211. The gas outlet 211 is communicated with the reaction chamber 20, and residual gas or reaction by-products in the reaction chamber 20 are discharged through the gas outlet 211. In the present embodiment, the air outlet end 21 includes a body 212, and a through hole penetrates the body 212 to form the air outlet 211. The cross-sectional shape of the air outlet 211 may be circular, rectangular, irregular, etc.
The gas purge line 22 is communicated with a sidewall of the gas outlet 211, and is configured to input a gas having a set pressure into the gas outlet 211 from the sidewall of the gas outlet 211. Specifically, in the present embodiment, the gas purge line 22 passes through the body 212 from the periphery of the gas outlet 211 and bends to extend to the side wall of the gas outlet 211.
The gas forms a gas layer 23 on the surface of the sidewall of the gas outlet 211. Wherein the thickness of the gas layer 23 can be controlled by controlling the pressure and flow rate of the gas. For example, the set pressure of the gas is 20 to 30PISA, and the flow rate of the gas is 10 to 30SLPM, so as to provide a suitable thickness of the gas layer 23, which does not affect the flow of the residual gas or the reaction by-products, and can prevent the reaction by-products from accumulating on the side wall of the gas outlet 211.
Further, the gas may be nitrogen, an inert gas, or a mixture thereof, so as to prevent the gas from flowing backwards and affecting the process reaction in the reaction chamber 20. The gas may be provided by an external gas source.
When the residual gas or the reaction by-products in the reaction chamber 20 is exhausted through the gas outlet 211, the gas layer 23 can prevent the reaction by-products from accumulating on the sidewall of the gas outlet 211, thereby preventing the accumulation from affecting the semiconductor process performed in the reaction chamber.
It can be understood that the process change introduced by the above design change, such as the change of the pressure control curve, can be compensated by the Pump flow rate (Pump capacity) of the vacuum system or the PID system pressure negative feedback of the throttle valve, so as to eliminate the influence.
Further, in the present embodiment, the semiconductor process reaction chamber includes two gas purging lines 22, and the two gas purging lines 22 are symmetrically disposed with respect to the axis of the gas outlet 211 as a symmetry axis, so that a uniform gas layer 23 can be further formed, and the reaction byproducts are further prevented from being accumulated on the sidewall of the gas outlet 211. Further, in other embodiments of the present invention, a plurality of gas purge lines 22 may be provided in order to form a complete gas layer 23 on the sidewall of the gas outlet 211.
The semiconductor processing chamber of the present invention also provides a second embodiment. FIG. 3 is a schematic view of the outlet end of a second embodiment of a semiconductor processing reaction chamber of the present invention. Referring to fig. 3, the second embodiment is different from the first embodiment in that a liner 24 is provided on a sidewall of the air outlet 211. The liner 24 may be a quartz liner.
An air storage space 24A is formed between the liner 24 and the sidewall of the air outlet 211. The gasket 24 has at least one through hole 241, the through hole 241 communicates the air storage space 24A with the air outlet 211, and the gas purge line 22 communicates with the air storage space 24A. The gas enters the gas storage space 24A through the side wall of the gas outlet 211 and enters the gas outlet 211 through the through hole 241, and the gas forms the gas layer 23 on the outer surface of the pad 24. The gas storage space 24A can buffer the gas input from the gas purging line 22, so as to prevent the gas input from the gas purging line from affecting the circulation of the residual gas and the reaction byproducts in the gas outlet 211.
Further, the through hole 241 and the outlet of the gas purging line 22 on the side wall of the gas outlet 211 are disposed in a staggered manner, so that the transmission path of the gas output from the gas purging line 22 is changed, and the gas is output to the gas outlet 211 at a more appropriate position to form the gas layer 23.
Further, in the second embodiment, the sidewall of the air outlet 211 is recessed to receive the pad 24. The gasket 24 may be fitted in a recess of the air outlet 211 and fixed with respect to the air outlet 211. The pad 24 has a concave configuration having at least one groove, and at least one air storage space 24A is formed between the groove and the sidewall of the air outlet 211. Specifically, in the second embodiment, the concave configuration has a groove, and the groove and the sidewall of the air outlet 211 form an air storage space 24A therebetween. In another embodiment of the present invention (please refer to fig. 5), the concave structure has a plurality of grooves, and a gas storage space is formed between each groove and the sidewall of the gas outlet 211, so as to form a plurality of gas storage spaces.
Further, in the second embodiment, only one through hole 241 is disposed on the liner 24, and in the third embodiment of the present invention, please refer to fig. 4, which is a schematic structural diagram of the outlet end of the third embodiment of the semiconductor process reaction chamber of the present invention, a plurality of uniformly distributed through holes 241 are disposed on the liner 24. The gas in the gas storage space 24A is discharged to the gas outlet 211 through the through hole 241, and then a uniform gas layer 23 is formed on the outer surface of the liner 24, so as to reduce the influence of the gas layer 23 on the circulation of the residual gas and the reaction by-products in the gas outlet 211.
To further improve the uniformity of the gas layer 23, a fourth embodiment of the semiconductor processing chamber of the present invention is also provided. Referring to fig. 5, a schematic structural view of an outlet end of a fourth embodiment of a semiconductor processing reaction chamber according to the present invention is shown, and referring to fig. 5, the fourth embodiment is different from the third embodiment in that a plurality of gas storage spaces 24A are formed between the liner 24 and the sidewall of the gas outlet 211, and each gas storage space 24A is communicated with at least one gas purging line 22.
In the fourth embodiment, compared to only one air storage space 24A between the pad 24 and the sidewall of the air outlet 211, the area between the pad 24 and the sidewall of the air outlet 211 is divided into a plurality of air storage spaces 24A, and each small area of the pad 24 has the same pressure of air output, so that the uniformity of the air layer 23 can be further improved.
Further, a fifth embodiment of the semiconductor processing chamber of the present invention is also provided. Fig. 6 is a schematic structural view of an outlet port of a fifth embodiment of a reaction chamber for semiconductor process according to the present invention, referring to fig. 6, the fifth embodiment is different from the third embodiment in that a plurality of liners are disposed on sidewalls of the gas outlet, and a gas storage space 24A is formed between each liner and the sidewall of the gas outlet 211. In the fifth embodiment, the gas is output from a plurality of the pads at the same pressure, so that the gas layer 23 having a uniform thickness can be formed on the outer surface of the pad, thereby improving the uniformity of the gas layer 23. Specifically, in the present embodiment, two liners, i.e., a liner 242 and a liner 243, are disposed on the sidewall of the air outlet 211, and the two liners are disposed on the upper and lower sides of the air outlet 211.
The gas pressure at the outlet of the gas purging line 22 on the side wall of the gas outlet 211 is the maximum, and the pressure is gradually reduced along with the transmission of the gas, so as to avoid that the gas at the outlet of the gas purging line 22 on the side wall of the gas outlet 211 affects the uniformity of the gas layer 23 due to the excessive pressure. The semiconductor process chamber of the present invention also provides a sixth embodiment. Fig. 7 is a schematic structural view of an outlet end of a sixth embodiment of a semiconductor processing reaction chamber according to the present invention, and referring to fig. 7, the sixth embodiment is different from the third embodiment in that a blocking pad 25 is further disposed on the liner 24. The blocking pad 25 is arranged corresponding to the outlet of the gas purging pipeline 22 on the side wall of the gas outlet 211, so as to change the gas flow direction of the outlet of the gas purging pipeline 22 on the side wall of the gas outlet 211, realize transverse flow guiding, and enable the gas to be uniformly diffused.
Specifically, in the sixth embodiment, the blocking pad 25 is disposed on the inner side wall of the liner 24, that is, the side of the liner 24 facing the side wall of the gas outlet 211, the blocking pad 25 is disposed opposite to the outlet of the gas purging line 22 on the side wall of the gas outlet 211, and the gas output from the outlet of the gas purging line 22 is blocked by the blocking pad 25 to change the flow direction, so as to prevent the high-pressure gas from being directly output from the through hole of the liner 24, and to laterally diffuse the gas, thereby improving the uniformity of gas diffusion. In addition, the gas output from the edge of the blocking pad 25 has a higher pressure than the gas in other areas, and the gas diffuses toward the area blocked by the blocking pad 25 on the outer surface of the liner 24, so that a gas layer can be formed on the area blocked by the blocking pad 25, and a uniform gas layer 23 is formed on the outer surface of the liner 24.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A semiconductor processing reaction chamber, comprising:
the air outlet end is provided with an air outlet;
a liner is arranged on the side wall of the air outlet, an air storage space is formed between the liner and the side wall of the air outlet, and the liner is provided with at least one through hole;
at least one gas purging pipeline, which is communicated with the gas storage space, wherein gas with a set pressure enters the gas storage space through the side wall of the gas outlet and enters the gas outlet through the through hole, and the gas forms a gas layer on the surface of the liner;
the gasket is also provided with a blocking gasket, and the blocking gasket is arranged corresponding to the outlet of the gas purging pipeline so as to change the gas flow direction at the outlet of the gas purging pipeline.
2. The chamber of claim 1, wherein the gas outlet comprises a body, and a through hole extends through the body to form the gas outlet.
3. The semiconductor process chamber of claim 2, wherein the gas purge line passes through the body and extends to a sidewall of the gas outlet.
4. The semiconductor process reaction chamber of claim 1, comprising two gas purging lines, wherein the two gas purging lines are symmetrically arranged with an axis of the gas outlet as a symmetry axis.
5. The semiconductor process reaction chamber of claim 1, wherein the through hole and the gas purging line are arranged in a staggered manner at an outlet of the gas outlet side wall.
6. The semiconductor process reaction chamber of claim 1, wherein the liner is provided with a plurality of uniformly distributed through holes.
7. The chamber of claim 1, wherein a plurality of gas reservoirs are formed between the liner and the sidewall of the gas outlet, each gas reservoir being in communication with at least one of the gas purge lines.
8. The chamber of claim 1, wherein a plurality of liners are disposed on sidewalls of the gas outlet, and a gas storage space is formed between each liner and the sidewall of the gas outlet.
9. The semiconductor process chamber of claim 1, wherein a sidewall of the gas outlet is recessed to receive the liner.
10. The chamber of claim 1, wherein the liner has a concave configuration with at least one groove, and wherein the groove and the sidewall of the gas outlet define at least one gas storage space therebetween.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010097883.8A CN111276384B (en) | 2020-02-17 | 2020-02-17 | Semiconductor process reaction chamber |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010097883.8A CN111276384B (en) | 2020-02-17 | 2020-02-17 | Semiconductor process reaction chamber |
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| CN111276384B true CN111276384B (en) | 2021-04-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104979237A (en) * | 2014-04-11 | 2015-10-14 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semiconductor processing device |
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| US7204913B1 (en) * | 2002-06-28 | 2007-04-17 | Lam Research Corporation | In-situ pre-coating of plasma etch chamber for improved productivity and chamber condition control |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104979237A (en) * | 2014-04-11 | 2015-10-14 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semiconductor processing device |
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