CN111274752B - Power amplifier behavior modeling method based on two-stage open loop and binary function - Google Patents

Power amplifier behavior modeling method based on two-stage open loop and binary function Download PDF

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CN111274752B
CN111274752B CN201811478375.3A CN201811478375A CN111274752B CN 111274752 B CN111274752 B CN 111274752B CN 201811478375 A CN201811478375 A CN 201811478375A CN 111274752 B CN111274752 B CN 111274752B
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雷易鸣
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Abstract

The invention provides a power amplifier behavior modeling method based on two-stage open loop and binary function, which relates to the technical field of nonlinear system modeling and analysis application.

Description

Power amplifier behavior modeling method based on two-stage open loop and binary function
Technical Field
The invention relates to the technical field of nonlinear system modeling and analysis application, in particular to a power amplifier behavior modeling method based on a two-stage open loop structure and a binary function unit.
Background
The power amplifier is an important module of the transmitter and is a complex nonlinear system. In order to make the power amplifier operate with high efficiency, the transistors in the power amplifier are mostly operated in a region close to saturation or even in a cut-off region, so that the power amplifier often generates severe nonlinear distortion, and the power amplifier generates a memory effect due to the equivalent reactance of the device.
The digital predistortion module can effectively remove the nonlinearity of the power amplifier and the system by a low-cost and high-precision method, and therefore becomes an indispensable part in the modern wireless transmitter. In the digital predistortion phase of the signal, the characteristics of the power amplifier need to be modeled. The linearization performance and practical availability of digital predistortion for power amplifiers depends to a large extent on the accuracy and complexity of the relevant non-linear power amplifier behavior model.
The modeling method of the power amplifier can be divided into physical modeling and behavior modeling: physical modeling usually requires knowing the circuit structure of the power amplifier, the characteristics of related components, the basic circuit law, related theoretical rules and the like; and the behavior modeling only needs to utilize the input and output data of the power amplifier, adopts a black box mode to describe the response characteristics of the system, and is simpler and more convenient to analyze.
According to the physical essence reflected by the model, the behavior model is divided into a non-memory model, a memory model and the like. The memoryless power amplifier model is relatively simple and has good effect on the modeling of the narrow-band system. But in practice the power amplifier is a typical non-linear memory system. Memory models typically employ a basic two-block-Hammerstein model, a Time Delay Neural Network (TDNN) model, and a closed-loop nonlinear auto-regressive moving average (NARMA) model, which exhibits relatively higher accuracy in modeling power amplifiers with memory effects than open-loop power amplifier models. However, the closed-loop power amplifier model requires an additional feedback path to return real-time samples of the power amplifier output, which makes implementation of digital predistortion techniques using the closed-loop model inconvenient for mobile terminals and high frequency systems. In addition, the memory model of the power amplifier is generally a unitary function unit, the essence of the unitary function unit is that the input values at different times respectively and independently influence the output value, and the correlation of the input values at different times also has influence on the output value of the power amplifier, which is not considered by the existing power amplifier modeling method.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a power amplifier behavior modeling method based on a two-stage open-loop structure and a binary function unit. The method utilizes a two-stage open loop structure and a two-stage function unit, can complete modeling of the nonlinear power amplifier with the memory effect only by needing fewer parameters and no feedback path, provides good modeling precision for band-internal distortion and spectrum regeneration, and is beneficial to reducing the interference of nonlinear noise in a system containing a power amplifier circuit to the system by improving the modeling precision of the power amplifier.
In order to achieve the above object, the present invention adopts the following technical solutions:
a power amplifier behavior modeling method based on two-stage open loop and a binary function comprises the following steps:
step 1): collecting input signal data vector x of a power amplifierin＝[xin(1),xin(2),xin(3),...,xin(N)]And output signal data vector yout＝[yout(1),yout(2),yout(3),...,yout(N)]Wherein each element represents a signal data, N being the data length;
step 2): establishing a first-stage part of a power amplifier behavior model: the forward path μ (k), whose input variables contain the instantaneous and past samples, is expressed as follows:
Figure GDA0003473209310000021
wherein x (k) and x (k-d)n) Representing instantaneous and past samples, respectively, Fn() Representing a two-dimensional linear function for characterizing the memory effect of a power amplifier, Fn[x(k),x(k-dn)]Is the constructed binary function unit and d represents the delay tap.
Step 3): establishing a second-stage part of the power amplifier behavior model: feedback path λ (k), expression is as follows:
Figure GDA0003473209310000022
wherein G ism()、Gp()、Gq() And Gr() Representing a two-dimensional linear function, Gm[μ(k),μ(k-dm)]Equal representing binary function unit containing first stage current total output and past total output, d representing delay tap, M, P, Q, R value size measuring the power amplifierThe larger the value is, the larger the memory effect is, and the larger the memory effect is determined according to the actual engineering.
Step 4): the model for power amplifier behavior modeling based on the two-stage open-loop structure and the binary function unit is obtained as follows:
Figure GDA0003473209310000023
wherein the output y (k) of the power amplifier in the feedback path λ (k) is approximated using the forward path μ (k);
step 5): the selection of the number of terms in the feedback path lambda (k) is determined according to the characteristics of the power amplifier model, and the larger the memory effect of the power amplifier is, the larger the number of terms is, and the general selection is
Figure GDA0003473209310000031
The feedback path of the power amplifier can be described. Therefore, the parameters of the power amplifier behavior model based on the two-stage open loop structure and the binary function unit are selected, and the number N of the sample delay taps is equal to N0，M＝M0，N0、M0The magnitude of (A) measures the memory effect of the power amplifier, N0、M0The larger the memory effect of the power amplifier is, the larger the memory effect is, and the memory effect is determined according to engineering practice; delay tap dnAnd dmRespectively is dn-maxAnd dm-maxActually determining according to engineering; the model estimates the error e ∞, which is reduced by iterative calculations.
Step 6): initializing the behavior model of the power amplifier and selecting a delay tap dnAnd dmThe sequences of (a) and (b) are,
Figure GDA0003473209310000032
step 7): input signal data vector x of power amplifier to be collectedinAnd output signal data vector youtAnd (4) bringing the behavior model into the power amplifier, and calculating to obtain the behavior model of the power amplifier.
Step 8): function of calculated error
Figure GDA0003473209310000033
Wherein, youtIs the actual output of the power amplifier and,
Figure GDA0003473209310000034
is the output of a power amplifier behavior model based on a two-level open-loop structure and a binary function unit.
Step 9): update dnAnd dmOf (a) i.e.
Figure GDA0003473209310000035
And
Figure GDA0003473209310000036
until a critical condition is reached
Figure GDA0003473209310000037
And
Figure GDA0003473209310000038
until now. Is found out so that
Figure GDA00034732093100000319
Minimized delay tap dnAnd dmThe sequence of (a) is the final output of the power amplifier model. Wherein an optimum tap delay sequence is found
Figure GDA0003473209310000039
And
Figure GDA00034732093100000310
including but not limited to traversal search, depth first search algorithms, etc.
Preferably, the updating in step 9
Figure GDA00034732093100000311
And
Figure GDA00034732093100000312
the algorithm of (a) includes, but is not limited to, the following algorithm steps:
step 91): comparing the value of the previously retained model estimation error e with the value of the current error function
Figure GDA00034732093100000313
Size of (1), if
Figure GDA00034732093100000314
The system updates the delay tap sequence dnAnd dmI.e. by
Figure GDA00034732093100000315
Figure GDA00034732093100000316
Entering step 7; if it is
Figure GDA00034732093100000317
The current tap delay sequence value is retained
Figure GDA00034732093100000318
Figure GDA0003473209310000041
And updating the model estimation error
Figure GDA0003473209310000042
The system then updates the delay tap sequence dnAnd dmI.e. by
Figure GDA0003473209310000043
Figure GDA0003473209310000044
Step 7 is entered and the steps are performed sequentially downwards.
Step 92): when detecting that
Figure GDA0003473209310000045
And is
Figure GDA0003473209310000046
Thereafter, the tap delay sequence is updated
Figure GDA0003473209310000047
Figure GDA0003473209310000048
And entering step 7; when detecting that
Figure GDA0003473209310000049
And is
Figure GDA00034732093100000410
Thereafter, step 9 is stopped and the residue is obtained
Figure GDA00034732093100000411
And
Figure GDA00034732093100000412
preferably, the sequence in the above steps
Figure GDA00034732093100000413
And sequence
Figure GDA00034732093100000414
Has the following properties:
Figure GDA00034732093100000415
the invention adopts a two-stage model, the first stage mu (k) is a parallel memory polynomial, and each branch is represented by a sequence with excellent convergence characteristics and accuracy characteristics. In order to better represent the memory effect of the power amplifier, the input variable of each branch is constructed by a two-stage function unit, the two-stage function unit comprises an instantaneous sample and a past sample, and the influence of the input values at different moments on an output value and the influence of the correlation between the samples at different moments on the output of the power amplifier are considered. The second stage λ (k) of the two-stage model is also a parallel memory polynomial in which the input variables of each branch are not feedback samples from the power amplifier output, but their approximate signals, i.e. the total output of the first stage; meanwhile, the second stage also adopts a two-stage function unit, and the input variables comprise the current total output and the past total output of the first stage.
The invention has the beneficial effects that: the invention predicts the behavior model of the nonlinear power amplifier with memory effect by a two-stage open-loop structure model, and simultaneously uses a binary function unit to describe the specific behavior of the model. In this model, the sampled power amplifier output in the feedback path is replaced by an approximation signal. In addition, a sequence having excellent convergence characteristics and accuracy characteristics is adopted in each branch of the parallel memory polynomial used in the model. The power amplifier model is generated by a forward path and a feedback path, which shows that the output of the power amplifier is not only related to the input at the current moment, but also related to the historical input, and the memory effect of the power amplifier is described. Compared with an open-loop time delay neural network, the model requires fewer parameters and no feedback path, and provides good modeling accuracy for in-band distortion and spectrum regeneration. The method has the advantages that the convergence speed of the model is accelerated, the precision of the model is guaranteed, and the behavior modeling of the power amplifier is facilitated. In addition, the influence of the correlation of input values input into the power amplifier at different moments on an output value is considered by introducing the binary function unit, and compared with a power amplifier model of a unitary function, the method has higher modeling precision.
Drawings
Fig. 1 is a graph of test results for a power amplifier.
Fig. 2 is a flow chart of a power amplifier behavior modeling method based on a two-stage open-loop structure and a binary function unit.
Fig. 3A is a graph of the AM-AM distortion characteristics of a measured power amplifier, and fig. 3B is a graph of the AM-AM distortion characteristics of a fitted power amplifier.
Fig. 4 is an AM-AM distortion characteristic error plot of a power amplifier model.
Fig. 5A is a graph of the AM-PM distortion characteristics of a measured power amplifier, and fig. 5B is a graph of the AM-PM distortion characteristics of a fitted power amplifier.
Fig. 6 is an AM-PM distortion characteristic error plot of a power amplifier model.
Detailed Description
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment discloses a power amplifier behavior modeling method based on a two-stage open-loop structure and a binary function unit, which is used for constructing a power amplifier model. The power amplifier is tested using a test structure as shown in fig. 1. The data for model extraction and validation was measured from a 2.15GHZ, 170W Lateral Diffused Metal Oxide Semiconductor (LDMOS) power amplifier and the test signal used the 3G wideband code division multiplexing access specification (WCDMA). The modeling method is shown in fig. 2 and is specifically described below.
Step 1): collecting input signal data vector x of a power amplifierin＝[xin(1),xin(2),xin(3),...,xin(N)]And output signal data vector yout＝[yout(1),yout(2),yout(3),...,yout(N)]Where N is the data length.
Step 2): the first stage part μ (k) of the power amplifier behavior model is built with its input variables containing instantaneous samples and past samples. Fn() The method comprises the steps of representing a two-dimensional linear function, and being capable of representing the memory effect of the power amplifier; fn[x(k),x(k-dn)]Is a constructed binary function unit containing instantaneous samples and past samples. The expression is as follows:
Figure GDA0003473209310000051
step 3): establishing a second-stage part lambda (k), G of a power amplifier behavior modelm()、Gp()、Gq() And Gr() Representing two-dimensional linesSexual function, Gm[μ(k),μ(k-dm)]Equal represents a binary function unit, containing the first-stage current total output and the past total output. The expression is as follows:
Figure GDA0003473209310000061
step 4): approximating the output y (k) of the power amplifier in the feedback path λ (k) using the forward path μ (k), the model for power amplifier behavior modeling based on a two-stage open-loop structure and a binary function unit is derived as:
Figure GDA0003473209310000062
step 5): the choice of the number of terms in the feedback path λ (k) is determined by the characteristics of the power amplifier model, and is generally chosen
Figure GDA0003473209310000063
The feedback path of the power amplifier can be described. Therefore, the parameters of the power amplifier behavior model based on the two-stage open loop structure are selected, and the number N of the sample delay taps is equal to N0，M＝M0Delay tap dnAnd dmRespectively is dn-maxAnd dm-maxThe model estimation error e ═ infinity.
Step 6): initializing the behavior model of the power amplifier and selecting a delay tap dnAnd dmThe sequences of (a) and (b) are,
Figure GDA0003473209310000064
step 7): input signal data vector x of power amplifier to be collectedinAnd output signal data vector youtAnd (4) bringing the behavior model into the power amplifier, and calculating to obtain the behavior model of the power amplifier.
Step 8) calculating a function of the error
Figure GDA0003473209310000065
Wherein, youtIs the actual output of the power amplifier and,
Figure GDA0003473209310000066
is the output of a power amplifier behavior model based on a two-level open-loop structure and a binary function unit.
Step 9): comparing the value of the previously retained model estimation error e with the value of the current error function
Figure GDA0003473209310000067
Size of (1), if
Figure GDA0003473209310000068
Or
Figure GDA0003473209310000069
The system updates the sequence of delay taps,
Figure GDA00034732093100000610
Figure GDA00034732093100000611
entering step 7; if it is
Figure GDA00034732093100000612
Or
Figure GDA00034732093100000613
The current tap delay sequence value is retained
Figure GDA00034732093100000614
Figure GDA00034732093100000615
And updating the model estimation error
Figure GDA00034732093100000616
The system then updates the delay tap sequence, i.e.
Figure GDA0003473209310000071
Figure GDA0003473209310000072
Step 7 is entered and the steps are performed sequentially downwards.
Step 10): when detecting that
Figure GDA0003473209310000073
And is
Figure GDA0003473209310000074
Thereafter, the tap delay sequence is updated
Figure GDA0003473209310000075
Figure GDA0003473209310000076
And entering step 7; when detecting that
Figure GDA0003473209310000077
And is
Figure GDA0003473209310000078
Thereafter, step 9 is stopped and the residue is obtained
Figure GDA0003473209310000079
And
Figure GDA00034732093100000710
step 11): according to calculation
Figure GDA00034732093100000711
And
Figure GDA00034732093100000712
the behavior of the output power amplifier is modeled as
Figure GDA00034732093100000713
Wherein the sequence
Figure GDA00034732093100000714
And sequence
Figure GDA00034732093100000715
Has the following properties that,
Figure GDA00034732093100000716
the pairs of the results of fitting after model construction and the results of actual measurement are shown in fig. 3 to 6.
As can be seen from fig. 3A-3B, the measured AM-AM distortion characteristic curve of the power amplifier and the AM-AM distortion characteristic curve fitted to the power amplifier model both enter a saturation state when the input signal power is about-14 dBm, which indicates that the power amplifier model better fits the AM-AM distortion characteristic of the power amplifier.
Fig. 4 compares the error of the power actually output by the power amplifier with the error of the power output by the power amplifier model, and it is obvious from the graph that the error of the power of most points is within 1dB except that the error of individual points is more than 1dB, which shows that the modeling accuracy of the power amplifier model is high.
As is apparent from fig. 5A-5B, the measured AM-PM distortion characteristic curve of the power amplifier and the AM-PM distortion characteristic curve fitted to the power amplifier model both enter an apparent phase distortion state when the input signal power is about-10 dBm, which indicates that the power amplifier model better fits the AM-PM distortion characteristic of the power amplifier.
Fig. 6 compares the phase of the signal actually output by the power amplifier with the phase difference of the signal output by the power amplifier model, and it is obvious from the graph that the error of the phase difference of most points is within pi/8 except that the error of individual points is larger than pi/8, which shows that the modeling precision of the power amplifier model is high.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.

Claims (9)

1. A power amplifier behavior modeling method based on two-stage open loop and a binary function comprises the following steps:
1) collecting input signal data vector x of a power amplifierin＝[xin(1),xin(2),xin(3),…,xin(N′)]And output signal data vector yout＝[yout(1),yout(2),yout(3),…,yout(N′)]Wherein each element represents a signal data, N' is a data length;
2) establishing a first stage of a power amplifier behavior model: forward path μ (k), expressed as:
Figure FDA0003530711290000011
wherein, Fn() Representing a two-dimensional linear function, representing the memory effect of the power amplifier, and constructing a binary function unit; x (k) denotes instantaneous samples, x (k-d)n) Represents past samples, d represents delay taps;
3) establishing a second stage of the power amplifier behavior model: a feedback path λ (k), expressed as:
Figure FDA0003530711290000012
wherein G ism()、Gp()、Gq() And Gr() Representing a two-dimensional linear function, and constructing a binary function unit, wherein two elements contained in the binary function unit are the current total output and the past total output of the first stage in sequence, and d represents a delay tap;
4) and adding mu (k) and lambda (k) to obtain a power amplifier behavior model y (k), wherein the expression is as follows:
Figure FDA0003530711290000013
2. the method of claim 1, wherein the term in the feedback path λ (k) is determined based on a power amplifier memory effect magnitude.
3. The method of claim 2, wherein the term in the feedback path λ (k) is selected
Figure FDA0003530711290000014
The number N of the sample delay taps in the step 4) is equal to N0，M＝M0Delay tap dnAnd dmRespectively is dn-maxAnd dm-maxThe model estimation error e ═ infinity.
4. The method of claim 3 wherein the power amplifier behavior model is initialized and a delay tap d is selectednAnd dmThe sequences of (a) are:
Figure FDA0003530711290000015
Figure FDA0003530711290000021
5. the method of claim 4, wherein calculating the error function of the power amplifier behavior model is:
Figure FDA0003530711290000022
wherein, youtIs the actual output of the power amplifier and,
Figure FDA0003530711290000023
is the output of the power amplifier behavior model.
6. The method of claim 5, wherein d is updatednAnd dmThe sequence of (a):
Figure FDA0003530711290000024
and
Figure FDA0003530711290000025
until a critical condition is reached
Figure FDA0003530711290000026
And
Figure FDA0003530711290000027
until now, find such that
Figure FDA0003530711290000028
Minimized delay tap dnAnd dmOf (2) is optimized
Figure FDA0003530711290000029
And
Figure FDA00035307112900000210
i.e. the final output of the power amplifier model.
7. The method of claim 6, wherein a sequence of tap delays d is foundnAnd dmOf (2) is optimized
Figure FDA00035307112900000211
And
Figure FDA00035307112900000212
the algorithm of (a) includes a traversal search algorithm or a depth-first search algorithm.
8. The method of claim 6, wherein d is updatednAnd dmThe method of (a) comprises the steps of:
1) comparing the value of the previously retained model estimation error e with the value of the current error function
Figure FDA00035307112900000213
Size of (1), if
Figure FDA00035307112900000214
The delay tap sequence d is updatednAnd dm：
Figure FDA00035307112900000215
Figure FDA00035307112900000216
If it is
Figure FDA00035307112900000217
The current tap delay sequence value is retained:
Figure FDA00035307112900000218
Figure FDA00035307112900000219
and updating the model estimation error
Figure FDA00035307112900000220
After which the delay tap sequence d is updatednAnd dm：
Figure FDA00035307112900000221
Figure FDA00035307112900000222
2) When detecting that
Figure FDA00035307112900000223
And is
Figure FDA00035307112900000224
Thereafter, the tap delay sequence is updated
Figure FDA00035307112900000225
Figure FDA00035307112900000226
When detecting that
Figure FDA00035307112900000227
And is
Figure FDA00035307112900000228
After that, the updating is stopped and the data is retained
Figure FDA00035307112900000229
And
Figure FDA00035307112900000230
9. the method of claim 6 or 8, wherein the sequence is
Figure FDA00035307112900000231
And sequence
Figure FDA0003530711290000031
Has the following properties:
Figure FDA0003530711290000032
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