CN111274163A - Dual in-line memory module device of storage-level memory and caching method thereof - Google Patents

Dual in-line memory module device of storage-level memory and caching method thereof Download PDF

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CN111274163A
CN111274163A CN202010230514.1A CN202010230514A CN111274163A CN 111274163 A CN111274163 A CN 111274163A CN 202010230514 A CN202010230514 A CN 202010230514A CN 111274163 A CN111274163 A CN 111274163A
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memory
data
storage area
range
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周小锋
江喜平
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Xian Unilc Semiconductors Co Ltd
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Xian Unilc Semiconductors Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space

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Abstract

The invention relates to a dual in-line memory module device of a storage-level memory and a caching method thereof. The dual inline memory module of the storage level memory of the invention can expand the nonvolatile memory on the dual inline memory module into the memory of the system for use, and the memory space of the system is increased. In addition, a core controller is present on the dual inline memory module DIMM of the storage level memory SCM of the present invention for driving the command/address signals as well as the data signals as they are output in order to improve the speed performance of the module.

Description

Dual in-line memory module device of storage-level memory and caching method thereof
Technical Field
The present invention relates to the field of memories. More particularly, the present invention relates to a Dual In-line Memory Module (DIMM) device of a Storage Class Memory (SCM) and a caching method thereof.
Background
The dual inline memory module DIMM of the storage level memory SCM is a new type of dual inline memory module, on which there is memory space that can be accessed in storage form.
The signal flow and interface schematic in a dual inline memory module DIMM of a storage level memory SCM known from the prior art is shown in fig. 1. In the prior art, with a branch (stub) signal, a host (host) or a central Processing unit cpu (central Processing unit) can Access a dynamic Random Access memory dram (dynamic Random Access memory) and a controller such as a Non-volatile controller NVC (Non-volatile controller) during normal operation, and the purpose of accessing a Non-volatile memory NVM (Non-volatile memory) such as NAND Flash is achieved by accessing the controller, thereby increasing the memory space of the system.
The bifurcation signal is embodied in the following aspects: a Command/Address CA (Command/Address) signal is output from a DIMM slot (slot) followed by a fork (stub) signal, which is connected to a clock driver rcd (register clock driver) and a controller, respectively; the data DQ signal also has a bifurcated signal between the data buffer db (data buffer) and the dynamic random access memory DRAM. Such a bifurcated signal has great difficulty in implementing a high-speed signal on a printed Circuit board (pcb), because the feedback of the high-speed signal interferes with another signal, which affects the speed.
Therefore, there is a need for a dual inline memory module DIMM device of the storage level memory SCM and a caching method thereof capable of solving the above problems.
Disclosure of Invention
The present invention relates to a Dual Inline Memory Module (DIMM) device of a storage level memory (SCM) and a cache method thereof, wherein the DIMM device can increase the storage space and improve the speed performance of a module.
The dual inline memory module of the storage level memory can expand the nonvolatile memory on the dual inline memory module into the memory of a system for use, and the memory space of a dual inline memory module DIMM is increased. In addition, a core controller is present on the dual inline memory module DIMM of the storage level memory SCM of the present invention for driving the command/address signals as well as the data signals as they are output in order to improve the speed performance of the module.
According to a first aspect of the present invention, there is provided a dual inline memory module arrangement of a storage level memory, wherein the dual inline memory module arrangement comprises:
a first storage area storing data having a first range of host access frequencies; and
a second storage area storing data having a second range of host access frequencies;
wherein the first range of host access frequencies is greater than the second range of host access frequencies.
Thus, the storage area of the dual inline memory module apparatus is divided into a "hot area" (i.e., a first storage area) where the host or the central processing unit frequently reads and writes and a "cold area" (i.e., a second storage area) where the host or the central processing unit does not frequently read and write, the processing speed of the "hot area" is relatively fast, and the processing speed of the "cold area" is relatively slow. In this way, the rate performance of the modular arrangement may be improved.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention, the first memory area is a dynamic random access memory.
Since the processing speed of the dram is relatively fast, the rate performance of the module device can be improved by storing data frequently read and written by the host or the cpu in the dram.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention, the second memory area comprises a plurality of sub-memory areas, each storing data having a different range of host access frequencies.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention, the second memory area comprises three sub-memory areas, namely a first sub-memory area, a second sub-memory area, a third sub-memory area; wherein the first sub-storage area, the second sub-storage area, and the third sub-storage area each store data having different ranges of host access frequencies.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention, the first subzone stores therein data having a first sub-range host access frequency; the second sub-storage area stores therein data having a second sub-range host access frequency; and storing data having a third sub-range host access frequency in the third sub-storage area; wherein the first sub-range host access frequency is higher than the second sub-range host access frequency, which is higher than the third sub-range host access frequency.
Thus, by storing cold data, which is not frequently read and written by the host or the central processing unit, in the "cold area" (i.e., the second storage area), the amount of data stored in the dynamic random access memory can be increased. Meanwhile, since storage in the "cold zone" (i.e., the second storage area) is further classified according to the host access frequency, the rate performance of the module device can be further improved.
According to a preferred embodiment of the dual inline memory module arrangement of a storage level memory according to the invention, said first sub-storage area is a static random access memory cache module.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the second sub-storage area is a dynamic random access memory cache module.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention, the third sub-storage area is a non-volatile memory and a dynamic random access memory index module.
According to a preferred embodiment of the dual inline memory module arrangement of a storage level memory according to the present invention, the dual inline memory module arrangement further comprises a caching algorithm module, wherein the caching algorithm module judges the access frequency of data and writes data with a first sub-range host access frequency into the first sub-storage area; writing data having a second sub-range host access frequency into the second sub-storage area; writing data having a third sub-range host access frequency into the third sub-storage area.
In this way, the memory space of the module device can be expanded by storing cold data in the nonvolatile memory. Meanwhile, cold data with the lowest access frequency of the host or the central processing unit is stored in the nonvolatile memory, so that frequent reading and writing of the nonvolatile memory can be reduced, and the service life of the nonvolatile memory is prolonged.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the non-volatile memory stores a plurality of static data patterns, each static data pattern being 2mA byte of data; and the index module of the dynamic random access memory stores n multiplied by 2 to be written in by the hostmAn index of a static data pattern corresponding to the byte data.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the sram cache module and the cache algorithm module are located in a controller, wherein the controller performs the following operations:
in response to determining to write the n × 2 data according to a chip select signal and a command/address signalmWriting byte data into the SRAM cache module or the DRAM cache module, and writing the n × 2 data to be written into the SRAM cache module by the controllermWriting byte data into the static random access memory cache module or the dynamic random access memory cache module; and
in response to determining to write the n × 2 data according to a chip select signal and a command/address signalmWriting byte data to the non-volatile memory and the DRAM index module, the controller writing the nx2 to be writtenmWriting the index of the static data pattern corresponding to the byte data into the index module of the dynamic random access memory; wherein m and n are positive integers.
According to a preferred embodiment of the dual inline memory module arrangement of a storage level memory according to the invention, said controller writes said n to be written×2mWriting the index of the static data pattern corresponding to the byte data into the dynamic random access memory index module comprises:
n x 2 to be writtenmThe byte data is compared with the plurality of static data patterns, and
in response to the nx2 to be writtenmThe byte data corresponds to n static data patterns, and the indexes of the n static data patterns are written into the index module of the dynamic random access memory; and
in response to the nx2 to be writtenmkX 2 in one byte datamOne byte of data corresponds to k static data patterns, and (n-k) × 2mByte data does not correspond to static data patterns, an index of the k static data patterns is stored in the DRAM index block, the (n-k) x 2 is stored in the DRAM index blockmByte data is stored in the nonvolatile memory as a newly added static data pattern, and an index of the newly added static data pattern is stored in the dynamic random access memory index module, wherein k is a natural number, and n is more than or equal to k.
If the data to be written already exists in the static data pattern, the corresponding index is directly stored in the dynamic random access memory index module. If the data to be written does not exist in the static data pattern, the data to be written is stored in the nonvolatile memory as a newly added data pattern, and an index of the newly added static data pattern is stored in the dynamic random access memory index module.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the non-volatile memory stores a plurality of static data patterns, each static data pattern being 2mA byte of data; and the index module of the dynamic random access memory stores n multiplied by 2 to be read out by the hostmAn index of a static data pattern corresponding to the byte data.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the sram cache module and the cache algorithm module are located in a controller, wherein the controller performs the following operations:
in response to determining the n × 2 to be read out according to a chip select signal and a command/address signalmThe byte data is positioned in the cache module of the static random access memory or the cache module of the dynamic random access memory, and the controller directly reads out the data from the cache module of the static random access memory or the cache module of the dynamic random access memory; and
in response to determining the n × 2 to be read out according to a chip select signal and a command/address signalmThe byte data is located in the nonvolatile memory and the DRAM index module, and the controller reads out the n × 2 data to be read out from the DRAM index modulemAn index of a static data pattern corresponding to each byte of data, and according to the n × 2 data to be readmAn index of a static data pattern corresponding to the byte data, the data being read from the nonvolatile memory;
wherein m and n are positive integers.
Thus, the dual inline memory module device of a storage class memory according to the present invention can achieve the purpose of expanding the memory space with a nonvolatile memory, and can achieve high-speed writing of the nonvolatile memory and can improve the life of the nonvolatile memory.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, said m is 8.
It has been verified that m is 8, i.e. the data pattern is 256 bytes, is particularly preferred.
According to a preferred embodiment of the dual inline memory module arrangement of a storage level memory according to the invention, the n x 2 to be writtenmThe bits in the index of the byte data are:
the first plurality of bits represents a plane number;
the second plurality of bits represents a block number in the plane;
the third plurality of bits represents a page number in the block; and
the fourth plurality of bits represents a static data pattern number in the page.
According to a preferred embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the controller further comprises:
a command/address signal driving module for driving the command/address signal when the controller outputs the command/address signal to the dram module; and
and the data signal driving module is used for driving the data signal when the controller outputs the data signal to the dynamic random access memory module.
At least because of this, the dual inline memory module arrangement of storage level memory of the present invention enables high rate performance.
According to a second aspect of the present invention, there is provided a method of caching a dual inline memory module arrangement of a storage level memory, wherein the dual inline memory module arrangement comprises: a first storage area; and, a second storage area;
the caching method comprises the following steps:
storing data having a first range of host access frequencies in a first storage area; and
storing data having a second range of host access frequencies in a second storage area;
wherein the first range of host access frequencies is greater than the second range of host access frequencies.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises:
data having a first range of host access frequencies is stored in a dynamic random access memory.
According to a preferred embodiment of the caching method of a dual in-line memory module arrangement of a storage level memory according to the invention, the second memory area comprises a plurality of sub-memory areas, each storing data having a different range of host access frequencies.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, said second memory area comprises three sub memory areas, namely a first sub memory area, a second sub memory area, a third sub memory area; the first sub storage area, the second sub storage area and the third sub storage area respectively store data with different ranges of host access frequency.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises:
storing data having a first sub-range host access frequency in the first sub-storage area;
storing data having a second sub-range host access frequency in the second sub-storage area; and
storing data having a third sub-range host access frequency in the third sub-storage area;
wherein the first sub-range host access frequency is higher than the second sub-range host access frequency, which is higher than the third sub-range host access frequency.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises: and storing the data with the first sub-range host access frequency in the SRAM cache module.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises: and storing the data with the second sub-range host access frequency in a dynamic random access memory cache module.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises: data having a first sub-range of host access frequencies is stored in a non-volatile memory and a dynamic random access memory index module.
According to a preferred embodiment of the method for caching a dual inline memory module arrangement of a storage level memory according to the invention, said dual inline memory module arrangement further comprises a caching algorithm module; the caching method further comprises the following steps:
the cache algorithm module judges the access frequency of the data, and
writing data having a first sub-range host access frequency into the first sub-storage area;
writing data having a second sub-range host access frequency into the second sub-storage area; and
writing data having a third sub-range host access frequency into the third sub-storage area.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises:
storing a plurality of static data patterns in the non-volatile memory, each static data pattern being 2mA byte of data;
n x 2 to be written by hostmAnd the index of the static data pattern corresponding to the byte data is stored in the dynamic random access memory index module.
According to a preferred embodiment of the caching method of the dual inline memory module arrangement of a storage level memory according to the invention, the sram cache module and the caching algorithm module are located in a controller, the caching method further comprising the controller performing the following operations:
in response to determining to write the n × 2 data according to a chip select signal and a command/address signalmWriting byte data into the SRAM cache module or the DRAM cache module, the controller writing the n to be written×2mWriting byte data into the static random access memory cache module or the dynamic random access memory cache module;
in response to determining to write the n × 2 data according to a chip select signal and a command/address signalmWriting byte data to the non-volatile memory and the DRAM index module, the controller writing the nx2 to be writtenmWriting the index of the static data pattern corresponding to the byte data into the index module of the dynamic random access memory;
wherein m and n are positive integers.
According to a preferred embodiment of the method for caching a dual inline memory module arrangement of a storage level memory according to the invention, the controller writes the nx2 memory block to be written tomWriting the index of the static data pattern corresponding to the byte data into the dynamic random access memory index module comprises: n x 2 to be writtenmThe byte data is compared with the plurality of static data patterns, and
in response to the nx2 to be writtenmThe byte data corresponds to n static data patterns, and the indexes of the n static data patterns are written into the index module of the dynamic random access memory; and
in response to the nx2 to be writtenmkX 2 in one byte datamOne byte of data corresponds to k static data patterns, and (n-k) × 2mByte data does not correspond to static data patterns, an index of the k static data patterns is stored in the DRAM index module, and the (n-k) x 2 is stored in the DRAM index modulemByte data is stored in the nonvolatile memory as a newly added static data pattern, and an index of the newly added static data pattern is stored in the dynamic random access memory index module, wherein k is a natural number, and n is more than or equal to k.
According to a preferred embodiment of the caching method of a dual inline memory module arrangement of a storage level memory according to the invention, the caching method further comprises:
storing a plurality of static data patterns in the non-volatile memory, each static data pattern being 2mA byte of data;
n x 2 to be read by hostmAnd the index of the static data pattern corresponding to the byte data is stored in the dynamic random access memory index module.
According to a preferred embodiment of the caching method of the dual inline memory module arrangement of a storage level memory according to the invention, the sram cache module and the caching algorithm module are located in a controller, the caching method further comprising the controller performing the following operations:
in response to determining the n × 2 to be read out according to a chip select signal and a command/address signalmThe byte data is positioned in the cache module of the static random access memory or the cache module of the dynamic random access memory, and the controller directly reads out the data from the cache module of the static random access memory or the cache module of the dynamic random access memory; and
in response to determining the n × 2 to be read out according to a chip select signal and a command/address signalmThe byte data is located in the nonvolatile memory and the DRAM index module, and the controller reads out the n × 2 data to be read out from the DRAM index modulemAn index of a static data pattern corresponding to each byte of data, and according to the n × 2 data to be readmAn index of a static data pattern corresponding to the byte data, the data being read from the nonvolatile memory;
wherein m and n are positive integers.
According to a preferred embodiment of the method for caching a dual in-line memory module arrangement of a storage level memory according to the invention, said m is 8.
According to a preferred embodiment of the method for caching a dual inline memory module arrangement of a storage level memory according to the invention, said nx 2 memory to be written tomThe bits in the index of the byte data are:
the first plurality of bits represents a plane number;
the second plurality of bits represents a block number in the plane;
the third plurality of bits represents a page number in the block; and
the fourth plurality of bits represents a static data pattern number in the page.
According to a preferred embodiment of the method for caching a dual inline memory module arrangement of a storage level memory according to the invention, the controller further comprises:
a command/address signal driving module for driving the command/address signal when the controller outputs the command/address signal to the dram module; and
and the data signal driving module is used for driving the data signal when the controller outputs the data signal to the dynamic random access memory module.
It will be appreciated by a person skilled in the art that the technical effects as described in relation to the first aspect of the invention can be achieved according to the second aspect of the invention.
Drawings
The invention will be more readily understood by the following description in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of the signal flow and interface in a dual inline memory module DIMM of a prior art storage level memory SCM.
FIG. 2 is a diagram of memory space distribution in a dual inline memory module DIMM device of a storage level memory SCM according to one embodiment of the present invention.
Fig. 3 is a configuration in a dual inline memory module DIMM of a storage level memory SCM according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
FIG. 2 is a diagram of memory space distribution in a dual inline memory module DIMM device of a storage level memory SCM according to one embodiment of the present invention.
As shown in fig. 2, the memory space of the dual in-line memory module DIMM arrangement of the storage level memory SCM generally comprises a first memory area ("hot zone") 21 and a second memory area ("cold zone") 22.
In the present invention, "hot zone" refers to an area that is frequently read and written by a host or a central processing unit (i.e., storing data having a first range of host access frequencies), and "cold zone" refers to an area that is not frequently read and written by a host or a central processing unit (i.e., storing data having a second range of host access frequencies, the first range of host access frequencies being greater than the second range of host access frequencies). Whether to read and write frequently is defined according to specific situations and has no specific value.
The second storage area ("cold area") 22 is divided into a first sub-storage area 221, a second sub-storage area 222 … …, an nth sub-storage area 22n according to the access frequency of the host or the central processing unit, and these sub-storage areas 221, 222 … 22n each store data having different ranges of host access frequencies.
The division of the "cold zone" into three levels of storage cells is described in detail below in conjunction with FIG. 3.
Fig. 3 is a configuration in a dual inline memory module DIMM of a storage level memory SCM according to an embodiment of the present invention.
The dual in-line memory module DIMM of the storage level memory SCM in fig. 3 comprises a conventional dynamic random access memory DRAM 301. In the prior art, a conventional dynamic random access memory DRAM301 is a hot zone visible to the host or central processing unit.
The invention relates generally to read and write operations for "cold areas" including static random access memory SRAM cache module 306, dynamic random access memory DRAM cache module 302, non-volatile memory such as NAND Flash 303, and dynamic random access memory DRAM index module 304.
The inventive aspects of the present invention do not relate to the read and write operations to the "hot zone," i.e., the dynamic random access memory DRAM 301.
Regarding the read/write operation of the "hot zone", those skilled in the art will understand that the read/write operation is performed according to the burst operation of the DDR synchronous dynamic random access memory DDR, and each time, 4 bytes or 8 bytes of data are read/written. Since the invention of the present invention mainly relates to the operation of the "cold area", the detailed description of the read/write operation of the "hot area" is omitted here to avoid obscuring the gist of the present invention.
As further shown in fig. 3, the dual in-line memory module DIMM of the storage level memory SCM according to the present invention further comprises: a dynamic random access memory DRAM cache module 302; non-volatile memory such as nand flash 303; a dynamic random access memory DRAM index module 304; and a controller 31 including a SRAM cache block 306 and a cache algorithm block 305.
The DRAM cache module 302, the nonvolatile memory such as nand flash 303, the DRAM index module 304, and the SRAM cache module 306 of the present invention together form a "cold zone".
The SRAM cache block 306 forms a first level of storage in a "cold zone" for storing data having a first sub-range of host access frequencies (i.e., highest host access frequencies).
The DRAM cache module 302 constitutes a second level memory location in the "cold zone" for storing data having a second sub-range of host access frequencies (i.e., the next highest host access frequency).
The non-volatile memory, such as NAND Flash 303 and the dynamic random access memory DRAM index module 304 constitute a third level of storage locations in the "cold zone" for storing data having a third sub-range of host access frequencies (i.e., the host access frequencies are relatively low).
When the host writes data in the "cold area", the data is first written into the SRAM cache module 306, and after the SRAM cache module 306 is full, the data is written into the DRAM cache module 302. After both areas are full, the host starts counting the access frequency of the data stored in the addresses of both areas. Thereafter, data having a first sub-range of host access frequencies (i.e., the highest host access frequency) is stored in the static random access memory SRAM cache module 306, and data having a second sub-range of host access frequencies (i.e., the next highest host access frequency) is stored in the dynamic random access memory DRAM cache module 302, and data having a third sub-range of host access frequencies (i.e., the relatively lower host access frequencies) is stored in the non-volatile memory, such as NAND Flash 303, and the dynamic random access memory DRAM index module 304.
In general, the caching algorithm according to the present invention counts the access frequency in the "cold block" data and determines which of the first, second, and third level storage units the data is stored in. Meanwhile, after the cache algorithm determines which of the first-level, second-level and third-level storage units the data is stored in, a mapping relationship between the CPU address and the real address needs to be maintained.
The present invention divides the "cold zone" into three levels of storage cells with different ranges of host access frequencies. However, it should be understood that the "cold zone" of the present invention is not limited to the three-level memory cell, but may also include a one-level memory cell, a two-level memory cell, a four-level memory cell, and the like. Regarding the operation of the "cold region" including the one-stage memory cell, the two-stage memory cell, the four-stage memory cell, and the like, the operation of the "cold region" including the three-stage memory cell exemplified in the present invention is similar.
In a third level memory cell in the "cold zone", the non-volatile memory such as NAND Flash 303 stores a plurality of static data patterns, each of which is 2mA byte of data, where m is a positive integer. These data patterns have been stored in advance empirically at the time of shipment of the storage device. Preferably, m is 8. When m is 8, each static data pattern is 256 bytes of data. In the prior art, the typical size of each file in a file system is 4KB, i.e. 212A byte. When m is 8, each file can be conveniently patterned with 16 static dataThe rows represent.
In the third-level storage unit in the "cold area", the DRAM index module 304 stores an index of a static data pattern corresponding to data to be written by the host.
Each bit in the index of the data to be written is:
the first plurality of bits represents a plane (plane) number;
the second plurality of bits represents a block number in the plane;
the third plurality of bits represents a page number in the block; and
the fourth plurality of bits represents a static data pattern number in the page.
The specific setting of the index depends on the selected dual inline memory module DIMM of the storage level memory SCM.
For example, suppose that there are 2 planes in the nonvolatile memory of the dual in-line memory module DIMM, such as the NAND Flash 303, of the selected storage level memory SCM, there are 32 blocks in each plane, 512 pages in each block, and each page has a capacity of 16 kbytes (when each static data pattern is 256 bytes of data, each page stores 64 static data patterns). In this case, the index of the static data pattern corresponding to the data to be written is: a plane number of 1 bit + a block number of 5 bits + a page number of 9 bits + a static data pattern number of 6 bits.
In response to determining to write the n × 2 data according to a chip select signal and a command/address signalmWriting byte data into the SRAM cache module 306 or the DRAM cache module 302, the controller 31 writing the n × 2 data to be writtenmThe byte data is written into the SRAM cache module 306 or the DRAM cache module 302.
In response to determining nx2 host is to be written according to the chip select signal and the command/address signalmByte data is written to the non-volatile memory such as NAND Flash 303 and the dynamic random access memory DRAM index module 304The controller 31 writes the n × 2 data to be writtenmThe index of the static data pattern corresponding to each byte of data is written into the DRAM index module 304, where n and m are positive integers.
If the data size to be written by the host does not reach the data size of a single static data pattern, i.e. 2mOne byte, then wait until the size of the data to be written by the host is at least equal to the data size of a single static data pattern, i.e., equal to 2mA byte.
The controller 31 writes the n × 2 to be writtenmWriting the index of the static data pattern corresponding to the byte data into the DRAM index module 304 includes: n x 2 to be writtenmThe byte data is compared with the plurality of static data patterns, and
in response to the nx2 to be writtenmWriting indexes of n static data patterns into the DRAM index module 304, where the n bytes of data correspond to the n static data patterns;
in response to the nx2 to be writtenmkX 2 in one byte datamOne byte of data corresponds to k static data patterns, and (n-k) × 2mByte data does not correspond to a static data pattern, an index of the k static data patterns is stored in the DRAM index module 304, and the (n-k) x 2mByte data is stored in the non-volatile memory, such as NAND Flash 303, as a newly added static data pattern, and an index of the newly added static data pattern is stored in the DRAM index module 304, where k is a natural number and n ≧ k.
The above method is specifically explained below assuming that m is 8, n is 6, and k is 2.
When the controller 31 writes the 6 × 2 to be written8When the index of the static data pattern corresponding to the byte data is written into the DRAM index module 304, the 6 × 2 data to be written is written8Number of bytesIs compared with the plurality of static data patterns, and
in response to the 6 x 2 to be written8Byte data corresponds to 6 static data patterns, and indexes of the 6 static data patterns are written into the DRAM index module 304;
in response to the 6 x 2 to be written82 x 2 in one byte data8The byte data corresponds to 6 static data patterns, and (6-2) × 28＝4×28Byte data does not correspond to static data patterns, an index of the 2 static data patterns is stored in the DRAM index module 304, and the (6-2) x 2 is stored in the DRAM index module8＝4×28Byte data is stored in the non-volatile memory, such as NAND Flash 303, as a newly added static data pattern, and an index of the newly added static data pattern is stored in the DRAM index module 304.
In an embodiment of the dual in-line memory module arrangement of a storage level memory according to the invention, the controller 31 further comprises:
a command/address CA signal driving module 307 for driving a command/address CA signal when the controller 31 outputs the command/address CA signal to the DRAM module 301;
and a data DQ signal driving module 308 configured to drive the data DQ signal when the controller 31 outputs the data DQ signal to the DRAM module 301.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. It is to be understood that the scope of the invention is defined by the claims.

Claims (10)

1. A dual in-line memory module arrangement of a storage level memory, the dual in-line memory module arrangement comprising:
a first storage area storing data having a first range of host access frequencies; and
a second storage area storing data having a second range of host access frequencies;
wherein the first range of host access frequencies is greater than the second range of host access frequencies.
2. The dual in-line memory module arrangement of storage level memory according to claim 1,
the first storage area is a dynamic random access memory.
3. The dual in-line memory module arrangement of storage level memory according to claim 1,
the second storage area includes a plurality of sub-storage areas each storing data having a different range of host access frequencies.
4. The dual in-line memory module arrangement of storage level memory according to claim 3,
the second memory area includes three sub memory areas, namely:
a first sub-storage area,
A second sub-storage area,
A third sub-memory area;
wherein the first sub-storage area, the second sub-storage area, and the third sub-storage area each store data having different ranges of host access frequencies.
5. The dual in-line memory module arrangement of storage level memory according to claim 4,
the first sub-storage area stores data with a first sub-range host access frequency;
the second sub-storage area stores therein data having a second sub-range host access frequency; and
the third sub-storage area stores therein data having a third sub-range host access frequency;
wherein the first sub-range host access frequency is higher than the second sub-range host access frequency, which is higher than the third sub-range host access frequency.
6. A method of caching a dual in-line memory module device of a storage class memory, the dual in-line memory module device comprising: a first storage area; and, a second storage area;
the caching method comprises the following steps:
storing data having a first range of host access frequencies in a first storage area; and
storing data having a second range of host access frequencies in a second storage area;
wherein the first range of host access frequencies is greater than the second range of host access frequencies.
7. The method of caching a dual in-line memory module device of a storage level memory according to claim 6,
the caching method further comprises the following steps:
data having a first range of host access frequencies is stored in a dynamic random access memory.
8. The method of caching a dual in-line memory module device of a storage level memory according to claim 6,
the second storage area includes a plurality of sub-storage areas each storing data having a different range of host access frequencies.
9. The method of caching a dual in-line memory module device for storage level memory according to claim 8,
the second storage area comprises three sub storage areas, namely a first sub storage area, a second sub storage area and a third sub storage area;
wherein the first sub-storage area, the second sub-storage area, and the third sub-storage area each store data having different ranges of host access frequencies.
10. The method of caching a dual in-line memory module device of a storage level memory according to claim 9,
the caching method further comprises the following steps:
storing data having a first sub-range host access frequency in the first sub-storage area;
storing data having a second sub-range host access frequency in the second sub-storage area; and
storing data having a third sub-range host access frequency in the third sub-storage area;
wherein the first sub-range host access frequency is higher than the second sub-range host access frequency, which is higher than the third sub-range host access frequency.
CN202010230514.1A 2020-03-27 2020-03-27 Dual in-line memory module device of storage-level memory and caching method thereof Pending CN111274163A (en)

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