CN111273495A

CN111273495A - Display module, driving method of array substrate of display module and display device

Info

Publication number: CN111273495A
Application number: CN202010077879.5A
Authority: CN
Inventors: 邬豪轩; 杨镇豪
Original assignee: BOE Technology Group Co Ltd; Gaochuang Suzhou Electronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Gaochuang Suzhou Electronics Co Ltd
Priority date: 2020-02-01
Filing date: 2020-02-01
Publication date: 2020-06-12
Anticipated expiration: 2040-02-01
Also published as: CN111273495B

Abstract

The application discloses a display module and a driving method of an array substrate of the display module, and a display device, and relates to the technical field of display. The array substrate of the display module comprises a plurality of pixels, at least one target pixel exists in each partition along the extension direction of the data line, the target pixel can transmit working voltage during light emitting to the source electrode driving circuit through the detection signal line, and the source electrode driving circuit can adjust the voltage conversion rate of the source electrode driving circuit based on the working voltage. Since the adjusted voltage conversion rate is inversely related to the working voltage, and the time required for writing the data signal into the pixel by the data line is shorter as the voltage conversion rate is higher, the voltage conversion rate is flexibly adjusted based on the working voltage, the problem that the data signal cannot be reliably written into the pixel within the scanning time of the gate line due to the larger RC of the data line can be solved, the data signals written into the pixels in the same column can be ensured to be the same, and the display uniformity of the display device is better.

Description

Display module, driving method of array substrate of display module and display device

Technical Field

The disclosure relates to the technical field of display, and in particular to a display module, a driving method of an array substrate of the display module, and a display device.

Background

Liquid Crystal Display (LCD) devices are widely used in the display field due to their advantages of small size, low power consumption, high refresh rate, and the like.

In the related art, an array substrate of an LCD device generally includes: the pixel structure comprises a plurality of grid lines, a plurality of data lines and a plurality of pixels arranged in an array, wherein each grid line can be connected with one row of pixels and is used for providing a grid driving signal for the row of pixels. Each data line may be connected to a column of pixels for providing data signals to the column of pixels. And the data line can write the data signal into the pixel when the gate line provides the gate driving signal to the pixel.

However, since the parasitic resistance R and the parasitic capacitance C on the data line are increased more and more as the length of the data line increases, the larger the RC, the longer the time required for writing the data signal into the pixel is, and since the time for supplying the gate driving signal to each gate line is generally the same, the size of the data signal written into each pixel in the same column by each data line may be different, and the display uniformity of the LCD device is poor.

Disclosure of Invention

The disclosure provides a display module, a driving method of an array substrate of the display module and a display device, and can solve the problem of poor display uniformity of the display device in the related art. The technical scheme is as follows:

in one aspect, a display module is provided, the display module includes: the array substrate and the source electrode driving circuit; the array substrate includes: the pixel array structure comprises at least one detection signal line, a plurality of pixels arranged in an array, a plurality of grid lines connected with a plurality of rows of the pixels in a one-to-one corresponding mode, and a plurality of data lines connected with a plurality of columns of the pixels in a one-to-one corresponding mode, wherein a source electrode driving circuit is respectively connected with the plurality of data lines and the at least one detection signal line;

the array substrate is provided with a plurality of subareas arranged along the extending direction of the data lines, at least one target pixel exists in each subarea, and each target pixel is respectively connected with one grid line, one data line and one detection signal line;

each target pixel is used for responding to a grid driving signal provided by a grid line connected with the target pixel and a data signal provided by a data line connected with the target pixel to emit light, and is used for responding to a grid driving signal provided by a grid line connected with the target pixel and outputting an operating voltage when the target pixel emits light to the source driving circuit through a detection signal line connected with the target pixel;

the source electrode driving circuit is used for adjusting the voltage conversion rate of the source electrode driving circuit according to the working voltage and providing data signals for the data lines according to the adjusted voltage conversion rate, wherein the size of the adjusted voltage conversion rate is inversely related to the size of the working voltage.

Optionally, each of the target pixels includes: a drive circuit, a detection circuit, and a light emitting element;

the driving circuit is respectively connected with one grid line, one data line and the light-emitting element, the driving circuit is used for responding to a grid driving signal provided by the grid line connected with the driving circuit and outputting a data signal provided by the data line connected with the driving circuit to the light-emitting element, and the light-emitting element is used for emitting light under the driving of the data signal;

the detection circuit is connected with one grid line, the light-emitting element and one detection signal line respectively, and the detection circuit is used for responding to a grid driving signal provided by the grid line connected with the detection circuit and outputting working voltage when the light-emitting element emits light to the source electrode driving circuit through the detection signal line connected with the detection circuit.

Optionally, the driving circuit includes: a drive transistor, the detection circuit comprising: a detection transistor;

the grid electrode of the driving transistor is connected with one grid line, the first electrode of the driving transistor is connected with one data line, and the second electrode of the driving transistor is connected with the light-emitting element;

the gate of the detection transistor is connected to one of the gate lines, the first electrode of the detection transistor is connected to the light emitting element, and the second electrode of the detection transistor is connected to one of the detection signal lines.

Optionally, there is one target pixel in each of the partitions, and the target pixels in the partitions are located in the same column.

Optionally, the number of pixel rows included in each of the partitions is the same, and the target pixels in each of the partitions are arranged at equal intervals.

Optionally, the target pixel in each of the partitions is located in a first column.

Optionally, a plurality of target pixels located in the same row exist in each of the partitions; the source driving circuit includes: a plurality of driving sub-circuits, the array substrate comprising: a plurality of the detection signal lines;

the plurality of target pixels located in the same row are connected to different ones of the driving sub-circuits through different ones of the detection signal lines.

Optionally, two target pixels located in the same row exist in each partition, and of the two target pixels located in the same row, one target pixel is located in the first column, and the other target pixel is located in the last column; the source driving circuit includes: a first driving sub-circuit, a second driving sub-circuit and a third driving sub-circuit arranged along a scanning direction of the gate line; the array substrate includes: two of the detection signal lines;

the target pixel in the first column is connected with the first driving sub-circuit and the second driving sub-circuit through one detection signal line, and the target pixel in the last column is connected with the third driving sub-circuit through another detection signal line;

or, the target pixel in the first column is connected to the first driving sub-circuit through one detection signal line, and the target pixel in the last column is connected to the second driving sub-circuit and the third driving sub-circuit through another detection signal line.

In another aspect, a driving method of an array substrate in a display module is provided, where the driving method is applied to a source driving circuit in the display module, and the method includes:

providing data signals to a plurality of data lines;

receiving a working voltage output by a target pixel through a detection signal line, wherein the working voltage is a voltage when the target pixel responds to a grid driving signal provided by a grid line connected with the target pixel and a data signal provided by a data line connected with the target pixel and emits light;

adjusting a voltage conversion rate according to the working voltage, wherein the adjusted voltage conversion rate is inversely related to the working voltage;

and providing data signals to the plurality of data lines according to the adjusted voltage slew rates.

In still another aspect, there is provided a display device including: a gate driving circuit, and the display module set according to the above aspect;

the grid driving circuit is connected with a plurality of grid lines in the array substrate and used for providing grid driving signals for the grid lines.

The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least can include:

the disclosure provides a display module, a driving method of an array substrate of the display module and a display device.

The embodiment of the disclosure provides a display module, a driving method of an array substrate of the display module and a display device, wherein the array substrate of the display module comprises a plurality of pixels, at least one target pixel exists in each partition along the extension direction of a data line, the target pixel can transmit working voltage generated when the target pixel emits light to a source electrode driving circuit through a detection signal line, and the source electrode driving circuit can adjust the voltage conversion rate of the source electrode driving circuit based on the working voltage. Since the adjusted voltage conversion rate is inversely related to the working voltage, and the time required for writing the data signal into the pixel by the data line is shorter as the voltage conversion rate is higher, the voltage conversion rate is flexibly adjusted based on the working voltage, the problem that the data signal cannot be reliably written into the pixel within the scanning time of the gate line due to the larger RC of the data line can be solved, the data signals written into the pixels in the same column can be ensured to be the same, and the display uniformity of the display device is better.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display module according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a target pixel provided in an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another target pixel provided in the embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another display module provided in the embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display module provided in the embodiment of the present disclosure;

fig. 6 is a flowchart illustrating a driving method of an array substrate in a display module according to an embodiment of the disclosure;

fig. 7 is a timing diagram of signal lines in an array substrate according to an embodiment of the disclosure;

fig. 8 is a timing diagram of signal lines in an array substrate according to the related art;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail below with reference to the accompanying drawings.

The transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present disclosure are mainly switching transistors according to the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. Alternatively, the source may be referred to as a first pole and the drain may be referred to as a second pole, or the drain may be referred to as a first pole and the source may be referred to as a second pole. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the signal output end is a drain. In addition, the switching transistor used in the embodiments of the present disclosure may be any one of a P-type switching transistor that is turned on when the gate is at a low level and turned off when the gate is at a high level, and an N-type switching transistor that is turned on when the gate is at a high level and turned off when the gate is at a low level.

With the development of display technology, the refresh rate of display devices becomes higher and higher, for example, the refresh rate of most display devices can reach 144 hertz (Hz) or even 240 Hz. Here, the refresh rate is the number of times that the display device can be refreshed per second, and may be referred to as a frame rate (frame rate).

However, the higher the refresh rate, the shorter the scanning time of each gate line (gate line) in the display device, and correspondingly, the shorter the time for writing (i.e., charging) a data signal to a pixel by the data line (data line). And, the RC of each data line becomes larger and larger along a direction away from a source integrated circuit (source IC) due to the length increase. If the side of each data line close to the source driving circuit is called a near end, and the side far away from the source driving circuit is called a far end, then the RC of the far end of each data line is larger than that of the near end. The larger the RC is, the slower the data line writes data signals to the pixels (i.e., charges the pixels), which may cause the data signal written by the far end of the data line to the pixel connected to the data line to be smaller than the data signal written by the near end of the data line to the pixel connected to the data line in the same gate line scanning time. That is, part of pixels in the same column are charged insufficiently, and part of pixels are charged to be saturated, so that the display device has the problem of abnormal display, such as occurrence of poor bright and dark lines or grid lines.

The embodiment of the disclosure provides a display module, where a source driving circuit included in the display module can ensure that each data line can reliably write data signals into a row of pixels connected to the data line within the same gate line scanning time by detecting a working voltage when the pixels emit light in real time and dynamically adjusting a voltage conversion rate (slew rate) of the working voltage based on the working voltage, so as to improve display uniformity, and the method may also be referred to as voltage feedback detection. Wherein, the voltage conversion rate refers to: the amplitude of the voltage rise within a specified time is, for example, a square wave voltage, that is, the time required for the square wave voltage to rise from a wave trough to a wave crest.

Fig. 1 is a schematic structural diagram of a display module according to an embodiment of the disclosure. As shown in fig. 1, the display module may include: the array substrate 00 and the source driving circuit 01. The array substrate 00 may include: the pixel array includes at least one detection signal line SL, a plurality of pixels 10 arranged in an array, a plurality of gate lines G connected to the plurality of rows of pixels 10 in a one-to-one correspondence, and a plurality of data lines D connected to the plurality of columns of pixels 10 in a one-to-one correspondence.

Referring to fig. 1, the array substrate 00 has a plurality of partitions a arranged along an extending direction of data lines D. At least one target pixel 10 exists in each of the partitions a, and each of the target pixels 10 may be connected to one gate line G, one data line D, and one detection Signal Line (SL), respectively. The source driving circuit 01 may be connected to a plurality of data lines D and at least one detection signal line SL, respectively. That is, the pixel 10 connected to the detection signal line SL shown in fig. 1 is the target pixel.

For example, referring to fig. 1, the array substrate 00 in the display module shown therein includes one detection signal line SL, m × n pixels 10, m data lines D1 to Dm, and n gate lines G1, Gi to Gn, i being a positive integer less than n. And the array substrate 00 has K partitions a1 to Ak, in each of which there are a plurality of target pixels 10 connected to the source drive circuit 01 through the detection signal lines SL.

In the embodiment of the present disclosure, each target pixel 10 may emit light in response to a gate driving signal supplied from a gate line G to which it is connected and a data signal supplied from a data line D to which it is connected, and may output an operating voltage at the time of its light emission to the source driving circuit 01 through a detection signal line SL to which it is connected in response to a gate driving signal supplied from a gate line G to which it is connected.

For example, each target pixel 10 may emit light under the driving of a data signal when the gate line G to which it is connected supplies the gate driving signal and the data line D to which it is connected supplies the data signal. In addition, each target pixel 10 can also output an operating voltage at the time of its light emission to the source drive circuit 01 through the detection signal line SL connected thereto when the gate line G connected thereto supplies a gate drive signal.

The source driving circuit 01 may adjust a voltage slew rate of the source driving circuit 01 according to the received operating voltage, and provide the data signals to the plurality of data lines D according to the adjusted voltage slew rate, where a magnitude of the adjusted voltage slew rate is inversely related to a magnitude of the operating voltage. That is, the smaller the operating voltage, the larger the adjusted voltage conversion rate; the larger the operating voltage, the smaller the adjusted voltage slew rate. Moreover, for writing data signals with the same size into the pixel 10, that is, for each data line D, the larger the voltage conversion rate, the shorter the time required for the data line D to write the data signals into the pixel 10; the smaller the voltage slew rate, the longer the time required for the data line D to write the data signal to the pixel 10.

Alternatively, since the voltage slew rate of the source driving circuit 01 is related to the current magnitude supplied to the data line D by the source driving circuit 01, the source driving circuit 01 can adjust the voltage slew rate by adjusting the current output to the data line D.

For example, if the received operating voltage is small, the source driving circuit 01 can increase the voltage conversion rate by increasing the current output to the data line D, that is, increase the efficiency of writing the data signal to the data line D (which may also be referred to as increasing the output thrust), thereby avoiding the problem that the data signal cannot be reliably written to the pixel 10 by the data line D within the gate line scanning time due to the large RC, and further effectively improving the problem of bright and dark lines or grid lines that may occur when the display device displays.

If the received operating voltage is large, the source driving circuit 01 may reduce the voltage slew rate thereof by reducing the current output to the data line D, i.e., reduce the efficiency of writing the data signal to the data line D. Because the RC of the near end of each data line D is small, correspondingly, the time for writing the data signal into the pixel 10 by the near end may be shorter than the gate line scanning time, that is, the data line D may rapidly realize the charging of the pixel 10, and therefore, by reducing the voltage conversion rate when the working voltage is large, the power consumption of the source driving circuit 01 may be reduced.

In summary, the embodiment of the present disclosure provides a display module, where an array substrate of the display module includes a plurality of pixels, and at least one target pixel exists in each partition along an extending direction of a data line, the target pixel can transmit a working voltage during light emission thereof to a source driving circuit through a detection signal line, and the source driving circuit can adjust a voltage conversion rate thereof based on the working voltage. Because the adjusted voltage conversion rate is inversely related to the working voltage, and the higher the voltage conversion rate is, the shorter the time required for writing the data signal into the pixel is, the voltage conversion rate is flexibly adjusted based on the working voltage, the problem that the data signal cannot be reliably written into the pixel within the scanning time of the grid line due to the larger RC of the data line can be solved, the data signals written into the pixels in the same column can be ensured to be the same in size, and the display uniformity of the display device is better.

Fig. 2 is a schematic structural diagram of a target pixel according to an embodiment of the present disclosure. As shown in fig. 2, each target pixel 10 may include: a drive circuit 101, a detection circuit 102, and a light emitting element 103.

The driving circuit 101 may be connected to one gate line G, one data line D, and the light emitting element 103, respectively. The driving circuit 101 may output a data signal supplied from the data line D to which it is connected to the light emitting element 103 in response to a gate driving signal supplied from the gate line G to which it is connected.

For example, the driving circuit 101 may output a data signal supplied from the data line D to which it is connected to the light emitting element 103 to which it is connected when the gate line G to which it is connected supplies a gate driving signal. The light emitting element 103 can emit light under the driving of the data signal.

The detection circuit 102 may be connected to one gate line G, the light emitting element 103, and one detection signal line SL, respectively. The detection circuit 102 can output an operating voltage when the light emitting element 103 emits light to the source drive circuit 01 through a detection signal line SL connected thereto in response to a gate drive signal supplied from a gate line G connected thereto. Also, referring to fig. 2, the gate lines G to which the driving circuit 101 and the detecting circuit 102 are connected in each target pixel 10 are the same gate line G. Accordingly, the drive circuit 101 and the detection circuit 102 in each target pixel 10 can operate simultaneously. Since each gate line G sequentially supplies a gate driving signal in each frame of scanning, it is possible to reliably prevent signals output from the detection signal line SL to the source driving circuit 01 from interfering with each other when different gate lines G are scanned.

For example, the detection circuit 102 may output an operating voltage when the light emitting element 103 emits light to the source driving circuit 01 through the detection signal line SL connected thereto when the gate line G connected thereto supplies the gate driving signal.

Fig. 3 is a schematic structural diagram of another target pixel provided in the embodiment of the present disclosure. As shown in fig. 3, the driving circuit 101 may include: driving the transistor T1. The detection circuit 102 may include: the transistor M1 is detected.

The gate electrode of the driving transistor T1 may be connected to one gate line G, the first electrode of the driving transistor T1 may be connected to one data line D, and the second electrode of the driving transistor T1 may be connected to the light emitting element 103.

The gate of the sensing transistor M1 may be connected to a gate line G, the first pole of the sensing transistor M1 may be connected to the light emitting element 103, and the second pole of the sensing transistor M1 may be connected to a sensing signal line SL.

Optionally, the array substrate 00 may be an array substrate of an LCD display module, or the array substrate 00 may be an array substrate of an organic light-emitting diode (OLED) display module. When the array substrate 00 is an array substrate of an LCD display module, the light emitting element 103 may include a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode. When the array substrate 00 is an array substrate of an OLED display module, the light emitting device 103 can be an OLED. The embodiment of the present disclosure takes the array substrate as an example of an LCD display module.

As an alternative implementation: fig. 4 is a schematic structural diagram of another display module provided in the embodiment of the present disclosure. As shown in fig. 4, there may be only one target pixel 10 in each partition a, and the target pixels 10 in the respective partitions a may be located in the same column. Since the RC variation on each data line D is substantially equivalent, by providing only one target pixel 10 in each of the partitions a, it is possible to reduce the number of detection signal lines to be arranged and to reduce the cost while ensuring the display uniformity.

Optionally, in the embodiment of the present disclosure, the number of rows of the pixels 10 included in each partition a may be the same, and the target pixels 10 in each partition a may be arranged at equal intervals. Since the RC variation of each data line D is equivalent at the same length, that is, if n rows of pixels are included, the RC variation of the data line D is equivalent every i rows. Therefore, the display uniformity of the display device can be further ensured by the equidistant arrangement.

Alternatively, the target pixels 10 in the respective partitions a may all be located in the first column. By disposing the target pixels 10 in the first column, the wiring difficulty and the wiring cost of the detection signal lines SL can be reduced.

For example, referring to fig. 4, the structure of the display module is described by taking the display module applied to a Full High Definition (FHD) display device, and the arrangement of the plurality of pixels 10 included in the array substrate of the display module is one gate line G, one data line D, and zigzag row inversion (i.e. 1G1D Zig Zag Column inversion).

As shown in fig. 4, the array substrate 00 includes 1080 rows of pixels, and the array substrate 00 has six partitions a1 to a6 along the extending direction of the data lines D, i.e., perpendicular to the direction of the gate lines G. Wherein each partition a comprises 180 rows of pixels, and only the first column and the first row in each partition a has one target pixel 10. That is, for each partition a, the first pixel 10 located in the partition a is the target pixel. With reference to fig. 4, in the array substrate 00, the first pixel 10 connected to the first gate line G1 is a target pixel, the first pixel 10 connected to the 181 th gate line G181 is a target pixel, the first pixel 10 connected to the 361 th gate line G361 is a target pixel, the first pixel 10 connected to the 541 st gate line G541 is a target pixel, the first pixel 10 connected to the 721 gate line G721 is a target pixel, and the first pixel 10 connected to the 901 th gate line G901 is a target pixel. Note that fig. 4 does not show each row of pixels 10 included in each partition a.

Alternatively, each row of pixels 10 included in the array substrate 00 shown in fig. 4 may be sequentially arranged according to the order of the green pixels 10, the blue pixels 10, and the red pixels 10. In addition, since the six target pixels 10 are all located in different rows, that is, all connected to different gate lines G, and each gate line G does not output a gate driving signal at the same time, referring to fig. 4, the six target pixels 10 shown therein can be connected to the source driving circuit 01 through the same detection signal line S1, and this connection manner can further reduce the cost, and can avoid occupying more space for wiring, which is beneficial to the implementation of a narrow frame. That is, in the embodiment of the present disclosure, the target pixels 10 located in different rows may be connected to the source driving circuit 01 through the same detection signal line SL. Of course, each target pixel 10 may also be connected to the source driving circuit 01 through a different detection signal line SL, for example, in conjunction with fig. 4, the six target pixels 10 may be connected to the source driving circuit 01 through six detection signal lines SL and sources, respectively. The number of the detection signal lines SL is not limited in the embodiment of the present disclosure.

As another alternative implementation: there may be a plurality of target pixels 10 located in the same row in each partition a. The source driving circuit 01 may include: the plurality of driving sub-circuits, the array substrate 00 may include: a plurality of detection signal lines SL. Moreover, a plurality of target pixels 10 located in the same row may be connected to different driving sub-circuits through different detection signal lines SL.

Since a plurality of target pixels located in the same row are connected to the same gate line G, the source driving circuit 01 is connected to different detection signal lines SL, so that the source driving circuit 01 can be prevented from receiving a plurality of operating voltages at the same time, and the operational reliability of the source driving circuit 01 can be ensured.

For example, fig. 5 is a schematic structural diagram of another display module provided in the embodiment of the present disclosure. As shown in fig. 5, it is also exemplified that the array substrate 00 includes 1080 rows of pixels, having six partitions a1 to a6, each partition a including 180 rows of pixels. Referring to fig. 5, only two target pixels 10 located on the first row exist in each partition a. In the two target pixels 10, one target pixel 10 is located in the first column, and the other target pixel 10 is located in the last column. In addition, referring to fig. 5, the source driving circuit 01 may include: the first drive sub-circuit 011, the second drive sub-circuit 012, and the third drive sub-circuit 013 are arranged in this order along the scanning direction of the gate line G. The array substrate 00 includes: two detection signal lines SL.

Among them, the target pixel 10 located in the first column may be connected to the first driving sub-circuit 011 and the second driving sub-circuit 012 through one detection signal line SL, and the target pixel 10 located in the last column may be connected to the third driving sub-circuit 013 through another detection signal line SL.

Alternatively, the target pixel 10 in the first column may be connected to the first drive sub-circuit 011 through one detection signal line SL, and the target pixel 10 in the last column may be connected to the second drive sub-circuit 012 and the third drive sub-circuit 013 through another detection signal line SL.

For example, referring to fig. 5, the target pixel 10 in the first column is shown to be connected to the first driving sub-circuit 011 and the second driving sub-circuit 012 through one detection signal line SL, and the target pixel 10 in the last column is connected to the third driving sub-circuit 013 through another detection signal line SL.

And optionally, the target pixel 10 in the first column is connected with only the first driving sub-circuit 011, and the first driving sub-circuit 011 can be connected with the second driving sub-circuit 012, i.e. the target pixel 10 in the first column can be connected with the second driving sub-circuit 012 through the first driving sub-circuit 011. Through the connection mode, when a plurality of driving sub-circuits are included, the voltage conversion rate of each driving sub-circuit can be rapidly adjusted on the premise of saving the wiring cost.

Alternatively, referring to fig. 4, the source driving circuit 01 shown therein may also include a first driving sub-circuit 011, a second driving sub-circuit 012, and a third driving sub-circuit 013. Alternatively, for the display module shown in fig. 4, the six target pixels 10 may be connected with only the first driving sub-circuit 011, and the first driving sub-circuit 011 may be connected with the second driving sub-circuit 012 and the third driving sub-circuit 013 respectively, i.e. the target pixels 10 may be connected with the other two driving sub-circuits 012 and 013 respectively through the first driving sub-circuit 011. By the connection mode, when each row only comprises one target pixel 10 and comprises a plurality of driving sub-circuits, on the premise of saving the wiring cost, the target pixel 10 can rapidly output the working voltage to each driving sub-circuit, so that each driving sub-circuit can rapidly adjust the voltage conversion rate.

Of course, for the display modules shown in fig. 4 and 5, the target pixel 10 may also be directly connected to two driving sub-circuits or three driving sub-circuits through the detection signal line SL, respectively.

In addition, referring to fig. 4, a Flexible Printed Circuit (FPC) on which the three driver sub-circuits are provided, that is, FPCs 1, 2, and 3 shown in fig. 4 are also schematically shown. And the array substrates 00 shown in fig. 4 and 5 each include 5800 data lines D1 to D5800.

It should be noted that the number of target pixels in each partition a mentioned in the embodiments of the present disclosure is not limited to the number shown in fig. 4 and 5, for example, in order to achieve the accuracy of adjusting the voltage slew rate, a greater number of target pixels 10 may exist in each partition a. By the arrangement mode, individual adjustment of charging of the inter-wafer difference can be avoided under the condition that the RC is different due to the inter-wafer difference in the production process.

In the above embodiments, each transistor is an N-type transistor, for example. Of course, a P-type transistor may be used for each transistor.

Fig. 6 is a driving method of an array substrate in a display module according to an embodiment of the disclosure, which can be applied to the source driving circuit 01 in the display module shown in any one of fig. 1, 4 and 5. As shown in fig. 6, the method may include:

step 601, providing data signals to a plurality of data lines.

Alternatively, the source driving circuit 01 may first provide data signals to the plurality of data lines connected thereto according to the initial voltage slew rate, respectively.

Step 602, receiving a working voltage output by the target pixel through the detection signal line.

The operating voltage may be a voltage when the target pixel emits light in response to a gate driving signal provided by a gate line connected thereto and a data signal provided by a data line connected thereto.

Alternatively, when the gate line provides the gate driving signal, the data line may output the data signal provided by the source driving circuit to the pixel connected thereto, and then the pixel may emit light under the driving of the data signal. In addition, the target pixel may be driven by the gate driving signal to output an operating voltage when the target pixel emits light to the source driving circuit through the detection signal line connected thereto. That is, the source driver circuit may receive the operating voltage output from the target pixel through the detection signal line.

Step 603, adjusting the voltage conversion rate according to the working voltage.

After receiving the working voltage, the source driving circuit may dynamically adjust its voltage slew rate in real time according to the received working voltage, for example, adjust its voltage slew rate by adjusting its output current. And, the magnitude of the adjusted voltage slew rate may be inversely related to the magnitude of the operating voltage. Optionally, a corresponding relationship between the working voltage and the slew rate may be preset in the source driving circuit, and after receiving the working voltage, the source driving circuit may directly call the corresponding relationship to reliably determine and adjust the voltage slew rate.

Step 604, providing data signals to the plurality of data lines according to the adjusted voltage slew rates.

Finally, the source driving circuit can provide the data signals to the plurality of data lines again according to the adjusted voltage slew rate. Because the voltage conversion rate is inversely related to the working voltage, and the higher the voltage conversion rate is, the faster the data signal writing time of the data lines to the pixels is, the flexible adjustment of the voltage conversion rate can ensure that the data signals written to the pixels in the same column can be the same in the same grid line scanning time of each data line, and the display uniformity is ensured.

In summary, the embodiments of the present disclosure provide a driving method for an array substrate in a display module, in which a source driving circuit can adjust a voltage conversion rate of a target pixel based on a working voltage output by the target pixel. Since the adjusted voltage conversion rate is inversely related to the operating voltage, and the time required for writing the data signal into the pixel by the data line is shorter as the voltage conversion rate is higher, the problem that the data signal cannot be reliably written into the pixel within the scanning time of the gate line due to the larger RC of the data line, that is, the problem that the pixel is insufficiently charged due to the larger RC, can be avoided by flexibly adjusting the voltage conversion rate based on the operating voltage. The data signals written to the pixels in the same column can be guaranteed to be the same in size, and the display device is good in display uniformity.

Taking the display module shown in fig. 4 and the target pixel shown in fig. 3, the display module is a liquid crystal display module as an example, and each transistor included in the display module is an N-type transistor, so as to introduce the working principle of the display module provided in the embodiment of the present disclosure.

Fig. 7 is a timing diagram of signal lines in an array substrate according to an embodiment of the disclosure, which illustrates scanning of an nth frame (frame n) and an n +1 th frame (frame n + 1). Referring to fig. 7, each gate line G included in the array substrate 00 may sequentially supply a gate driving signal when each frame is scanned.

Taking the target pixel 10 in the first partition a1 as an example, when the gate line G1 provides the gate driving signal, in the first row of pixels 10 connected to the gate line G1, the driving transistor T1 included in each pixel 10 is turned on, and the detecting transistor M1 in the target pixel 10 (i.e., the first pixel) connected to the gate line G1 is also turned on at the same time. The data lines D1 to D5800 (illustrated as the data line D1 in the figure) respectively supply data signals to the light emitting elements 103 connected thereto through the driving transistors T1 connected thereto, and the pixels in the first row emit light. Meanwhile, the detection transistor M1 included in the target pixel can detect an operating voltage when the light emitting element 103 of the pixel emits light, and output the operating voltage to the first drive sub circuit 011, the second drive sub circuit 012, and the third drive sub circuit 013 included in the source drive circuit 01 through the detection signal line SL. Then, the three driving sub-circuits can flexibly adjust the voltage conversion rate according to the received working voltage. And the adjusted voltage slew rate is inversely related to the operating voltage.

When the other gate line G (e.g., the gate line G2) except for the gate line G1 starts to supply the gate driving signal, the gate line G1 stops supplying the gate driving signal. At this time, the driving transistor T1 and the detecting transistor M1 included in the target pixel 10 existing in the first partition a1 may both be turned off. When only one detection signal line SL is included, the detection signal line SL is prevented from generating signal interference when different gate lines are turned on.

Fig. 8 is a timing diagram of signal lines in an array substrate included in a display module according to the prior art, which is illustrated by taking the same structure as the timing diagram shown in fig. 7 as an example. As can be seen from comparing fig. 7 and 8, since the source driving circuit 01 of the related art can only supply data signals to the data lines D at a fixed voltage slew rate, there is a difference between the magnitude of the data signal output from the far end of each data line D to the pixel to which it is connected and the magnitude of the data signal output from the near end to the pixel to which it is connected. With reference to fig. 7, with the structure and driving method provided by the embodiment of the present disclosure, the data signals output by each data line D to the respective pixels connected thereto may all be the same. Thereby improving the display effect of the display device.

In the two-frame image scanning shown in fig. 7 and 8, the polarity of the data signal written on the data line D is just opposite, for example, the data signal written on the n-th frame is positive (+) and the data signal written on the n + 1-th frame is negative (-). Also, fig. 7 and 8 also show signal timings of the common voltage Vcom.

Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 9, the display device may include: a gate driving circuit 02, and a display module as shown in any one of fig. 1, 4 and 5. Referring to fig. 9, the display module includes a source driving circuit 01 and an array substrate 00, and a gate driving circuit 02 may be respectively connected to a plurality of gate lines G (e.g., G1 to Gn shown in fig. 9) in the array substrate 00 and configured to provide gate driving signals to the plurality of gate lines G. The source driving circuit 01 may be connected to a plurality of data lines D (e.g., D1 to Dm shown in fig. 9) in the array substrate 00, respectively, and used to supply data signals to the plurality of data lines D.

Alternatively, the gate driving circuit 02 may be disposed on the array substrate 00, or the gate driving circuit 02 may be disposed independently of the array substrate 00. The display device may be: any product or component with a display function, such as an LCD display device, an OLED display device, an AMOLED display device, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the display module and the circuits included in the display module described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The above description is intended to be exemplary only and not to limit the disclosed embodiments, and any modifications, equivalents, improvements, etc. made within the spirit and principles of the disclosed embodiments should be included within the scope of the disclosed embodiments.

Claims

1. The utility model provides a display module assembly, its characterized in that, display module assembly includes: the array substrate and the source electrode driving circuit; the array substrate includes: the pixel array structure comprises at least one detection signal line, a plurality of pixels arranged in an array, a plurality of grid lines connected with a plurality of rows of the pixels in a one-to-one corresponding mode, and a plurality of data lines connected with a plurality of columns of the pixels in a one-to-one corresponding mode, wherein a source electrode driving circuit is respectively connected with the plurality of data lines and the at least one detection signal line;

2. The display module of claim 1, wherein each of the target pixels comprises: a drive circuit, a detection circuit, and a light emitting element;

3. The display module of claim 2, wherein the driving circuit comprises: a drive transistor, the detection circuit comprising: a detection transistor;

4. The display module according to any one of claims 1 to 3, wherein there is one target pixel in each of the partitions, and the target pixels in the respective partitions are located in the same column.

5. The display module according to claim 4, wherein each of the partitions comprises the same number of pixel rows, and the target pixels in each of the partitions are arranged at equal intervals.

6. The display module of claim 5, wherein the target pixel in each of the partitions is in a first column.

7. The display module according to any one of claims 1 to 3, wherein a plurality of target pixels located in the same row exist in each of the partitions; the source driving circuit includes: a plurality of driving sub-circuits, the array substrate comprising: a plurality of the detection signal lines;

8. The display module according to claim 7, wherein two target pixels located in the same row exist in each of the partitions, and one of the two target pixels located in the same row is located in a first column, and the other one of the two target pixels is located in a last column; the source driving circuit includes: a first driving sub-circuit, a second driving sub-circuit and a third driving sub-circuit arranged along a scanning direction of the gate line; the array substrate includes: two of the detection signal lines;

9. A driving method of an array substrate in a display module, applied to a source driving circuit in the display module according to any one of claims 1 to 8, the method comprising:

providing data signals to a plurality of data lines;

10. A display device, characterized in that the display device comprises: a gate driving circuit, and a display module according to any one of claims 1 to 8;