CN111273191B - RVDT/LVDT signal processing circuit and detection method - Google Patents
RVDT/LVDT signal processing circuit and detection method Download PDFInfo
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- CN111273191B CN111273191B CN202010139680.0A CN202010139680A CN111273191B CN 111273191 B CN111273191 B CN 111273191B CN 202010139680 A CN202010139680 A CN 202010139680A CN 111273191 B CN111273191 B CN 111273191B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention discloses an RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test and a detection method, which consists of an RVDT/LVDT signal simulation and switching circuit, an RVDT/LVDT demodulation circuit, a rectification filtering summation circuit, an amplifier, an A/D sampling and switching control circuit and an A/D sampling circuit, can automatically detect the disconnection and short circuit conditions of an RVDT/LVDT lead terminal in real time on line and report a single chip microcomputer, and has the characteristics of detection real-time property, high reliability and strong practicability; and meanwhile, a BIT non-online self-testing circuit (namely an RVDT/LVDT signal simulation and switching circuit) is arranged to carry out non-online self-testing on the working state of the RVDT/LVDT signal processing circuit and report the detection result to the single chip microcomputer, so that the method has the characteristics of detection safety and reliability. The online automatic detection and BIT self-test RVDT/LVDT signal processing circuit is mainly used for the occasions with low operation frequency of the RVDT/LVDT sensor.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to an RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test and a detection method.
Background
The differential transformer type displacement sensor includes an RVDT (differential transformer type angular displacement sensor) and an LVDT (differential transformer type linear displacement sensor). RVDT and LVDT are in principle identical.
The RVDT/LVDT sensor is widely applied to the fields of various industrial controls and military controls, has the characteristics of high reliability and high safety, particularly has the characteristics of high sealing property, no contact, high sensitivity and high repeatability, and is suitable for being applied to places with severe environment, high reliability and high control precision requirements. However, because there are many lead wires (3-wire, 4-wire and 5-wire lead wire types) in the RVDT/LVDT sensor, especially in the application of multi-path RVDT/LVDT, there are more lead terminals, and the problems of poor contact, wire breakage and short circuit of the lead terminals are more likely to occur. Therefore, the application of monitoring the RVDT/LVDT sensor signals and monitoring and alarming the working state of the signal processing circuit is more and more demanding. The monitoring of the working state of the circuit is generally realized by adopting a BIT self-test technology, namely, a test circuit and a test singlechip are additionally arranged. The self-test type signal processing circuit mainly comprises a non-online type and an online type, when the non-online type test circuit tests the working state of the signal processing circuit, a change-over switch is required to be added to cut off the signal input of a sensor of the signal processing circuit, and meanwhile, a self-test analog signal is input, if the output signal of the signal processing circuit is consistent with an expected signal, the signal processing circuit is determined to work normally, but the increase of the change-over switch can not avoid the increase of circuit links, so that the working reliability of the signal processing circuit is reduced, and the self-test type signal processing circuit has limitation; in the on-line test, an input self-test voltage signal needs to be additionally added at the working signal input end of the signal processing circuit, and if the output signal of the signal processing circuit is consistent with an expected signal, the signal processing circuit is determined to work normally. The test directly changes the working signal during the test, which easily causes the working state deviation of the signal processing circuit to influence the normal work of the signal processing circuit; both self-test control circuits have limitations, and corresponding self-test methods need to be adopted according to specific conditions.
Therefore, in order to find out the problems of poor contact, disconnection, short circuit and the like of the lead of the RVDT/LVDT terminal in time and to monitor the working state of the RVDT/LVDT signal processing circuit, how to provide the RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test and the detection method thereof are problems that need to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the invention provides an RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test and a detection method, which consists of an RVDT/LVDT signal simulation and switching circuit, an RVDT/LVDT demodulation circuit, a rectification filtering summing circuit, an amplifier, an A/D sampling and switching control circuit and an A/D sampling circuit, can automatically detect the disconnection and short circuit conditions of an RVDT/LVDT lead terminal in real time on line and report to a single chip microcomputer, and has the characteristics of detection instantaneity, high reliability and strong practicability; and meanwhile, a BIT non-online self-testing circuit (namely an RVDT/LVDT signal simulation and switching circuit) is arranged to carry out non-online self-testing on the working state of the RVDT/LVDT signal processing circuit and report the detection result to the single chip microcomputer, so that the method has the characteristics of detection safety and reliability. The online automatic detection and BIT self-test RVDT/LVDT signal processing circuit is mainly used for the occasions with low operation frequency of the RVDT/LVDT sensor.
In order to achieve the above purpose, the invention provides the following technical scheme:
an RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test, comprising: the system comprises an RVDT/LVDT signal simulation and switching circuit, an RVDT/LVDT demodulation circuit, a rectifying, filtering and summing circuit, an amplifier, an A/D sampling circuit and a main controller; wherein, the first lead, the second lead, the third lead, the fourth lead and the fifth lead of the RVDT/LVDT sensor are used as the input of the circuit;
the first lead is respectively connected with a third resistor of the RVDT/LVDT signal simulation and switching circuit, a fourteenth resistor of the rectification filtering summation circuit and the RVDT/LVDT demodulation chip; the second lead is respectively connected with a fourth resistor of the RVDT/LVDT signal simulation and switching circuit and the RVDT/LVDT demodulation circuit; the third lead is connected with a second normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit; the fourth lead is connected with a ground wire; the fifth lead is connected with a first normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit;
the RVDT/LVDT signal simulation and switching circuit is electrically connected with the RVDT/LVDT demodulation circuit, the rectifying, filtering and summing circuit and the main controller respectively;
the RVDT/LVDT demodulation circuit is output through the amplifier;
the A/D sampling circuit is electrically connected with the rectifying, filtering and summing circuit and the main controller respectively, and sampling ends are connected to two sides of the amplifier respectively.
Preferably, in the RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test described above, further comprising: an isolation circuit; the A/D sampling circuit and the RVDT/LVDT signal simulation and switching circuit are connected with the main controller through the isolation circuit.
Preferably, in the RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test described above, the RVDT/LVDT signal simulating and switching circuit includes a second resistor, a third resistor, a fourth resistor, a second capacitor, a first diode, a first relay, a relay driving circuit, and a first digital potentiometer; one end of the relay driving circuit is connected with the first diode and the first relay respectively, and the other end of the relay driving circuit is connected with the isolation circuit; the first diode is connected with the first relay in parallel, and the other end of the parallel connection is connected with a power supply + 15V; one end of the third resistor is connected with the first digital potentiometer and a second normally open point of the first relay, and the other end of the third resistor is connected with the first lead; one end of the fourth resistor is connected with the first digital potentiometer and the first normally open point of the first relay, and the other end of the fourth resistor is connected with the second lead.
Preferably, in the RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test, the RVDT/LVDT demodulation circuit includes a fifth resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an RVDT/LVDT demodulation chip; the two ends of the fifth resistor, the fifth capacitor, the sixth capacitor, the ninth capacitor and the tenth capacitor are connected to the RVDT/LVDT demodulation chip; the eighth resistor is connected with the ninth resistor in series, and the other end of the eighth resistor is connected to a-15V power supply; the other end of the ninth resistor is connected to the RVDT/LVDT demodulation chip; the tenth resistor is connected with the eleventh resistor in series, and the other end of the tenth resistor is connected with the ninth capacitor and the RVDT/LVDT demodulation chip respectively; the other end of the eleventh resistor is respectively connected with the RVDT/LVDT demodulation chip, the amplifier and the A/D sampling circuit; the third capacitor is connected with the fourth capacitor in parallel, the negative electrode end of the third capacitor is respectively connected with the RVDT/LVDT demodulation chip and the-15V power supply, and the positive electrode end of the third capacitor is connected with the SGND1 ground wire; and the positive end of the eighth capacitor is respectively connected with the RVDT/LVDT demodulation chip, the +15V power supply, the A/D sampling circuit and the amplifier, and the negative end of the eighth capacitor is respectively connected with the ground wire and the RVDT/LVDT demodulation chip.
Preferably, in the RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test, the amplifier includes a seventh resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, and a fourth operational amplifier; one end of the seventh resistor is connected with a +15V power supply, and the other end of the seventh resistor is connected with one end of the fifteenth resistor; the other end of the fifteenth resistor is connected with the sixteenth resistor in series; the other end of the sixteenth resistor is connected with a-15V power supply; the center end of the fifteenth resistor is connected with the seventeenth resistor; the center end of the nineteenth resistor is in short circuit with one end, the other end of the nineteenth resistor is connected with the eighteenth resistor in series to form a whole, and is connected with the fourth operational amplifier and the fourteenth capacitor in parallel, one end of a parallel point is connected with the seventeenth resistor and the twenty-first resistor, and the other end of the parallel point is connected with the twentieth resistor; the other end of the twentieth resistor is connected with the fifteenth capacitor, the A/D sampling circuit and the output end respectively; one end of a sixteenth capacitor is connected with the +15V power supply and the fourth operational amplifier respectively, and the other end of the sixteenth capacitor is connected with the ground wire; one end of a seventeenth capacitor is connected with a-15V power supply and the fourth operational amplifier respectively, and the other end of the seventeenth capacitor is connected with the ground wire.
Preferably, in the RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test described above, the fifteenth resistor and the nineteenth resistor are adjustable potentiometers.
Preferably, in the RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test, the rectifying, filtering and summing circuit includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-third resistor, a thirty-second resistor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor, a twenty-eighth capacitor, a fifth operational amplifier, a sixth electronic switch, a second diode, a third diode, and a fourth diode; the other ends of the twelfth resistor, the thirteenth resistor and the fourteenth resistor are connected with the fifth operational amplifier; the fifth operational amplifier is respectively connected with one end of a twenty-third resistor, one end of a twenty-fourth resistor and one end of a twenty-fifth resistor, and the other ends of the twenty-third resistor, the twenty-fourth resistor and the twenty-fifth resistor are respectively connected with a sixth electronic switch; the twenty-first capacitor is connected with the twenty-second capacitor in parallel, the negative end of the twenty-second capacitor is respectively connected with the sixth electronic switch and the-15V power supply, and the positive end of the twenty-second capacitor is connected with the ground wire; a twenty-third capacitor is connected with a twenty-fourth capacitor in parallel, the positive end of the twenty-fourth capacitor is respectively connected with a sixth electronic switch and a +15V power supply, and the negative end of the twenty-fourth capacitor is connected with a ground wire; the sixth electronic switch is respectively connected with the cathode ends of the second diode, the third diode and the fourth diode, the anode of the second diode is connected with a twenty-sixth resistor, the anode of the third diode is connected with a twenty-eighth resistor, and the anode of the fourth diode is connected with a thirty-sixth resistor; two ends of a twenty-seventh resistor are connected with the fifth operational amplifier and the twenty-fifth capacitor in parallel, and one end of a parallel point is also connected with the other ends of a twenty-sixth resistor, a twenty-eighth resistor and a thirty-fifth resistor respectively; the other end of the parallel point is connected with a thirty-first resistor; the other end of the thirty-first resistor is connected with the thirty-second resistor, the twenty-eighth capacitor and the A/D sampling circuit respectively; the other ends of the twenty-eighth capacitor and the thirty-second resistor are connected with the ground wire; one end of a twenty-sixth capacitor is respectively connected with the +15V power supply and the fifth operational amplifier, and the other end of the twenty-sixth capacitor is connected with the ground wire; one end of a twenty-seventh capacitor is connected with a-15V power supply and the fifth operational amplifier respectively, and the other end of the twenty-seventh capacitor is connected with the ground wire.
A real-time on-line automatic detection method for wire break and short circuit of RVDT/LVDT lead terminal includes VA value, VB value, VEXC value and sum value (VA + VB) corresponding to voltage values of RVDT/LVDT lead terminal, VA minimum value is VAminVA maximum is VAmaxWith VB minimum value VBminVB maximum value is VBmax(ii) a The judging steps are as follows:
1) the sum (VA + VB) is normal, namely when the (VA + VB)/(VA + VB) is rated to be 0.8-1.2;
a) if VA is greater than or equal to VAminAnd VB is not less than VBminJudging no disconnection;
b) if VA < VAminJudging the disconnection of the VA lead terminal;
c) if VA is greater than or equal to VAmin，VB＜VBminJudging that the VB lead terminal is broken;
2) the sum (VA + VB)/(VA + VB) is rated less than 0.8;
a) if VA < VAminAnd VB is not less than VBminJudging the disconnection of the VA lead terminal;
b) if VA is greater than or equal to VAminAnd VB < VBminJudging that the VB lead terminal is broken;
c) if VA is greater than or equal to VAminAnd VB is not less than VBminJudging that no lead terminal is broken;
d) if VA < VAminAnd VB < VBminJudging according to the following conditions:
if the VEXC value is normal, judging that the secondary VA and VB lead terminals are disconnected or the EXC1 and the EXC1a primary lead terminal are disconnected;
if the VEXC value is abnormal, judging that the RVDT demodulation chip AD598 stimulates the power supply to have a fault, and no lead terminal is disconnected;
3) the sum (VA + VB)/(VA + VB) is rated to be more than 1.2;
a) if VA < VAminAnd VB is not less than VBminJudging that the VA lead terminal is short-circuited with the grounding terminal;
b) if VA is greater than or equal to VAminAnd VB < VBminJudging that the VB lead terminal is short-circuited with the grounding terminal;
c) if VA is greater than or equal to VAminAnd VB is not less than VBminAnd judging that no lead terminal is broken.
Through the technical scheme, the RVDT signal processing circuit with the online automatic detection and BIT self-test functions and the detection method can be known, the conditions of poor contact, disconnection, short circuit and the like of the RVDT terminal lead can be automatically detected online by arranging the RVDT signal simulation and switching circuit, the RVDT demodulation circuit, the rectification filtering summing circuit, the amplifier, the A/D sampling circuit and the A/D sampling and switching control circuit (namely a single chip microcomputer), the working state of the RVDT signal processing circuit can be monitored and reported to the single chip microcomputer, and the RVDT signal processing circuit has the characteristics of detection comprehensiveness, high reliability and strong practicability. The invention is also applicable to LVDT signal processing circuits.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic block diagram of an LVDT sensor operation;
FIG. 2 is a schematic block diagram of the operation of the RVDT sensor;
FIG. 3 is a block diagram of the working principle of AD 598;
FIG. 4 is a schematic block diagram of RVDT signal simulation;
FIG. 5 is a schematic block diagram of a preferred embodiment of the present invention;
FIG. 6 is a circuit diagram of the preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses an RVDT/LVDT signal processing circuit with online automatic detection and BIT self-test and a detection method, which can automatically detect the conditions of poor contact, disconnection, short circuit and the like of RVDT terminal leads on line by arranging an RVDT signal simulation and switching circuit, an RVDT demodulation circuit, a rectification filtering summation circuit, an amplifier, an A/D sampling circuit and an A/D sampling and switching control circuit (namely a singlechip), can monitor the working state of the RVDT signal processing circuit and report the working state to the singlechip, and has the characteristics of detection comprehensiveness, high reliability and strong practicability. The invention is also applicable to LVDT signal processing circuits.
Referring to fig. 5 and 6, an RVDT signal processing circuit with on-line automatic detection and BIT self-test has five lines at the input end, namely, a first lead EXC1, a second lead EXC1a, a third lead VA1, a fourth lead SGND1 and a fifth lead VB1, and the Output end (Output) outputs the signal after RVDT signal demodulation and amplification processing. The signal processing circuit comprises an input end (five lines), an Output end (Output), a ground wire S1GND, first to fourth diodes V1 to V4, second resistors R2 to thirty-second resistors R32, second capacitors C2 to thirty-second capacitors C32, a digital potentiometer N1, a relay drive circuit (drive circuit for relay, the same below), an RVDT demodulation chip N2, a voltage stabilizer N3, an amplifier (amplifier, the same below) N4, a rectification and filtering circuit (rectification and filtering circuit, the same below) (operational amplifier N5, an electronic switch N6), an A/D sampling circuit (A/D sampling circuit, the same below) N7, an A/D sampling and switching control circuit (namely) (A/D sampling circuit, the same below), an isolation circuit (isolation circuit, the same below) and the like.
Wherein, the end of the first lead EXC1 is respectively connected with a third resistor R3 of an RVDT signal simulating and switching circuit (RVDT signal simulating and switching circuit, the same below), a fourteenth resistor R14 of a rectifying, filtering and summing circuit and an RVDT demodulation circuit (the same below);
the end of the second lead EXC1a is respectively connected with a fourth resistor R4 of the RVDT signal simulation and switching circuit and the RVDT demodulation circuit;
the end of a third lead VA1 is connected with a second normally closed contact K1C of a first relay K1 of the RVDT signal simulation and switching circuit;
the fourth lead terminal is connected with the SGND1 ground wire;
a fifth lead VB1 is connected at its end to the first normally closed contact K1B of the first relay K1 of the RVDT signal simulation and switching circuit.
An eleventh resistor R11 of the RVDT demodulation circuit is respectively connected with a twenty-first resistor R21 of the amplifier and the A/D sampling circuit; the twentieth resistor R20 of the amplifier is respectively connected with the fifteenth capacitor C15, the A/D sampling circuit and the output end UO, and the other end of the fifteenth capacitor C15 is connected with the ground line SGND 1. A twelfth resistor R12 of the rectifying, filtering and summing circuit is respectively connected with the RVDT demodulation chip N2 and a second action point K1C of a first relay K1 of the RVDT signal simulation and switching circuit; a thirteenth resistor R13 of the rectifying, filtering and summing circuit is respectively connected with the RVDT demodulation chip N2 and the first action point K1B of the first relay K1 of the RVDT signal simulation and switching circuit; a fourteenth resistor R14 of the rectifying, filtering and summing circuit is respectively connected with the RVDT demodulation chip N2 and a third resistor R3 of the RVDT signal simulation and switching circuit; a thirty-first resistor R31 of the rectifying, filtering and summing circuit is respectively connected with a thirty-second resistor R32, a twenty-eighth capacitor C28 and an A/D sampling circuit, and the other ends of the thirty-second resistor R32 and the twenty-eighth capacitor C28 are respectively connected with an SGND1 ground wire; an isolation circuit is arranged between the A/D sampling and switching control circuit (namely a singlechip) and the RVDT signal simulation and switching circuit and the control ends of the relay drive circuit, the A/D sampling circuit, the rectification filtering summation circuit and the like.
The RVDT signal analog and switching circuit comprises a second resistor R2-a fourth resistor R4, a second capacitor C2, a first diode V1, a first relay K1, a relay driving circuit and a first digital potentiometer N1. One end of the relay driving circuit is connected with the first diode V1 and the first relay K1, and the other end of the relay driving circuit is connected with the isolation circuit; the first diode V1 is connected in parallel with the first relay K1, and the other end of the parallel connection is connected with a power supply + 15V; one end of a third resistor R3 is connected with a first digital potentiometer N1 and a second normally open point K1C of a first relay K1, and the other end is connected with an input end EXC1, a fourteenth resistor R14 of a rectifying, filtering and summing circuit and an RVDT demodulation chip N2; one end of the fourth resistor R4 is connected to the first digital potentiometer N1 and the first normally open point K1B of the first relay K1, and the other end is connected to the input end EXC1a and the RVDT demodulation chip N2.
The RVDT demodulation circuit is designed according to a typical application circuit of the RVDT demodulation chip AD598 and comprises a fifth resistor R5, an eighth resistor R8-an eleventh resistor R11, a third capacitor C3-a tenth capacitor C10, an RVDT demodulation chip N2 and the like. The two ends of a fifth resistor R5, a fifth capacitor C5, a sixth capacitor C6, a ninth capacitor C9 and a tenth capacitor C10 are connected to an RVDT demodulation chip N2; the eighth resistor R8 is connected with the ninth resistor R9 in series, and the other end of the eighth resistor R8 is connected with a-15V power supply; the other end of the ninth resistor R9 is connected to an RVDT demodulation chip N2; the tenth resistor R10 is connected in series with the eleventh resistor R11, and the other end of the tenth resistor R10 is respectively connected with the ninth capacitor C9 and the RVDT demodulation chip N2; the other end of the eleventh resistor R11 is respectively connected with the RVDT demodulation chip N2, the amplifier N4, the twenty-first resistor R21 and the A/D sampling circuit; a third capacitor C3 is connected with a fourth capacitor C4 in parallel, the negative electrode end of the third capacitor C3 is respectively connected with the RVDT demodulation chip N2 and the-15V power supply, and the positive electrode end of the third capacitor C3 is connected with the SGND1 ground wire; the seventh capacitor C7 is connected in parallel with the eighth capacitor C8, the positive terminal of the eighth capacitor C8 is respectively connected with the RVDT demodulation chip N2, the +15V power supply, the sixth resistor R6 of the A/D sampling circuit and the seventh resistor R7 of the amplifier, and the negative terminal of the eighth capacitor C8 is respectively connected with the SGND1 ground wire and the RVDT demodulation chip N2.
The rectifying, filtering and summing circuit comprises a twelfth resistor R12-a fourteenth resistor R14, a twenty-third resistor R23-a thirty-second resistor R32, a twenty-first capacitor C21-a twenty-eighth capacitor C28, a fifth operational amplifier N5, a sixth electronic switch N6, a second diode V2-a fourth diode V4 and the like. The other ends of the twelfth resistor R12 to the fourteenth resistor R14 are connected with the fifth operational amplifier N5; the fifth operational amplifier N5 is respectively connected with one end of a twenty-third resistor R23 to one end of a twenty-fifth resistor R25, and the other end of the twenty-third resistor R23 to the other end of the twenty-fifth resistor R25 are respectively connected with a sixth electronic switch N6; a twenty-first capacitor C21 is connected with a twenty-second capacitor C22 in parallel, the negative electrode end of the twenty-second capacitor C22 is respectively connected with a sixth electronic switch N6 and a 15V power supply, and the positive electrode end of the twenty-second capacitor C22 is connected with an SGND1 ground wire; a twenty-third capacitor C23 is connected in parallel with a twenty-fourth capacitor C24, the positive terminal of the twenty-fourth capacitor C24 is respectively connected with a sixth electronic switch N6, +15V power supply, and the negative terminal of the twenty-fourth capacitor C24 is connected with an SGND1 ground wire; a sixth electronic switch N6 is connected to the negative terminals of the second to fourth diodes V2 to V4, respectively, the positive terminal of the second diode V2 is connected to a twenty-sixth resistor R26, the positive terminal of the third diode V3 is connected to a twenty-eighth resistor R28, and the positive terminal of the fourth diode V4 is connected to a thirty-fifth resistor R30; two ends of a twenty-seventh resistor R27 are connected with a fifth operational amplifier N5 and a twenty-fifth capacitor C25 in parallel, and one end of a parallel point is also connected with the other ends of a twenty-sixth resistor R26, a twenty-eighth resistor R28 and a thirty-fifth resistor R30 respectively; the other end of the parallel point is connected with a thirty-one resistor R31; the other end of the thirty-first resistor R31 is respectively connected with a thirty-second resistor R32, a twenty-eighth capacitor C28 and an A/D sampling circuit; the other ends of the twenty-eighth capacitor C28 and the thirty-second resistor R32 are connected with the SGND1 ground wire; one end of a twenty-sixth capacitor C26 is respectively connected with a +15V power supply and a fifth operational amplifier N5, and the other end of the twenty-sixth capacitor C26 is connected with an SGND1 ground wire; one end of a twenty-seventh capacitor C27 is connected with a-15V power supply and a fifth operational amplifier N5 respectively, and the other end of the twenty-seventh capacitor C27 is connected with an SGND1 ground wire.
The amplifier comprises a seventh resistor R7, a fifteenth resistor R15-a twenty-second resistor R22 (the fifteenth resistor R15 and the nineteenth resistor R19 are adjustable potentiometers), a fourteenth capacitor C14-a seventeenth capacitor C17 and a fourth operational amplifier N4. One end of the seventh resistor R7 is connected with a +15V power supply, and the other end of the seventh resistor R7 is connected with one end of the fifteenth potentiometer R15; the other end of the fifteenth potentiometer R15 is connected in series with a sixteenth resistor R16; the other end of the sixteenth resistor R16 is connected with a-15V power supply; the center end of the fifteenth resistor R15 is connected with a seventeenth resistor R17; the central end of a nineteenth potentiometer R19 is in short circuit with one end, the other end of the nineteenth potentiometer R19 is connected with an eighteenth resistor R18 in series to form a whole, two ends of the whole are connected with a fourth operational amplifier N4 and a fourteenth capacitor C14 in parallel, one end of a parallel point is also connected with a seventeenth resistor R17 and a twenty-first resistor R21, and the other end of the parallel point is connected with a twentieth resistor R20; the other end of the twentieth resistor R20 is connected with the fifteenth capacitor C15, the A/D sampling circuit and the output end UO respectively; one end of a sixteenth capacitor C16 is respectively connected with a +15V power supply and a fourth operational amplifier N4, and the other end of the sixteenth capacitor C16 is connected with an SGND1 ground wire; one end of a seventeenth capacitor C17 is connected with a-15V power supply and the fourth operational amplifier N4, and the other end of the seventeenth capacitor C17 is connected with the SGND1 ground wire.
The A/D sampling circuit consists of a sampling integrated circuit N7, a sixth resistor R6, an eleventh capacitor C11-a thirteenth capacitor C13, an eighteenth capacitor C18-a twentieth capacitor C20, a nineteenth capacitor C29-a thirty-second capacitor C32 and a voltage stabilizer N3, and is designed according to typical application circuits of the A/D sampling integrated circuit and the voltage stabilizing circuit.
Principle of operation
1. RVDT/LVDT sensor working principle
The RVDT sensor is shown in fig. 2, and the operation principle is similar to that of a differential transformer, and mainly comprises an armature core, a primary coil and two secondary coils, wherein the two secondary coils have the same number of turns and are wound in reverse series. The armature core rotates with the RVDT in the middle of the primary and secondary coils to do non-contact telescopic motion. After the excitation signal is applied to two ends of the RVDT primary coil, induced electromotive forces VA and VB with the same frequency are induced to be generated in two parts of the secondary coil, and when the difference value (VA-VB) of the two induced electromotive forces reaches the minimum value, the angle of the armature core is zero. As the iron core continues to rotate, the induced electromotive forces of the two secondary coils are increased and decreased, the farther the angle of the iron core is away from the central zero position, the larger the difference (VA-VB) between the induced electromotive forces, and the difference (VA-VB) is proportional to the rotation angle of the iron core, so that the angle detection is realized. According to the operation principle of the RVDT sensor, when the RVDT works normally, the sum (VA + VB) of the electromotive forces induced by the two secondary coils is always constant, and is independent of the angular position of the armature core.
LVDT sensors as shown in fig. 1, operate on a similar principle to RVDT sensors except that the rotation is converted to linear motion.
2. Working principle of real-time online automatic detection circuit for disconnection and short circuit of RVDT/LVDT lead terminal
The currently common RVDT/LVDT signal processing circuit uses AD company's dedicated processing chip AD598, as shown in fig. 3. AD598 has the following characteristics: the internal part contains a crystal oscillator and a reference voltage, and the conversion from mechanical change of position to direct current voltage can be realized by only adding a very small amount of passive elements, and the output of the direct current voltage conversion device is proportional to the angle or displacement change of the RVDT/LVDT. AD598 is provided with an excitation signal for driving RVDT/LVDT.
Still using RVDT as an example for explanation. The real-time online automatic detection function of RVDT lead terminal disconnection and short circuit is mainly completed by a rectification filter summation circuit and an A/D sampling circuit. As shown in fig. 5. According to the RVDT sensor operating principle, the sum (VA + VB) of the induced electromotive forces of the two secondary coils is always constant in normal operation and is independent of the angle position of the armature core. The RVDT lead terminal is disconnected or the excitation signal is reduced, the sum value (VA + VB) is reduced, and if the difference value of the (VA + VB) and the (VA + VB) rating exceeds the threshold value, the fault is judged.
In the circuit, a sum value (VA + VB), a VA value, a VB value and a VEXC value (excitation voltage) can be obtained by only respectively controlling the on-off of three switches of the electronic switch N6, and the four values are direct-current voltage values after rectification and filtration. And setting the VA minimum value as VAmin, the VA maximum value as VAmax, the VB minimum value as VBmin and the VB maximum value as VBmax. In order to prevent false detection alarm caused by signal interference, etc., a threshold value of the sum value (VA + VB) is set, and the threshold value is set at 20% of the rated value (VA + VB).
The judging steps are as follows:
1) the sum (VA + VB) is normal, namely when the (VA + VB)/(VA + VB) is rated to be 0.8-1.2
a) If VA is more than or equal to VAmin and VB is more than or equal to VBmin, judging that no line is broken
Note: when a lead at a VA zero line end (GND end) or a lead at a VB zero line end is disconnected, VA or VB voltage becomes a floating signal, the rectifying and filtering summing circuit cannot completely eliminate the floating signal, and when the frequency and amplitude of the VA or VB signal are relatively high in extreme conditions, the output of the rectifying and filtering summing circuit is close to the lower limit of a rated value of a sum value (VA + VB), and misjudgment is possibly caused. Therefore, the fault detection coverage rate can only reach 98-99 percent;
b) if VA is less than VAmin, the disconnection of the VA lead terminal is judged
Since it is possible that when VA is 0V and VB is VBmax, (0+ VBmax)/(VA + VB) is still rated between 0.8-1, the sum normal condition is satisfied. Therefore, this judgment needs to be added;
c) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal is judged to be broken
The reason is the same as the b;
2) when the (VA + VB)/(VA + VB) rating is less than 0.8
a) If VA is less than VAmin and VB is more than or equal to VBmin, the disconnection of the VA lead terminal is judged;
b) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal is judged to be broken;
c) if VA is more than or equal to VAmin and VB is more than or equal to VBmin, the fact that the lead-free terminal is disconnected is judged, and the fact that the sum value is lower than 80% of the rated value is caused by other reasons;
d) if VA is less than VAmin and VB is less than VBmin, judging according to the following conditions:
if the VEXC value is normal, judging that the secondary VA and VB lead terminals are disconnected or the EXC1 and the EXC1a primary lead terminal are disconnected;
if the VEXC value is abnormal, the RVDT demodulation chip AD598 is judged to excite the power supply to have a fault, and no lead terminal is disconnected;
3) when (VA + VB)/(VA + VB) rating > 1.2
a) If VA is less than VAmin and VB is more than or equal to VBmin, judging that the VA lead terminal and the ground terminal are in short circuit;
b) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal and the grounding terminal are judged to be in short circuit;
c) if VA is more than or equal to VAmin and VB is more than or equal to VBmin, the fact that the lead-free terminal is disconnected is judged, and the fact that the sum value is higher than 120% of the rated value is caused by other reasons;
3. working principle of real-time online automatic detection circuit of amplifier
The real-time on-line automatic detection function of the amplifier is mainly completed by an A/D sampling circuit and an A/D sampling control circuit (namely a singlechip). The RVDT/LVDT sensors process displacement or rotation angle signals, and the signal frequency is lower.
The A/D sampling circuit monitors the signals of the input end and the output end of the amplifier on line in real time, and the working state of the amplifier circuit can be obtained by calculation. Because the signal frequency is lower, the working state of the amplifier circuit can be accurately known only by monitoring the working signal of the amplifier fast enough (considering a certain time delay) during the online real-time self-test.
4. BIT non-online self-testing working principle of RVDT/LVDT signal processing circuit
The BIT offline self-test function is mainly completed by the RVDT signal simulation and switching circuit. Because the RVDT lead terminals are more, the simulation analog signals are not easy to be injected into the RVDT demodulation chip AD598 in real time and on line without influencing the normal work of the demodulation circuit, and therefore a BIT non-on-line self-test mode is adopted. During testing, the RVDT signal is disconnected by a relay and injected into the RVDT simulation analog signal.
The RVDT analog-to-digital signal is realized by a digital potentiometer, and the schematic block diagram is shown in FIG. 3.
In fig. 3, the voltage between the EXC terminal and the EXCa terminal is the excitation ac signal voltage emitted by AD598, and the voltage between the EXC terminal and the EXCa terminal is Vexc, Vexca is Vexca, and the voltage difference between the two terminals is Ve (Vexc-Vexca). VA is VAa and VB is VBb.
a) The amplitude of the excitation alternating current signal voltage Ve is a fixed value (influence of temperature drift and the like is not considered), and the fixed value is set to be | Ve |, namely | Vexc-Vexca | is a fixed value;
b) the voltage difference (Vexc-Vexca) between the EXC end and the EXCa end is divided by R1-R3 to obtain the voltage difference (VAa-VBb) between the VA end and the VB end, which comprises the following steps: VAa-VBb ═ (Vexc-Vexca) (R2/(R1+ R2+ R3)), so there are: i VAa-VBb i | Vexc-Vexca | R2/(R1+ R2+ R3), so i VAa-VBb | is also a fixed value;
c) if VAa is more than 0V, VBb is less than 0V; if VAa is less than 0V, VBb is more than 0V; comprises the following steps:
|VAa-VBb|＝|VAa-0+0-VBb|＝|VBb-0+0-VAa|＝|VAa|+|VBb|
therefore, | VAa | + | VBb | is also a fixed value;
i.e. | VAa | + | VBb | is the sum of VA and VB terminal voltages after rectification and filtering respectively, and is a fixed value. Therefore, signals at terminals VA and VB extracted from two ends of the digital potentiometer can simulate signals of the RVDT. The specific values of VAa, VBb are assigned by digital potentiometers.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. An RVDT/LVDT signal processing circuit with on-line automatic detection and BIT self-test, comprising: the system comprises an RVDT/LVDT signal simulation and switching circuit, an RVDT/LVDT demodulation circuit, a rectifying, filtering and summing circuit, an amplifier, an A/D sampling circuit and a main controller; wherein, the first lead, the second lead, the third lead, the fourth lead and the fifth lead of the RVDT/LVDT sensor are used as the input of the circuit; the first lead is respectively connected with the RVDT/LVDT signal analog and switching circuit, the rectifying, filtering and summing circuit and the RVDT/LVDT demodulation chip; the second lead is respectively connected with the RVDT/LVDT signal simulation and switching circuit and the RVDT/LVDT demodulation circuit; the third lead is connected with a second normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit; the fourth lead is connected with a ground wire; the fifth lead is connected with a first normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit; the RVDT/LVDT signal simulation and switching circuit is electrically connected with the RVDT/LVDT demodulation circuit, the rectifying, filtering and summing circuit and the main controller respectively; the RVDT/LVDT demodulation circuit is output through the amplifier; the A/D sampling circuit is electrically connected with the rectifying, filtering and summing circuit and the main controller respectively, and sampling ends are connected to two sides of the amplifier respectively.
2. The RVDT/LVDT signal processing circuit with automatic online detection and BIT self-test of claim 1, further comprising: an isolation circuit; the A/D sampling circuit, the RVDT/LVDT signal simulation and switching circuit are connected with the main controller through the isolation circuit.
3. The RVDT/LVDT signal processing circuit with automatic online detection and BIT self-test as claimed in claim 2, wherein the RVDT/LVDT signal analog and switching circuit comprises a second resistor, a third resistor, a fourth resistor, a second capacitor, a first diode, a first relay, a relay driving circuit, a first digital potentiometer; one end of the relay driving circuit is connected with the first diode and the first relay respectively, and the other end of the relay driving circuit is connected with the isolation circuit; the first diode is connected with the first relay in parallel, and the other end of the parallel connection is connected with a power supply + 15V; one end of the third resistor is connected with the first digital potentiometer and a second normally open point of the first relay, and the other end of the third resistor is connected with the first lead; one end of the fourth resistor is connected with the first digital potentiometer and the first normally open point of the first relay, and the other end of the fourth resistor is connected with the second lead.
4. The RVDT/LVDT signal processing circuit with the on-line automatic detection and BIT self-test function as claimed in claim 1, wherein the RVDT/LVDT demodulation circuit comprises a fifth resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an RVDT/LVDT demodulation chip; the two ends of the fifth resistor, the fifth capacitor, the sixth capacitor, the ninth capacitor and the tenth capacitor are connected to the RVDT/LVDT demodulation chip; the eighth resistor is connected with the ninth resistor in series, and the other end of the eighth resistor is connected to a-15V power supply; the other end of the ninth resistor is connected to the RVDT/LVDT demodulation chip; the tenth resistor is connected with the eleventh resistor in series, and the other end of the tenth resistor is connected with the ninth capacitor and the RVDT/LVDT demodulation chip respectively; the other end of the eleventh resistor is connected with the RVDT/LVDT demodulation chip, the amplifier and the A/D sampling circuit respectively; the third capacitor is connected with the fourth capacitor in parallel, the negative electrode end of the third capacitor is respectively connected with the RVDT/LVDT demodulation chip and the-15V power supply, and the positive electrode end of the third capacitor is connected with the SGND1 ground wire; and the positive end of the eighth capacitor is respectively connected with the RVDT/LVDT demodulation chip, the +15V power supply, the A/D sampling circuit and the amplifier, and the negative end of the eighth capacitor is respectively connected with the ground wire and the RVDT/LVDT demodulation chip.
5. The RVDT/LVDT signal processing circuit with automatic online detection and BIT self-test of claim 1, wherein the amplifier comprises a seventh resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor and a fourth operational amplifier; one end of the seventh resistor is connected with a +15V power supply, and the other end of the seventh resistor is connected with one end of the fifteenth resistor; the other end of the fifteenth resistor is connected with the sixteenth resistor in series; the other end of the sixteenth resistor is connected with a-15V power supply; the center end of the fifteenth resistor is connected with the seventeenth resistor; the center end of the nineteenth resistor is in short circuit with one end, the other end of the nineteenth resistor is connected with the eighteenth resistor in series to form a whole, and is connected with the fourth operational amplifier and the fourteenth capacitor in parallel, one end of a parallel point is connected with the seventeenth resistor and the twenty-first resistor, and the other end of the parallel point is connected with the twentieth resistor; the other end of the twentieth resistor is connected with the fifteenth capacitor, the A/D sampling circuit and the output end respectively; one end of a sixteenth capacitor is connected with the +15V power supply and the fourth operational amplifier respectively, and the other end of the sixteenth capacitor is connected with the ground wire; one end of a seventeenth capacitor is connected with a-15V power supply and the fourth operational amplifier respectively, and the other end of the seventeenth capacitor is connected with the ground wire.
6. The RVDT/LVDT signal processing circuit with automatic online detection and BIT self-test as claimed in claim 5, wherein the fifteenth resistor and the nineteenth resistor are adjustable potentiometers.
7. The RVDT/LVDT signal processing circuit with automatic online detection and BIT self-test of claim 1, wherein the rectifying, filtering and summing circuit comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eleventh resistor, a thirty-second resistor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor, a twenty-eighth capacitor, a fifth operational amplifier, a sixth electronic switch, a second diode, a third diode and a fourth diode; one end of the fourteenth resistor is connected with the first lead; the other ends of the twelfth resistor, the thirteenth resistor and the fourteenth resistor are connected with the fifth operational amplifier; the fifth operational amplifier is respectively connected with one end of a twenty-third resistor, one end of a twenty-fourth resistor and one end of a twenty-fifth resistor, and the other ends of the twenty-third resistor, the twenty-fourth resistor and the twenty-fifth resistor are respectively connected with a sixth electronic switch; a twenty-first capacitor is connected with a twenty-second capacitor in parallel, the negative end of the twenty-second capacitor is respectively connected with a sixth electronic switch and a-15V power supply, and the positive end of the twenty-second capacitor is connected with the ground wire; a twenty-third capacitor is connected with a twenty-fourth capacitor in parallel, the positive end of the twenty-fourth capacitor is respectively connected with a sixth electronic switch and a +15V power supply, and the negative end of the twenty-fourth capacitor is connected with a ground wire; the sixth electronic switch is respectively connected with the cathode ends of the second diode, the third diode and the fourth diode, the anode of the second diode is connected with a twenty-sixth resistor, the anode of the third diode is connected with a twenty-eighth resistor, and the anode of the fourth diode is connected with a thirty-sixth resistor; two ends of a twenty-seventh resistor are connected with the fifth operational amplifier and the twenty-fifth capacitor in parallel, and one end of a parallel point is also connected with the other ends of a twenty-sixth resistor, a twenty-eighth resistor and a thirty-fifth resistor respectively; the other end of the parallel point is connected with a thirty-first resistor; the other end of the thirty-first resistor is connected with the thirty-second resistor, the twenty-eighth capacitor and the A/D sampling circuit respectively; the other ends of the twenty-eighth capacitor and the thirty-second resistor are connected with the ground wire; one end of a twenty-sixth capacitor is connected with the +15V power supply and the fifth operational amplifier respectively, and the other end of the twenty-sixth capacitor is connected with the ground wire; one end of a twenty-seventh capacitor is connected with a-15V power supply and the fifth operational amplifier respectively, and the other end of the twenty-seventh capacitor is connected with the ground wire.
8. A real-time online automatic detection method for wire breakage and short circuit of RVDT/LVDT lead terminals is characterized in that a first lead, a second lead, a third lead, a fourth lead and a fifth lead of the RVDT/LVDT sensor are used as input of a circuit; the first lead is respectively connected with the RVDT/LVDT signal analog and switching circuit, the rectifying, filtering and summing circuit and the RVDT/LVDT demodulation chip; the second lead is respectively connected with the RVDT/LVDT signal simulation and switching circuit and the RVDT/LVDT demodulation circuit; the third lead is connected with a second normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit; the fourth lead is connected with a ground wire; the fifth lead is connected with a first normally closed contact of a first relay of the RVDT/LVDT signal simulation and switching circuit; corresponding voltage values of the RVDT/LVDT lead terminal comprise a VA value, a VB value, a VEXC value and a sum value (VA + VB), wherein the VA minimum value is VAmin, the VA maximum value is VAmax, the VB minimum value is VBmin, and the VB maximum value is VBmax; the judging steps are as follows:
1) the sum (VA + VB) is normal, namely when the (VA + VB)/(VA + VB) is rated to be 0.8-1.2;
a) if VA is more than or equal to VAmin and VB is more than or equal to VBmin, judging that no line is broken;
b) if VA is less than VAmin, the disconnection of the VA lead terminal is judged;
c) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal is judged to be disconnected;
2) the sum (VA + VB)/(VA + VB) is rated less than 0.8;
a) if VA is less than VAmin and VB is more than or equal to VBmin, the disconnection of the VA lead terminal is judged;
b) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal is judged to be broken;
c) if VA is more than or equal to VAmin and VB is more than or equal to VBmin, the disconnection of the lead-free terminal is judged;
d) if VA is less than VAmin and VB is less than VBmin, judging according to the following conditions:
if the VEXC value is normal, judging that the secondary VA and VB lead terminals are disconnected or the EXC1 and the EXC1a primary lead terminal are disconnected;
if the VEXC value is abnormal, judging that the RVDT demodulation chip AD598 stimulates the power supply to have a fault, and no lead terminal is disconnected;
3) the sum (VA + VB)/(VA + VB) is rated to be more than 1.2;
a) if VA is less than VAmin and VB is more than or equal to VBmin, judging that the VA lead terminal and the ground terminal are in short circuit;
b) if VA is more than or equal to VAmin and VB is less than VBmin, the VB lead terminal and the grounding terminal are judged to be in short circuit;
c) if VA is larger than or equal to VAmin and VB is larger than or equal to VBmin, the non-lead terminal is judged to be disconnected.
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