CN111273163A - Method and system for testing single event latch-up effect of microprocessor - Google Patents
Method and system for testing single event latch-up effect of microprocessor Download PDFInfo
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Abstract
A test method and a test system for single event latch-up of a microprocessor are provided, the method comprises: s1: supplying power to a microprocessor to be tested, monitoring the power supply current and the running state, irradiating by using high-energy particles and counting the total fluence Q; s2: if Q reaches the preset value, turning to S7, and turning to S3 if Q reaches the preset value; s3: if the current exceeds the specified value, turning to S5, otherwise turning to S4; s4: if the running state is abnormal, turning to S5, and turning to S2; s5: stopping irradiation, restarting the microprocessor to be tested without power failure, if the current is not greater than the specified value and the running state is normal, resuming irradiation to be switched to S2, and if not, switching to S6; s6: increasing the K value by 1, restarting the microprocessor to be tested after power failure, recovering the irradiation to rotate S2 if the current does not exceed the specified value and the running state is normal, and judging whether SEB to rotate S7 occurs or not; s7: and stopping irradiation, and calculating the single-particle latch section C of the microprocessor to be tested as K/Q. The system is implemented according to the method described above. The method can accurately judge the occurrence of the single event latch-up effect of the microprocessor and improve the accuracy of the evaluation of the single event latch-up effect of the microprocessor.
Description
Technical Field
The invention mainly relates to the technical field of detection of microprocessors, in particular to a method and a system for testing single event latch-up effect of a microprocessor.
Background
Modern microprocessors are increasingly widely applied to the fields of aviation and aerospace by virtue of the characteristics of high integration level, complex functions and the like. However, modern microprocessors applied to severe radiation environments such as aviation and aerospace are easily affected by Single-Event Effect (SEE) to cause errors and even failures, which results in immeasurable loss. Therefore, it is important to accurately evaluate the sensitivity of the microprocessor to the single event latchup effect. The main Single Event effect includes Single-Event Latch-up (SEL), Single-Event Upset (SEU), Single-Event Burnout (SEB), and the like.
The traditional method for testing the single event latch-up effect of the microprocessor is a current monitoring method. The single event latch-up effect of the integrated circuit is tested by a method for monitoring the sudden increase of the power supply current in the aerospace industry standard QJ10005-2008 for aerospace semiconductor device heavy ion single event effect test guideline of the people's republic of China. And when the current exceeds a specified value, determining that the single event latch-up effect occurs. The current regulation value is preferably generally 1.5 to 2 times the normal operating current of the integrated circuit.
However, with the progress of microelectronic technology level, modern microprocessors have high integration level, large power consumption and complex power consumption management, and single event latch-up test according to the traditional single event latch-up test method can generate false alarm and false alarm.
First, the internal modules of a modern microprocessor are numerous, and during normal operation, all internal modules are not always turned on, but are selectively turned on by a power management unit inside the microprocessor to save power consumption. When a single event latch-up test of the microprocessor is carried out, an internal power management unit of the microprocessor can mistakenly open an internal module which is not opened during normal work due to a single event upset effect under high-energy particle irradiation, so that the power current of the microprocessor exceeds a specified value, but the single event latch-up effect does not occur at the moment, and the false alarm of the single event latch-up effect occurs.
Secondly, the modern microprocessor has high integration level and high power consumption, when a certain module in the microprocessor is influenced by the single event latch-up effect and the current is increased, the overall supply current of the microprocessor is large, and if the increase of the local current cannot enable the increase of the overall current to exceed a current specified value, the single event latch-up effect is missed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a method and a system for testing the single event latch-up effect of a microprocessor, which can accurately judge the occurrence of the single event latch-up effect of the microprocessor and improve the accuracy of the evaluation of the single event latch-up effect of the microprocessor.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for testing single event latchup effect of a microprocessor comprises the following steps:
step S1: supplying power to a microprocessor to be tested and monitoring power supply current, running a microprocessor test program by the microprocessor to be tested, initializing a single-particle latch counting variable K to be 0, irradiating the microprocessor to be tested by high-energy particles and beginning to count the total fluence;
step S2: if the total fluence of the high-energy particles reaches a preset value, and the preset value meets the requirement of the preset threshold value on the total fluence of the high-energy particles, turning to the step S7, otherwise, turning to the step S3;
step S3: if the supply current is found to exceed the current designated value, go to step S5, otherwise go to step S4;
step S4: if the running state of the microprocessor test program is found to be abnormal, turning to the step S5, otherwise, turning to the step S2;
step S5: suspending the irradiation of the high-energy particles, resetting the microprocessor to be tested without power failure and running the microprocessor test program again, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, turning to the step S6;
step S6: increasing the K value by 1, resetting the tested microprocessor and re-running the microprocessor test program after power failure, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, judging that SEB occurs, and turning to the step S7;
step S7: and stopping the irradiation of the high-energy particles, and calculating the single-particle latch section C of the microprocessor to be tested.
As a further improvement of the process of the invention: the specified value of the power supply current in the step S1 is 1.5 times to 2 times of the normal working current when the microprocessor to be tested runs the microprocessor test program.
As a further improvement of the process of the invention: and the section C of the single-particle latch of the microprocessor to be tested is K/Q, and Q is the total fluence of high-energy particles when the microprocessor to be tested performs the single-particle latch test.
As a further improvement of the process of the invention: in step S5, the controller for testing continuously resets the tested microprocessor and re-runs the microprocessor test program.
As a further improvement of the process of the invention: in step S7, the controller for testing powers down and resets the tested microprocessor and re-runs the microprocessor test program.
A test system for single event latch-up of a microprocessor comprises a controller and a power supply; the controller is connected with the microprocessor to be tested and the power supply, is in bidirectional communication with the microprocessor to be tested, controls the microprocessor to be tested to run a microprocessor test program and monitor whether the running state of the microprocessor is normal or not, reads the power supply current of the power supply and controls the power supply or power failure of the power supply, performs variable operation, logic judgment and calculation, and counts the number of single event latch-up times; the power supply is connected with the microprocessor to be tested and the controller and is used for supplying power to the microprocessor to be tested and monitoring the power supply current.
As a further improvement of the system of the invention: the microprocessor to be tested is connected with the controller and the power supply, is in two-way communication with the controller, runs a microprocessor test program, and the running state of the test program is used for reflecting whether the running state of the microprocessor to be tested is normal or not.
As a further improvement of the system of the invention: the power supply reports the supply current to the controller and supplies or removes power as required by the controller.
As a further improvement of the system of the invention: the specified value of the power supply current of the power supply is 1.5 times to 2 times of the normal working current when the microprocessor to be tested runs the microprocessor test program.
As a further improvement of the system of the invention: the processor comprises three peripheral components, namely an inner core, an internal memory, an external memory bus interface EMIF, a direct memory access controller DMA and a multi-channel buffer serial port McBSP, and is provided with two power supply ports of 3.3V and 1.2V.
Compared with the prior art, the invention has the advantages that: according to the method and the system for testing the single event latch-up effect of the microprocessor, the characteristic that the microprocessor has abnormal functions and cannot be recovered after power failure when the single event latch-up effect occurs is utilized, the functional state of the microprocessor is reset and restarted without power failure when the power supply current of the microprocessor is increased or the functions of the microprocessor are abnormal, and then whether the functions and the power supply current are recovered to be normal or not is judged to judge whether the single event latch-up effect occurs or not, so that the possibility of false alarm and false alarm leakage of the single event latch-up effect is eliminated.
Drawings
FIG. 1 is a schematic flow chart of the test method of the present invention.
FIG. 2 is a schematic diagram of the structural principle of the test system in a specific application example of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in FIG. 1, the method for testing single event latchup of a microprocessor according to the present invention comprises:
step S1: and supplying power to the microprocessor to be tested and monitoring the power supply current, running a microprocessor test program by the microprocessor to be tested, initializing a single-particle latch counting variable K to be 0, irradiating the microprocessor to be tested by using high-energy particles and beginning to count the total fluence.
Step S2: and (4) if the total fluence of the high-energy particles reaches a preset value, and the preset value meets the requirement of the QJ10005-2008 on the total fluence of the high-energy particles, turning to the step S7, otherwise, turning to the step S3.
Step S3: if the supply current is found to exceed the current specified value, go to step S5, otherwise go to step S4.
In a specific application example, the current designated value is preferably 1.5 times to 2 times of the normal working current when the tested microprocessor runs a microprocessor test program.
Step S4: if the running state of the microprocessor test program is found to be abnormal, go to step S5, otherwise go to step S2.
Step S5: and suspending the irradiation of the high-energy particles, resetting the tested microprocessor without power failure and re-running the microprocessor test program, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, turning to the step S6.
Step S6: and increasing the K value by 1, resetting the tested microprocessor and re-running the microprocessor test program after power failure, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, judging that the SEB occurs, and turning to the step S7.
Step S7: and stopping the irradiation of the high-energy particles, and calculating the single-particle latch section C of the microprocessor to be tested, wherein C is K/Q. Q is the total high-energy particle fluence of the microprocessor to be tested during the single-particle latch-up test.
As shown in FIG. 2, the present invention further provides a system for testing single event latchup of a microprocessor, comprising a controller and a power supply. The tested microprocessor is connected with the controller and the power supply, is in two-way communication with the controller, runs a microprocessor test program, and the running state of the test program can reflect whether the running state of the tested microprocessor is normal or not; the controller is connected with the microprocessor to be tested and the power supply, is in bidirectional communication with the microprocessor to be tested, controls the microprocessor to be tested to run a microprocessor test program and monitor whether the running state of the microprocessor is normal or not, reads the power supply current of the power supply and controls the microprocessor to supply power or cut off the power, performs variable operation, logic judgment and calculation, and counts the number of single event latch-up times; the power supply is connected with the microprocessor to be tested and the controller, supplies power to the microprocessor to be tested, monitors the power supply current, reports the power supply current to the controller, and supplies power or cuts off power according to the requirement of the controller.
With reference to fig. 1, the work flow of the single event latch test system is as follows:
step S1: the power supply of the single-particle latch test system supplies power to the microprocessor to be tested and monitors the power supply current, the microprocessor to be tested runs a microprocessor test program, the single-particle latch counting variable K is initialized to be 0, the microprocessor to be tested is irradiated by high-energy particles, and the total fluence starts to be counted.
Step S2: and (4) if the total fluence of the high-energy particles reaches a preset value, and the preset value meets the requirement of the QJ10005-2008 on the total fluence of the high-energy particles, turning to the step S7, otherwise, turning to the step S3.
Step S3: if the controller of the single event latch test system finds that the supply current exceeds the specified value of the current, go to step S5, otherwise go to step S4. Preferably, the current designated value is 1.5 to 2 times the normal operating current of the microprocessor under test when running the microprocessor test program.
Step S4: if the controller of the single event latch test system finds that the running state of the microprocessor test program is abnormal, go to step S5, otherwise go to step S2.
Step S5: and (4) suspending the irradiation of the high-energy particles, enabling a controller of the single-particle latch test system to continuously reset the tested microprocessor and rerun the test program of the microprocessor, if the power supply current does not exceed the current specified value and the running state of the test program of the microprocessor is normal, resuming the irradiation of the high-energy particles, and turning to the step S2, otherwise, turning to the step S6.
Step S6: and increasing the K value by 1, resetting the tested microprocessor and re-running the microprocessor test program by the controller of the single-particle latch test system in a power-off manner, recovering the irradiation of the high-energy particles if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, and turning to the step S2, otherwise, judging that the SEB occurs, and turning to the step S7.
Step S7: and stopping the irradiation of the high-energy particles, and calculating the single-particle latch section C of the microprocessor to be tested, wherein C is K/Q. Q is the total high-energy particle fluence of the microprocessor to be tested during the single-particle latch-up test.
In combination with the method and system provided by the invention, a single event latch-up test is performed on a certain type of microprocessor in a specific application example. The processor comprises three peripheral components, namely an inner core, an internal memory, an external memory bus interface EMIF, a direct memory access controller DMA and a multi-channel buffer serial port McBSP, and is provided with two power supply ports of 3.3V and 1.2V.
The specific implementation steps are as follows:
the first step is as follows: and constructing a single event latch test system. The single event latch test system consists of an FPGA serving as a controller and a program-controlled voltage source serving as a power supply. The tested microprocessor is connected with the FGPA and the program-controlled voltage source, can be in two-way communication with the FPGA and can also run a test program, and the running state of the test program reflects whether the running states of the kernel, the internal memory, the EMIF, the DMA and the McBSP are normal or not; the FPGA is provided with a plurality of ports which are respectively connected with a tested microprocessor and a program-controlled voltage source, can be in bidirectional communication with the tested microprocessor, can control the microprocessor to reset and restart a test program, can monitor whether the running state of the test program is normal, can read the power supply current of the program-controlled voltage source and control the power supply or power failure of the program-controlled voltage source, can also perform variable operation, logic judgment and calculation, and counts the number of single-event latch-up times; the program control voltage source is connected with the microprocessor to be tested and the FPGA, outputs two paths of power supplies of 3.3V and 1.2V to supply power for the microprocessor to be tested, reports power supply current to the FPGA, and supplies power or cuts off power according to the requirement of the FPGA.
The second step is that: the program control voltage source supplies power to a microprocessor to be tested and monitors two paths of 3.3V and 1.2V power supply currents, the microprocessor to be tested runs a microprocessor test program, a single event latch counting variable K is initialized to be 0, the two paths of power supply currents when the microprocessor to be tested runs the microprocessor test program are measured to be I1 and I2 respectively, Ith1 is calculated to be I1 multiplied by 1.5, Ith2 is calculated to be I2 multiplied by 1.5, the microprocessor to be tested is irradiated by high-energy particles, and total injection is counted.
The third step: if the total fluence of the high-energy particles reaches 107Particle per cm-2And if not, turning to the fourth step.
The fourth step: and if the FPGA finds that the power supply current of the 3.3V power supply is larger than Ith1 or the power supply current of the 1.2V power supply is larger than Ith2, turning to the sixth step, and otherwise, turning to the fifth step.
The fifth step: and if the FPGA finds that the running state of the microprocessor test program is abnormal, the sixth step is carried out, and if not, the third step is carried out.
And a sixth step: and suspending the irradiation of the high-energy particles, resetting the microprocessor to be tested by the FPGA without powering off and running the test program of the microprocessor again, if the power supply current of the 3.3V power supply is not more than Ith1 and the power supply current of the 1.2V power supply is not more than Ith2 and the running state of the test program of the microprocessor is normal, recovering the irradiation of the high-energy particles, turning to the third step, and otherwise, turning to the seventh step.
The seventh step: and increasing the K value by 1, resetting the tested microprocessor by the FPGA in a power-off mode, re-running the microprocessor test program, if the power supply current of the 3.3V power supply is not more than Ith1 and the power supply current of the 1.2V power supply is not more than Ith2 and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, turning to the third step, otherwise, judging that the SEB occurs, and turning to the eighth step.
Eighth step: and stopping the irradiation of the high-energy particles, and calculating the single-particle latch section C of the microprocessor to be tested, wherein C is K/Q. Q is the total high-energy particle fluence of the microprocessor to be tested during the single-particle latch-up test.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (10)
1. A method for testing single event latchup of a microprocessor is characterized by comprising the following steps:
step S1: supplying power to a microprocessor to be tested and monitoring power supply current, running a microprocessor test program by the microprocessor to be tested, initializing a single-particle latch counting variable K to be 0, irradiating the microprocessor to be tested by high-energy particles and beginning to count the total fluence;
step S2: if the total fluence of the high-energy particles reaches a preset value, and the preset value meets the requirement of the preset threshold value on the total fluence of the high-energy particles, turning to the step S7, otherwise, turning to the step S3;
step S3: if the supply current is found to exceed the current designated value, go to step S5, otherwise go to step S4;
step S4: if the running state of the microprocessor test program is found to be abnormal, turning to the step S5, otherwise, turning to the step S2;
step S5: suspending the irradiation of the high-energy particles, resetting the microprocessor to be tested without power failure and running the microprocessor test program again, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, turning to the step S6;
step S6: increasing the K value by 1, resetting the tested microprocessor and re-running the microprocessor test program after power failure, if the power supply current does not exceed the current specified value and the running state of the microprocessor test program is normal, recovering the irradiation of the high-energy particles, and turning to the step S2, otherwise, judging that SEB occurs, and turning to the step S7;
step S7: and stopping the irradiation of the high-energy particles, and calculating the single-particle latch section C of the microprocessor to be tested.
2. The method according to claim 1, wherein the specified value of the supply current in step S1 is 1.5 times to 2 times of the normal operating current of the microprocessor under test when running the microprocessor test program.
3. The method for testing the single event latchup effect of the microprocessor according to claim 1 or 2, wherein the single event latchup cross section C of the microprocessor to be tested is K/Q, and Q is the total fluence of high-energy particles when the microprocessor to be tested performs the single event latchup test.
4. The method for testing single event latchup of a microprocessor according to claim 1 or 2, wherein in step S5, the controller for testing resets the microprocessor under test without power-off and re-runs the microprocessor test program.
5. The method for testing single event latchup of a microprocessor according to claim 1 or 2, wherein in step S7, the controller for testing powers off to reset the microprocessor under test and re-run the microprocessor test program.
6. A test system for single event latch-up effect of microprocessor is characterized by comprising a controller and a power supply; the controller is connected with the microprocessor to be tested and the power supply, is in bidirectional communication with the microprocessor to be tested, controls the microprocessor to be tested to run a microprocessor test program and monitor whether the running state of the microprocessor is normal or not, reads the power supply current of the power supply and controls the power supply or power failure of the power supply, performs variable operation, logic judgment and calculation, and counts the number of single event latch-up times; the power supply is connected with the microprocessor to be tested and the controller and is used for supplying power to the microprocessor to be tested and monitoring the power supply current.
7. The system for testing the single event latchup effect of the microprocessor according to claim 6, wherein the microprocessor under test is connected with the controller and the power supply, is in bidirectional communication with the controller, and runs a microprocessor test program, and the running state of the test program is used for reflecting whether the running state of the microprocessor under test is normal or not.
8. The system for testing single event latchup of a microprocessor according to claim 6, wherein the power supply reports a supply current to the controller and supplies or cuts off power according to the controller requirement.
9. The system of claim 6, wherein the power supply current of the power supply is specified to be 1.5 to 2 times the normal operating current of the microprocessor under test when running the microprocessor test program.
10. The system for testing the single event latchup effect of the microprocessor according to any one of claims 6 to 9, wherein the processor comprises a kernel, an internal memory, three peripheral components of an external memory bus interface EMIF, a direct memory access controller DMA and a multi-channel buffer serial port McBSP, and is provided with two power supply ports of 3.3V and 1.2V.
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