CN111261634A - Manufacturing equipment and method of memory device - Google Patents

Manufacturing equipment and method of memory device Download PDF

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Publication number
CN111261634A
CN111261634A CN202010084060.1A CN202010084060A CN111261634A CN 111261634 A CN111261634 A CN 111261634A CN 202010084060 A CN202010084060 A CN 202010084060A CN 111261634 A CN111261634 A CN 111261634A
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deposition
layer
substrate
memory device
cavity
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吕震宇
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Wuxi Shunming Storage Technology Co ltd
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Wuxi Paibyte Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a manufacturing equipment of a memory device and a method thereof, comprising the following steps: depositing a first deposition layer on a substrate to be processed in a first deposition chamber; transferring the substrate from the first deposition chamber to the second deposition chamber in a vacuum state by a transfer module; and depositing a second deposition layer on the substrate in the second deposition chamber. The method can avoid the contact of the substrate with air or other impurities in the transfer process, thereby obviously improving the interface state between the material layers and further improving the performance of the finally formed device.

Description

Manufacturing equipment and method of memory device
Technical Field
The present invention relates to the field of memory fabrication. More particularly, the present invention relates to a manufacturing apparatus of a memory device and a method thereof.
Background
Ferroelectric memory is a special technology of non-volatile memory. When an electric field is applied to a ferritransistor, the central atom stops at a first low energy state position along the electric field, and when an electric field reversal is applied to the same ferritransistor, the central atom moves in the crystal along the direction of the electric field and stops at a second low energy state. A large number of central atoms move and couple in the crystal unit cell to form a ferroelectric domain, and the ferroelectric domain forms polarization charges under the action of an electric field. The polarization charge formed by the ferroelectric domain reversing under the electric field is higher, and the polarization charge formed by the ferroelectric domain not reversing under the electric field is lower, so that the binary stable state of the ferroelectric material can lead the ferroelectric to be used as a memory.
When the electric field is removed, the central atom is in a low energy state and remains unchanged, and the state of the memory is also preserved and does not disappear, so that the ferroelectric domain can be used for forming high polarization charges by inversion under the electric field or forming low polarization charges without inversion to judge that the memory cell is in a '1' or '0' state. The inversion of the ferroelectric domain does not need high electric field, and the state of the memory cell in '1' or '0' can be changed only by using common working voltage; and a charge pump is not needed to generate high-voltage data erasing, so that the phenomenon of erasing delay is avoided. The characteristic enables the ferroelectric memory to still keep data after power failure, has high writing speed and infinite writing service life, and is not easy to be damaged. And, compared with the existing non-volatile memory technology, the ferroelectric memory has higher writing speed and longer read-write life.
Ferroelectricity is a key factor in ferroelectric memories. Films and materials with better crystallinity, lower defects, will significantly improve the ferroelectricity of ferroelectric memories, resulting in better device performance.
The prior art ferroelectric memory deposition systems and methods typically accomplish all of the processing, such as the deposition of multiple material layers, in one processing chamber. Thus, the elements in the previous layer of material must remain more or less in the chamber, resulting in cross-contamination of the material of one layer with the material of the two layers, thereby affecting device performance.
Disclosure of Invention
An object of the present invention is to provide a method of forming an MIM (Metal-Insulator-Metal) capacitor ferroelectric memory device or an MIS (Metal-Insulator-Semiconductor) ferroelectric memory device having a zero or minimized interfacial region at an interface between a ferroelectric material and an electrode. The oxygen type holes and traps with the zero interface structure are reduced, and the crystallization quality of the film is improved, so that the electrical property of the device is obviously improved.
According to an aspect of the present invention, there is provided a method of manufacturing a memory device, including:
depositing a first deposition layer on a substrate to be processed in a first deposition chamber;
transferring the substrate from the first deposition chamber to the second deposition chamber in a vacuum state by a transfer module; and
and depositing a second deposition layer on the substrate in a second deposition chamber.
In one embodiment of the present invention, the performing of the depositing of the first deposition layer further comprises:
etching the substrate in the etching cavity; and
and transferring the substrate from the etching chamber to the first deposition chamber in a vacuum state through the transfer module.
In one embodiment of the invention, the first deposited layer is a high K ferroelectric oxide.
In one embodiment of the invention, the first deposited layer is one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials.
In one embodiment of the invention, the second deposited layer is an electrode layer, the second deposited layer being one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials.
In one embodiment of the present invention, the method of manufacturing the memory device further includes:
transferring the substrate from the second deposition chamber to the first deposition chamber in a vacuum state by a transfer module; and
and depositing a third deposition layer on the substrate in the first deposition cavity.
In one embodiment of the invention, the first and third deposited layers are electrode layers, the first and third deposited layers being one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials.
In one embodiment of the invention, the second deposited layer is a high K ferroelectric oxide.
In one embodiment of the invention, the second deposited layer is one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials.
According to another aspect of the present invention, there is provided a memory device manufacturing apparatus, including:
the first deposition chamber is used for depositing a first material layer on the wafer to be processed;
the second deposition chamber is used for depositing a second material layer on the wafer to be processed; and
and the transfer module is respectively connected with the first deposition cavity and the second deposition cavity and is used for transferring the wafer between the first deposition cavity and the second deposition cavity, and the transfer module is in a vacuum state in the transfer process.
In another embodiment of the present invention, the memory device manufacturing apparatus further includes: the wafer etching device comprises an etching cavity, a transmission module and a first deposition cavity, wherein the etching cavity is used for etching the impurity layer on the surface of the wafer to remove the impurity layer, the transmission module is connected with the etching cavity, the transmission module is used for transmitting the wafer between the etching cavity and the first deposition cavity or the second deposition cavity, and the transmission module is in a vacuum state in the transmission process.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 shows a schematic view of an in-situ deposition vacuum system according to one embodiment of the present invention.
Fig. 2A to 2E show cross-sectional views of a process of forming a high-k ferroelectric gate field effect transistor according to one embodiment of the present invention.
Figure 3 illustrates a flow diagram for forming a high-k ferroelectric gate field effect transistor according to one embodiment of the present invention.
Fig. 4 shows an electron microscope image of an interface layer between a TiN layer and a high K ferroelectric oxide layer formed by a prior art process.
Fig. 5 shows an electron microscope image of a TiN layer and a high-K ferroelectric oxide layer formed according to an embodiment of the present invention.
Fig. 6A to 6F are cross-sectional views illustrating a process of forming a high dielectric constant ferroelectric capacitor device according to one embodiment of the present invention.
Fig. 7 illustrates a flow diagram for forming a high dielectric constant ferroelectric capacitor device in accordance with one embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
In general, terms may be understood at least in part from the context in which they are used. For example, the terms "one or more" as used herein may be used, at least in part, in the context of context to describe any feature, structure, or characteristic in the singular or in the plural. Similarly, terms such as "a," "an," or "the" may in turn be understood to convey singular usage or plural usage, depending at least in part on the context.
It will be readily understood that the meaning of "on … …", "above … …", and "above … …" in the present invention should be interpreted in the broadest manner such that "on … …" not only means directly on something, but may also include on something with an intermediate feature or layer therebetween, and "on … …", or "on … ….
Furthermore, spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation of the device depicted in the figures. The device may be otherwise oriented (rotated 90 deg. or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
The term "substrate" as used herein refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added over the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may also be made of an electrically non-conductive material, such as glass, plastic, or sapphire wafers.
The term "layer" as used herein refers to a region of material that includes a certain area having a thickness. A layer may extend over all of the underlying or overlying structures or may have a lesser extent than the underlying or overlying structures. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes, or at the top or bottom surface of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or one or more layers thereunder. One layer may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
FIG. 1 shows a schematic view of an in-situ deposition vacuum system 100 according to one embodiment of the present invention. As shown in fig. 1, the in-situ deposition vacuum system 100 may include an etch chamber 110, a first deposition chamber 120, a second deposition chamber 130, and a transfer module 140. In other embodiments of the present invention, the in-situ deposition vacuum system 100 may also include other deposition chambers or process chambers.
The etch chamber 110 may be used to perform atomic layer etch ALE or other similar etch processes.
The first deposition chamber 120 and the second deposition chamber 130 may be used to perform one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
The wafer to be processed is transferred among the etch chamber 110, the first deposition chamber 120, and the second deposition chamber 130 by the transfer module 140. The transfer module 140 is connected to the etch chamber 110, the first deposition chamber 120, and the second deposition chamber 130, respectively. The transfer module 140 maintains the wafer in a vacuum state during the transfer of the wafer, i.e., the transfer module 140 can transfer the wafer to be processed from one chamber to another chamber without substantially changing the vacuum state of the wafer to be processed, thereby achieving multi-layer deposition in different chambers without the wafer to be processed contacting with the external environment.
Fig. 2A to 2E show cross-sectional views of a process of forming a high-k ferroelectric gate field effect transistor according to one embodiment of the present invention. Figure 3 illustrates a flow diagram for forming a high-k ferroelectric gate field effect transistor according to one embodiment of the present invention. A process of forming the MIS FET device by the in-situ deposition vacuum system is described in conjunction with fig. 2A to 2E and fig. 3.
First, at step 310, a semiconductor substrate 210 is provided, as shown in fig. 2A. The substrate 210 may have completed the fabrication process of the functional regions. For example, the substrate 210 has formed source and drain regions S and D. When the substrate 210 is pre-processed, a native oxide layer 211 is formed on the surface of the substrate 210 due to the contact with air.
Next, at step 320, substrate 210 is etched to remove unwanted surface oxides and contaminants from the surface of substrate 210, as shown in FIG. 2B. In an embodiment of the present invention, the substrate 210 may be placed in an etch chamber and an etch operation may be performed by an atomic layer etch process.
Then, at step 330, a deposition of a first deposition layer 220 is performed on the surface of the substrate 210, as shown in fig. 2C. In the in-situ deposition vacuum system, after the substrate 210 is etched, the substrate 210 is transferred to the first deposition chamber through the transfer module to perform deposition of the first deposition layer. The first deposited layer may be a high K ferroelectric oxide, for example, one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials. The first deposited layer may be deposited by one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
By transferring the substrate 210 from the etching chamber to the first deposition chamber by the transfer module without changing the vacuum state of the substrate 210, the substrate is prevented from contacting with the external air to generate SiO, for example, on the surface of the substratexSuch as impurity layer, provided on the surface of the substrate 210The cleaning condition significantly improves the interfacial condition between the substrate 210 and the first deposition layer 220, thereby improving the performance of the finally formed device.
Next, at step 340, deposition of a second deposition layer 230 is performed, as shown in fig. 2D. In the in-situ deposition vacuum system, after the deposition of the first deposition layer 220 is completed, the substrate 210 is transferred to the second deposition chamber through the transfer module, and the deposition of the second deposition layer is performed. The second deposition layer 230 may be an electrode layer, for example, one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials. The second deposited layer may be deposited by one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
The substrate 210 is transferred from the first deposition chamber to the second deposition chamber by the transfer module without changing the vacuum state of the substrate 210, so that the substrate on which the first deposition layer is deposited can be prevented from contacting the outside, and an impurity layer between the first deposition layer 220 and the second deposition layer 230, which is generated due to external impurities such as oxygen or carbon in the air, can be significantly reduced or completely removed, thereby significantly improving the interface state between the first deposition layer 220 and the second deposition layer 230, and further improving the performance of the finally formed device.
In the above embodiments, the first deposition layer 220 is primarily an oxide material, and the second deposition layer 230 is primarily a metal or metal nitride material. Through the in-situ deposition vacuum system with the plurality of deposition cavities, the oxide material and the metal or nitride material are respectively deposited in different cavities, so that the elements (such as oxygen atoms or nitrogen atoms) remained in the cavities in the previous process step are prevented from polluting the subsequent deposition layers. Meanwhile, the in-situ deposition of various deposition layers is realized through the transmission module, the substrate 210 is prevented from contacting with the external environment, and substances such as external particles and oxygen atoms are effectively prevented from entering the deposition material layer.
Fig. 4 shows an electron microscope image of an interface layer between a TiN layer and a high K ferroelectric oxide layer formed by a prior art process. As can be seen from the image of fig. 4, an amorphous interface layer is present between the TiN layer and the high K ferroelectric oxide layer.
Fig. 5 shows an electron microscope image of a TiN layer and a high-K ferroelectric oxide layer formed according to an embodiment of the present invention. As can be seen from fig. 5, the TiN layer and the high K ferroelectric oxide layer have sharp interfaces without amorphous interface layers for transition therebetween, and the interface of the TiN layer and the high K ferroelectric oxide layer has no oxygen-nitrogen coexistence region.
After forming the first and second deposited layers 220 and 230, the substrate 210 is removed from the in-situ deposition vacuum system for subsequent processing of the FET device, as shown in fig. 2E, which includes removing portions of the first and second deposited layers 220 and 230 by an etching process, leaving only the first and second deposited layers 220 and 230 above the gate region; and an insulating layer 240 is deposited. The insulating layer 240 may be SiN.
Fig. 6A to 6F are cross-sectional views illustrating a process of forming a high dielectric constant ferroelectric capacitor device according to one embodiment of the present invention. Fig. 7 illustrates a flow diagram for forming a high dielectric constant ferroelectric capacitor device in accordance with one embodiment of the present invention. A process of forming a MIM capacitor device by an in situ deposition vacuum system is described in conjunction with fig. 6A to 6F and fig. 7.
First, at step 710, a semiconductor substrate 610 is provided, as shown in fig. 6A. The substrate 610 may have completed the fabrication process of the functional regions. After the substrate 610 is pre-processed, a native oxide layer 611 is formed on the surface of the substrate 610 due to the contact of the substrate 610 with air.
Next, at step 720, the substrate 610 is etched to remove unwanted surface oxides and contaminants from the surface of the substrate 610, as shown in FIG. 6B. In an embodiment of the present invention, the substrate 610 may be placed in an etch chamber and an etch operation may be performed by an atomic layer etch process.
Then, at step 730, deposition of a first deposition layer 620 is performed on the surface of the substrate 610, as shown in fig. 6C. In the in-situ deposition vacuum system, after the substrate 610 is etched, the substrate 610 is transferred to the first deposition chamber through the transfer module to perform deposition of the first deposition layer. The first deposition layer 620 may be an electrode layer, for example, one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials. The first deposited layer 620 may be deposited by one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
By transferring the substrate 610 from the etching chamber to the first deposition chamber by the transfer module without changing the vacuum state of the substrate 610, the substrate is prevented from contacting with the external air to generate, for example, SiO on the surface of the substratexSuch as an impurity layer, ensures a clean state of the surface of the substrate 610. Thereby significantly improving the interface state between the substrate 610 and the first deposited layer 620 and thus improving the performance of the finally formed device.
Next, at step 740, deposition of a second deposition layer 630 is performed, as shown in fig. 6D. In the in-situ deposition vacuum system, after the deposition of the first deposition layer 620 is completed, the substrate 610 is transferred to the second deposition chamber through the transfer module, and the deposition of the second deposition layer is performed. The second deposited layer may be a high K ferroelectric oxide, for example, one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials. The second deposited layer may be deposited by one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
By transferring the substrate 610 from the first deposition chamber to the second deposition chamber by the transfer module without changing the vacuum state of the substrate 610, the first deposition layer is prevented from contacting the outside, and the generation of, for example, TiON between the first deposition layer 620 and the second deposition layer 630 due to foreign substances, which may be generated due to the outside, can be significantly reduced or completely removedx、TiCNxAnd the like, thereby significantly improving the interfacial state of the first deposited layer 620 and the second deposited layer 630, and thus improving the performance of the finally formed device.
Next, at step 750, deposition of a third deposition layer 640 is performed, as shown in fig. 6E. In the in-situ deposition vacuum system, after the deposition of the second deposition layer 630 is completed, the substrate 610 is transferred back to the first deposition chamber by the transfer module for deposition of the third deposition layer. The third deposited layer 640 may be an electrode layer, for example, one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials. The third deposited layer may be deposited by one or more of atomic layer deposition ALD, chemical vapor deposition CVD, physical vapor deposition PVD, electron beam Ebeam evaporation deposition, molecular beam epitaxy MBE deposition, pulsed laser deposition PLD, and the like.
The substrate 610 is transferred from the second deposition chamber to the first deposition chamber by the transfer module without changing the vacuum state of the substrate 610, thereby preventing the substrate deposited with the second deposition layer from contacting the outside, and significantly reducing or completely removing the impurity layer formed between the second deposition layer 630 and the third deposition layer 640 due to the external impurities, thereby significantly improving the interface state between the second deposition layer 630 and the third deposition layer 640, and further improving the performance of the finally formed device.
The first and third deposited layers 620, 640 are primarily metal or metal nitride materials in the above embodiments, while the second deposited layer 630 is primarily an oxide material. Through the in-situ deposition vacuum system with the plurality of deposition cavities, the oxide material and the metal or nitride material are respectively deposited in different cavities, so that the elements (such as oxygen atoms or nitrogen atoms) remained in the cavities in the previous process step are prevented from polluting the subsequent deposition layers. Meanwhile, the in-situ deposition of various deposition layers is realized through the transmission module, the substrate is prevented from contacting with the external environment, and substances such as external particles, oxygen atoms and the like are effectively prevented from entering the deposition material layer.
After forming the first, second and third deposition layers 620, 630 and 640, the substrate 610 leaves the in-situ deposition vacuum system for the subsequent processing of the capacitor device, as shown in fig. 6F, including removing a portion of the first, second and third deposition layers 620, 630 and 640 by an etching process; and an insulating layer 650 is deposited. The insulating layer 650 may be SiN.
The first, second and third deposited layers 620, 630 and 640 formed by the method of the present invention have sharp interfaces, an amorphous interface layer for transition between the two material layers is not present, and an oxygen and nitrogen coexisting region is not present at the interface of the two material layers.
The prior art in situ deposition systems and methods typically accomplish all of the processing, such as the deposition of multiple material layers, within one processing chamber. Thus, the elements in the previous material layer must remain more or less in the chamber and cannot be cleaned. Through the disclosed system and method of the invention, the deposition of different material layers is completed in different chambers, thus fundamentally solving the problem of element materials in the chambers. In addition, the method of the invention keeps the transmission module in a vacuum state in the transmission process of different processing cavities, and can avoid the formation of impurity layers due to the contact between wafers and air. As can be seen from the electron microscope images of the TiN layer and the high-K ferroelectric oxide layer formed according to the embodiment of the present invention, the TiN layer and the high-K ferroelectric oxide layer have a sharp interface without an amorphous interface layer for transition therebetween, and the interface of the TiN layer and the high-K ferroelectric oxide layer has no oxygen-nitrogen coexisting region.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (11)

1. A method of manufacturing a memory device, comprising:
depositing a first deposition layer on a substrate to be processed in a first deposition chamber;
transferring the substrate from the first deposition chamber to the second deposition chamber in a vacuum state by a transfer module; and
and depositing a second deposition layer on the substrate in a second deposition chamber.
2. The method of manufacturing a memory device of claim 1, wherein performing the deposition of the first deposition layer further comprises:
etching the substrate in the etching cavity; and
and transferring the substrate from the etching chamber to the first deposition chamber in a vacuum state through the transfer module.
3. The method of manufacturing a memory device of claim 1, wherein the first deposited layer is a high-K ferroelectric oxide.
4. The method of manufacturing a memory device of claim 1, wherein the first deposited layer is one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials.
5. The method of manufacturing a memory device according to claim 1, wherein the second deposited layer is an electrode layer, the second deposited layer being one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials.
6. The method of manufacturing a memory device of claim 1, further comprising:
transferring the substrate from the second deposition chamber to the first deposition chamber in a vacuum state by a transfer module; and
and depositing a third deposition layer on the substrate in the first deposition cavity.
7. The method of manufacturing a memory device according to claim 6, wherein the first and third deposition layers are electrode layers, the first and third deposition layers being one or more of the following materials: TiNx, TaNx, TiAlNx, TiCNx, TaAlNx, TaCNx, AlNx, Ru, RuOx, Ir, IrOx, W, WCNx, Wsix, Pt, Au, Ni, Mo or a combination of these materials.
8. The method of manufacturing a memory device of claim 6, wherein the second deposited layer is a high-K ferroelectric oxide.
9. The method of manufacturing a memory device of claim 6, wherein the second deposited layer is one or more of the following materials: HfOx、AlOx、ZrOx、LaOx、TaOx、NbOx、GdOx、YOx、SiOx、SrOxOr a composite of these materials.
10. A memory device fabrication apparatus, comprising:
the first deposition chamber is used for depositing a first material layer on the wafer to be processed;
the second deposition chamber is used for depositing a second material layer on the wafer to be processed; and
and the transfer module is respectively connected with the first deposition cavity and the second deposition cavity and is used for transferring the wafer between the first deposition cavity and the second deposition cavity, and the transfer module is in a vacuum state in the transfer process.
11. The memory device manufacturing apparatus of claim 10, further comprising:
the wafer etching device comprises an etching cavity, a transmission module and a first deposition cavity, wherein the etching cavity is used for etching the impurity layer on the surface of the wafer to remove the impurity layer, the transmission module is connected with the etching cavity, the transmission module is used for transmitting the wafer between the etching cavity and the first deposition cavity or the second deposition cavity, and the transmission module is in a vacuum state in the transmission process.
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