CN111261589A - Chip plastic package structure, wafer-level plastic package structure and manufacturing method thereof - Google Patents
Chip plastic package structure, wafer-level plastic package structure and manufacturing method thereof Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 26
- 239000005022 packaging material Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 5
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 239000012778 molding material Substances 0.000 claims description 3
- 238000012856 packing Methods 0.000 abstract description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract
The invention provides a chip plastic package structure, a wafer level plastic package structure and a manufacturing method thereof, relating to the technical field of semiconductor production and comprising the following steps: providing a wafer, wherein the wafer comprises a plurality of bottom chips; bonding the outer surface of the wafer with a carrier; cutting the wafer to form a plurality of bottom chips and a plurality of wafer edge chips which are separated from each other; picking up the edge chips of the wafers; and carrying out plastic package on the plurality of bottom chips by using a mold to form a plastic package structure. According to the technical scheme, the wafer is firstly cut into the independent bottom chip wafer edge chips, and the wafer edge chips are picked up and then are subjected to plastic packaging, so that the bottom chips can be prevented from being damaged during the plastic packaging, and the quality and the yield of the packing devices of the wafer level packaging structure are improved compared with the prior art.
Description
Technical Field
The invention relates to the technical field of semiconductor production, in particular to a chip plastic package structure, a wafer level plastic package structure and a manufacturing method thereof.
Background
Unlike the conventional Chip packaging method, Wafer Level Chip Scale Packaging (WLCSP) is a method in which a whole Wafer is packaged and tested, and then cut into individual Chip particles, so that the volume of a packaged package is almost equal to the original size of a bare Chip.
In the plastic packaging process of wafer level packaging, the initial state of the plastic packaging material is liquid or liquid after heating and solidification is carried out after cooling. In order to ensure that the plastic package material injected on the surface of the wafer has a predetermined plastic package density, the liquid plastic package material must have a certain injection pressure in the plastic package mold,
in the current plastic package process of wafer level package, the upper and lower annular molds of the plastic package mold clamp the wafer for wafer level mold package. And the annular clamp of the plastic package mold is pressed at the edge of the inner surface of the wafer to fix the wafer, and the annular clamp is separated from the wafer after the plastic package is finished.
During the clamping process of the ring fixture, the edge portion of the wafer is easily broken or cracked, and the normal chips near the edge of the wafer are affected, thereby causing problems of package quality and yield.
In view of the above, how to avoid edge mold breakage phenomena that are prone to occur during the wafer molding and dicing process is a problem that needs to be addressed currently.
It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a chip plastic package structure, a wafer level plastic package structure and a manufacturing method thereof, which at least solve the problem of edge breakage easily occurring in the process of wafer plastic package and cutting to a certain extent.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.
According to a first aspect of the embodiments of the present invention, a method for manufacturing a wafer level plastic package structure is provided, including: providing a wafer, wherein the wafer comprises a plurality of bottom chips; bonding the outer surface of the wafer with a carrier; cutting the wafer to form a plurality of bottom chips and a plurality of wafer edge chips which are separated from each other; picking up the edge chips of the wafers; and carrying out plastic package on the plurality of bottom chips by using a mold to form a plastic package structure.
In one embodiment, before dicing the wafer, the method further comprises: a chip stack is mounted on the bottom chip.
In one embodiment, after the plurality of bottom chips are molded by using the mold, the method further comprises detaching the carrier and the molding structure from each other.
In one embodiment, the plastic packaging of the plurality of bottom chips using a mold includes: positioning the plurality of bottom chips within a recess of a mold part, the mold part having an inner diameter greater than an outer diameter of the wafer; flowing a molding material into a recess of the mold; and solidifying the plastic packaging material.
In one embodiment, the plastic-sealing of the plurality of bottom chips using a mold further includes: and enabling the plastic packaging material to surround the side surface of the bottom chip carrying the chip stack group and cover the upper surface of the wafer.
In one embodiment, the picking up the plurality of wafer edge chips further comprises: and picking up the bottom chip with poor test.
In one embodiment, the mounting of the chip stack group onto the bottom chip comprises: the chip stack group is provided only on the well-tested bottom chip.
In one embodiment, detaching the carrier and the plastic package structure from each other includes: and detaching the plastic package structure from the carrier without removing the plastic package material.
In one embodiment, bonding the outer surface of the wafer to a carrier includes: and bonding the wafer and the carrier through an adhesive tape.
According to a second aspect of the embodiments of the present invention, there is provided a wafer level plastic package structure, including: a plurality of bottom chips; the chip stack group is arranged on the plurality of bottom chips, and gaps are formed among the plurality of bottom chips; and the plastic packaging material covers the inner surface of the bottom chip, and the plastic packaging material covers the side surface of the bottom chip.
In one embodiment, the gap has a width of 50 μm to 200 μm.
In one embodiment, the structure further comprises: and the carrier is adhered to the outer surface of the bottom chip.
In one embodiment, the bottom chip comprises a controller chip or a silicon interposer.
In one embodiment, the chip stack groups are communicated through silicon through holes; and/or the outer surface of the bottom chip is provided with a mounting terminal.
In one embodiment, the bottom chip and the chip stack group are electrically connected through a top bump or a pillar bump provided with solder.
According to a third aspect of the embodiments of the present invention, there is provided a chip plastic package structure, the structure is manufactured according to the manufacturing method of the wafer level plastic package structure in the above technical solution, and the structure includes:
a bottom chip; a chip stack group arranged on the bottom chip; and the plastic packaging material covers the inner surface of the bottom chip, and the plastic packaging material covers the side surface of the bottom chip.
In one embodiment, the bottom chip comprises a controller chip or a silicon interposer.
In one embodiment, the chip stack groups are connected through-silicon vias.
In one embodiment, the bottom chip and the chip stack group are electrically connected through a top bump or a pillar bump provided with solder.
In one embodiment, the outer surface of the bottom chip is provided with mounting terminals.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the technical solution provided in an exemplary embodiment of the present invention, the wafer is first cut into the independent bottom chip and the edge chips of the wafer are picked up and then plastic-packaged, so that the damage to the bottom chips during the plastic packaging can be avoided, and the quality and yield of the packing quality and yield of the wafer level packaging structure are improved compared with the prior art.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 schematically shows a structure diagram of a wafer-level plastic package structure in the related art;
FIG. 2 schematically illustrates a block diagram of a wafer level plastic package structure in accordance with one embodiment of the present invention;
FIG. 3 is a block diagram schematically illustrating a wafer level plastic package structure according to another embodiment of the present invention;
FIG. 4 schematically illustrates a flow chart of a method of fabricating a wafer level plastic package structure in accordance with one embodiment of the present invention;
FIG. 5 is a flow chart schematically illustrating a method of fabricating a wafer level plastic package structure, in accordance with another embodiment of the present invention;
fig. 6 to 10 are schematic cross-sectional views of steps S401 to S405;
fig. 11 schematically shows a structure diagram of a chip plastic package structure according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. The exemplary embodiments, however, may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the module of the icon is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
In the related art, as shown in fig. 1, in a wafer-level plastic package structure 100, a stacked chip set 102 is disposed on a wafer 101, and a plastic package structure 103 covers an inner surface of the wafer 101, where the wafer is not diced, and covers an upper surface and a side surface of the stacked chip set and a portion of the inner surface of the wafer 101 that is not covered by the stacked chip set.
Therefore, in the above technical solution, when the wafer-level plastic package structure is manufactured, the wafer is firstly subjected to plastic package and then is cut. Therefore, when the upper and lower dies of the plastic package die are used for clamping the wafer, the annular clamp of the plastic package die is pressed on the edge of the inner surface of the wafer, so that the edge of the wafer is easily damaged, and the packaging quality and the yield are further influenced.
In the manufacturing process of the wafer-level plastic package structure provided by the embodiment of the disclosure, the technical scheme that the wafer is firstly subjected to plastic package and then the wafer is cut in the related technology is changed into the technical scheme that the wafer is firstly cut, and then the bottom chip is subjected to plastic package after the edge chip of the wafer is picked up. Before the wafer is cut, a carrier needs to be adhered to the outer surface of the wafer before the wafer is cut, and the carrier is removed after the inner surface of the bottom chip is subjected to plastic packaging. Therefore, when the upper die and the lower die of the plastic package die are used for clamping the wafer, the annular clamp of the plastic package die is pressed on the carrier, the upper die does not press the edge of the wafer, the clamping stress of the die cannot be directly transmitted to the bottom chip, and the edge of the wafer cannot be damaged. The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 2 schematically shows a structure diagram of a wafer-level plastic package structure according to an exemplary embodiment of the present disclosure, and referring to fig. 2, a wafer-level plastic package structure 200 provided in an embodiment of the present invention includes: a plurality of bottom chips 201; a chip stack group 102 disposed on a plurality of bottom chips with a gap therebetween; and the plastic packaging material 203 covers the inner surface of the bottom chip, and covers the side surface of the bottom chip. As shown in fig. 2, gaps are formed among the plurality of bottom chips 201, and a portion of the molding compound is filled in the gaps.
In the embodiment of the invention, the wafer is cut before plastic package, and non-chip peripheral blocks at the periphery of the wafer, namely the chip at the edge of the wafer, are removed, so that the plastic package material can completely surround the bottom chip, and the chip is protected from being damaged by external force, thereby achieving the aim of improving the manufacturing quality of the semiconductor package.
In the present embodiment, the width of the gap is between 50 μm and 200 μm. For example, the gaps between the multiple chips may be: 80 μm, 110 μm, 140 μm or 170 μm.
The dicing wafer may be cut by using a diamond blade or a laser, and the thickness of the diamond blade is generally 10 μm to 100 μm, so that the width of the gap between the plurality of base chips is wider than the thickness of the diamond blade.
Here, the chip stack group may be at least one semiconductor die disposed on a bottom chip. Or at least one integrated circuit disposed on the base chip. Each bottom chip is electrically connected to a corresponding one of the chip stack groups.
In various embodiments, the bottom chip may be a controller chip or a silicon interposer. The integrated circuit side, i.e., the inner surface, of the bottom chip faces the stacked chip set.
In an exemplary embodiment of the present disclosure, as shown in fig. 3, the wafer-level plastic package structure 300 and the wafer-level plastic package structure 200 each include a bottom chip 201, a stacked chip set 102, and a plastic package material 103, and the difference is that the wafer-level plastic package structure 300 further includes a carrier 204, wherein the carrier 204 is bonded to an outer surface of the bottom chip 201 by an adhesive tape 205.
The bonding of the carrier and the wafer can prevent the wafer from warping due to too thin thickness. The carrier may be provided as hard glass or dicing tape.
Here, the chips in the chip stack group 102 are electrically connected to each other through the through-silicon vias. Through Silicon Vias (TSV) are through silicon vias.
The bottom chip is conducted with the chip stack group through the convex block or the columnar convex block with the solder arranged at the top end.
The outer surface of the bottom chip is provided with a mounting terminal. The mounting terminals are also called mounting bonding terminals, and have a function of electrically connecting the bottom chip with other devices. The mounting terminal may be a solder ball or a bump, or may be a columnar bump having a solder provided on its tip.
It should be noted that, although the schematic structural diagrams shown in fig. 2 and fig. 3 only include four bottom chips and four chip stack groups, fig. 2 and fig. 3 are only simple schematic diagrams drawn for specifically explaining the package structure, and actually, the wafer-level plastic package structure of the present embodiment may include a plurality of bottom chips and a plurality of chip stack groups, and is not limited to the schematic structural diagrams shown in fig. 2 and fig. 3.
The wafer-level plastic package structure provided by the invention can prevent the bottom chip from being damaged during plastic package by firstly cutting the wafer into the independent bottom chip wafer edge chips and then carrying out plastic package after picking up the wafer edge chips, and improves the packaging quality and yield of the wafer level plastic package structure compared with the prior art.
Fig. 4 is a flowchart of a method for manufacturing a wafer-level plastic package structure according to an embodiment of the disclosure. As shown in fig. 4, a method for manufacturing a wafer-level plastic package structure according to an exemplary embodiment of the present disclosure includes:
step S401, a wafer including a plurality of bottom chips is provided.
Step S402, bonding the outer surface of the wafer with the carrier.
Step S404, dicing the wafer to form a plurality of bottom chips and a plurality of wafer edge chips separated from each other.
In step S405, a plurality of wafer edge chips are picked up.
And step S406, carrying out plastic package on the plurality of bottom chips by using a mold to form a plastic package structure.
In the embodiment of the invention, the wafer is cut before plastic package, and non-chip peripheral blocks at the periphery of the wafer, namely the chip at the edge of the wafer, are removed, so that the plastic package material can completely surround the bottom chip and protect the bottom chip from being damaged by external force, thereby achieving the aim of improving the manufacturing quality of the semiconductor package.
After step S401 is performed, a cross-sectional view shown in fig. 6 is formed. The wafer 206 includes a plurality of bottom chips 201.
In step S402, the wafer is bonded to the carrier by the tape. After step S402 is performed, a cross-sectional view as shown in fig. 7 is formed. As shown in fig. 7, the outer surface of the wafer is bonded to carrier 204 by tape 205. The bonding of the carrier and the wafer can prevent the wafer from warping due to too thin thickness. In addition, the carrier can be bonded to the adhesive material via the wafer. The adhesive material may be heated to weaken its adhesion to the wafer, thereby facilitating removal of the carrier relative to the wafer.
Step S404 is a singulation process for the wafer. After step S404 is performed, a cross-sectional view as shown in fig. 9 is formed.
In step S405, when picking up the edge chips of the plurality of wafers, it is also necessary to pick up the bottom chips with poor test so as to improve the yield of the finished product. After step S405 is performed, a cross-sectional view as shown in fig. 10 is formed.
In step S406, first, a plurality of bottom chips are positioned in a recess of a mold part, wherein an inner diameter of the mold part is larger than an outer diameter of a wafer; then flowing the molding material into the recess of the mold; and then solidifying the plastic packaging material. After step S406 is performed, a cross-sectional view as shown in fig. 3 is formed.
And after the plastic packaging material is completely cured, separating the clamp of the mold component from the carrier with the plastic packaging material. At this time, the plastic package material completely packages the chip stack group and the bottom chip, i.e., surrounds six surfaces of the chip stack group and the bottom chip.
Specifically, in the process of plastic-packaging a plurality of bottom chips by using a mold, a plastic-packaging material is required to surround side surfaces of the plurality of bottom chips loaded with the chip stack group and cover an upper surface of the wafer at the same time.
In an exemplary embodiment of the disclosure, in another manufacturing method of a wafer-level plastic package structure shown in fig. 5, step S401, step S402, step S404, step S405, and step S406 are all the same as the manufacturing method of the wafer-level plastic package structure shown in fig. 4, except that the manufacturing method of the wafer-level plastic package structure shown in fig. 5 further includes the following steps:
in step S403, the chip stack group is mounted on the bottom chip.
And step S407, mutually detaching the carrier and the plastic package structure.
In step S403, a chip stack group is set only on the well-tested bottom chips. After step S403 is performed, a cross-sectional view shown in fig. 8 is formed. Thus, waste of the chip stack group can be avoided. The bad test bottom chips will be picked up together with the plurality of wafer edge chips in step S405. Here, even if the bottom chip with poor test is provided with the chip stack group and is formed into a finished chip through the plastic package procedure, the bottom chip with poor test is detected as poor in the subsequent test process, so that the waste of the chip stack group is caused.
In step S407, the plastic encapsulated structure is detached from the carrier without removing the plastic encapsulating material. After step 407, a cross-sectional view as shown in fig. 2 is formed.
And then, carrying out separation cutting on the wafer level plastic package structure to form a chip plastic package structure. The process may use a diamond cutting process or a laser cutting process for cutting.
In the method for manufacturing a wafer-level plastic package structure according to the exemplary embodiment of the invention, the wafer is first cut into the independent bottom chip wafer edge chips, and the wafer edge chips are picked up and then plastic-packaged, so that the bottom chips are prevented from being damaged during plastic packaging, and the packaging quality and yield of the wafer level packaging structures are improved compared with the prior art.
As shown in fig. 11, an embodiment of the present invention further provides a chip plastic package structure 400, which is manufactured according to the method for manufacturing a wafer-level plastic package structure in the foregoing technical solution, and includes: a bottom chip 201; a chip stack group 102 disposed on the bottom chip 201; and the plastic package material 403 covers the inner surface of the bottom chip, and covers the side surface of the bottom chip.
The structure is a product obtained by performing the separation and cutting on the wafer level package structure 200 in the above embodiment.
Here, the bottom chip includes a controller chip or a silicon interposer.
The chip stack groups 102 are connected through-silicon vias. Through Silicon Vias (TSV) are through silicon vias. Here, the set of chip stacks comprises at least two integrated circuits or at least two dies. The two integrated circuits are conducted through the silicon through hole. Or the two bare chips are conducted through a through silicon via.
The bottom chip is conducted with the chip stack group through the convex block or the columnar convex block with the solder arranged at the top end.
The outer surface of the bottom chip is provided with a mounting terminal. The mounting terminals are also called mounting bonding terminals, and have a function of electrically connecting the bottom chip with other devices. The mounting terminal may be a solder ball or a bump, or may be a columnar bump having a solder provided on its tip.
According to the chip plastic package structure provided by the invention, the wafer is firstly cut into the independent bottom chip wafer edge chip, and the plastic package is carried out after the wafer edge chip is picked up, so that the bottom chip can be prevented from being damaged during the plastic package.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (20)
1. A manufacturing method of a wafer-level plastic package structure is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises a plurality of bottom chips;
bonding the outer surface of the wafer with a carrier;
cutting the wafer to form a plurality of bottom chips and a plurality of wafer edge chips which are separated from each other;
picking up the edge chips of the wafers;
and carrying out plastic package on the plurality of bottom chips by using a mold to form a plastic package structure.
2. The method of claim 1, wherein before dicing the wafer, the method further comprises:
a chip stack is mounted on the bottom chip.
3. The method of manufacturing according to claim 2, wherein after the molding the plurality of base chips with the mold, the method further comprises:
and mutually detaching the carrier and the plastic packaging structure.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the step of plastically molding the plurality of base chips by using a mold comprises:
positioning the plurality of bottom chips in a recess of a mold, the mold having an inner diameter greater than an outer diameter of the wafer;
flowing a molding material into a recess of the mold;
and solidifying the plastic packaging material.
5. The method of manufacturing according to claim 4, wherein the plurality of bottom chips are plastically packaged using a mold, further comprising:
and enabling the plastic packaging material to surround the side surface of the bottom chip carrying the chip stack group and cover the upper surface of the wafer.
6. The method of claim 5, wherein the picking the plurality of wafer edge chips further comprises:
and picking up the bottom chip with poor test.
7. The method of manufacturing of claim 6, wherein said mounting a set of chip stacks on said bottom chip comprises:
the chip stack group is provided only on the well-tested bottom chip.
8. The method of manufacturing according to claim 7, wherein detaching the carrier and the plastic encapsulated structure from each other comprises:
and detaching the plastic package structure from the carrier without removing the plastic package material.
9. The method of claim 8, wherein bonding the outer surface of the wafer to a carrier comprises:
and bonding the wafer and the carrier through an adhesive tape.
10. A wafer level plastic package packaging structure, comprising:
a plurality of bottom chips;
the chip stack group is arranged on the plurality of bottom chips, and gaps are formed among the plurality of bottom chips;
and the plastic packaging material covers the inner surface of the bottom chip, and the plastic packaging material covers the side surface of the bottom chip.
11. The structure of claim 10, wherein the gap has a width of 50 μm to 200 μm.
12. The structure of claim 11, further comprising:
and the carrier is adhered to the outer surface of the bottom chip.
13. The structure of claim 12, wherein the bottom chip comprises a controller chip or a silicon interposer.
14. The structure of claim 13, wherein the chip stack groups are electrically connected by through-silicon vias; and/or the outer surface of the bottom chip is provided with a mounting terminal.
15. The structure of claim 14, wherein the bottom chip and the chip stack are electrically connected by bumps or stud bumps with solder disposed on top.
16. A chip plastic package structure, wherein the structure is manufactured according to the method for manufacturing a wafer-level plastic package structure as claimed in any one of claims 1 to 9, the structure comprising:
a bottom chip;
a chip stack group arranged on the bottom chip;
and the plastic packaging material covers the inner surface of the bottom chip, and the plastic packaging material covers the side surface of the bottom chip.
17. The structure of claim 16, wherein the bottom chip comprises a controller chip or a silicon interposer.
18. The structure of claim 17, wherein the chip stack groups are electrically connected to each other through-silicon vias.
19. The structure of claim 16, wherein the bottom chip and the chip stack are electrically connected by bumps or stud bumps with solder disposed on top.
20. The structure of claim 16, wherein an outer surface of the bottom die is provided with mounting terminals.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811459386.7A CN111261589A (en) | 2018-11-30 | 2018-11-30 | Chip plastic package structure, wafer-level plastic package structure and manufacturing method thereof |
| PCT/CN2019/121909 WO2020108602A1 (en) | 2018-11-30 | 2019-11-29 | Chip molding structure, wafer level chip scale packaging structure and manufacturing method thereof |
| EP19888608.7A EP3888122B1 (en) | 2018-11-30 | 2019-11-29 | Chip molding structure, wafer level chip scale packaging structure and manufacturing method thereof |
| US17/331,133 US20210287917A1 (en) | 2018-11-30 | 2021-05-26 | Chip molding structure, wafer level chip scale packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811459386.7A CN111261589A (en) | 2018-11-30 | 2018-11-30 | Chip plastic package structure, wafer-level plastic package structure and manufacturing method thereof |
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