CN111261207A - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

Info

Publication number
CN111261207A
CN111261207A CN201910796473.XA CN201910796473A CN111261207A CN 111261207 A CN111261207 A CN 111261207A CN 201910796473 A CN201910796473 A CN 201910796473A CN 111261207 A CN111261207 A CN 111261207A
Authority
CN
China
Prior art keywords
write
signal
control signal
internal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910796473.XA
Other languages
Chinese (zh)
Other versions
CN111261207B (en
Inventor
金雄来
郭明均
李承燻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Publication of CN111261207A publication Critical patent/CN111261207A/en
Application granted granted Critical
Publication of CN111261207B publication Critical patent/CN111261207B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

The invention discloses a semiconductor device. The semiconductor device includes an input/output I/O control signal generating circuit, a pipeline circuit, and an auto-precharge signal generating circuit. The I/O control signal generating circuit generates an input control signal, an output control signal, and an internal output control signal. The pipe circuit latches the internal command/address signal based on the input control signal, and outputs the latched internal command/address signal as a latch signal. An auto-precharge signal generation circuit generates an auto-precharge signal from the latch signal and the internal latch signal.

Description

Semiconductor device with a plurality of transistors
Cross Reference to Related Applications
The present application claims priority from korean patent application No. 10-2018-0153937, filed on 3.12.2018, the entire contents of which are incorporated herein by reference.
Technical Field
Embodiments of the present disclosure relate to a semiconductor device performing an auto-precharge operation.
Background
The semiconductor device performs a write operation for storing data into the cell array or a read operation for outputting data stored in the cell array. If a write operation or a read operation is performed, the semiconductor device may perform an auto-precharge operation after receiving or outputting data having one or more bits, the number of which is set according to a burst length.
Disclosure of Invention
According to one embodiment, a semiconductor device includes an input/output (I/O) control signal generation circuit, a pipeline circuit, and an auto-precharge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal, and an internal output control signal based on the bank mode and the burst length. The pipe circuit latches the internal command/address signal based on the input control signal, and outputs the latched internal command/address signal as a latch signal based on the output control signal, and outputs the latched internal command/address signal as an internal latch signal based on the internal output control signal. An auto-precharge signal generation circuit generates an auto-precharge signal from the latch signal and the internal latch signal based on the bank mode and burst length.
According to another embodiment, a semiconductor device includes an input/output (I/O) control signal generation circuit, a pipeline circuit, and an auto-precharge signal generation circuit. The I/O control signal generation circuit generates a write input control signal based on the write signal, and generates a write output control signal and an internal write output control signal based on the write flag and the internal write flag. The pipe circuit is synchronized with the write input control signal to latch the internal command/address signal, and with the write output control signal to output the latched internal command/address signal as a write latch signal, and is configured to be synchronized with the internal write output control signal to output the latched internal command/address signal as an internal write latch signal. In the bank group mode in which column operations are performed before and after the bubble period, the auto-precharge signal generation circuit generates a write auto-precharge signal based on the internal write latch signal, and if the semiconductor device transitions to a different bank mode, the auto-precharge signal generation circuit generates the write auto-precharge signal based on the write latch signal.
According to still another embodiment, a semiconductor device includes an input/output (I/O) control signal generation circuit, a pipeline circuit, and an auto-precharge signal generation circuit. The I/O control signal generation circuit generates a read input control signal based on the read signal, and generates a read output control signal and an internal read output control signal based on the read flag and the internal read flag. The pipe circuit is synchronized with the read input control signal to latch the internal command/address signal, and with the read output control signal to output the latched internal command/address signal as a read latch signal, and is configured to be synchronized with the internal read output control signal to output the latched internal command/address signal as an internal read latch signal. An auto-precharge signal generation circuit generates a read auto-precharge signal based on an internal read latch signal in a bank group mode in which column operations are performed before and after a bubble period; and generating a read auto-precharge signal based on the read latch signal if the semiconductor device is transitioned to a different bank mode.
Drawings
Fig. 1 is a block diagram illustrating a configuration of a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is a circuit diagram showing an example of a write input control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 3 shows an example of a read input control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 4 shows an example of a write output control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 5 shows an example of an internal write output control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 6 shows an example of a read output control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 7 shows an example of an internal read output control signal generation circuit included in the semiconductor device of fig. 1.
Fig. 8 is a block diagram illustrating an example of a first write pipe group included in the semiconductor device of fig. 1.
Fig. 9 is a circuit diagram illustrating an example of a first write pipe included in the first write pipe group of fig. 8.
Fig. 10 is a block diagram illustrating an example of a second write pipe group included in the semiconductor device of fig. 1.
Fig. 11 is a block diagram illustrating an example of a read pipe group included in the semiconductor device of fig. 1.
Fig. 12 is a block diagram illustrating an example of an auto-precharge signal generation circuit included in the semiconductor device of fig. 1.
Fig. 13 is a circuit diagram showing an example of a selection signal generation circuit included in the auto-precharge signal generation circuit of fig. 12.
Fig. 14 is a circuit diagram showing an example of a precharge signal generation circuit included in the auto-precharge signal generation circuit of fig. 12.
Fig. 15 shows an example of an auto-precharge signal output circuit included in the auto-precharge signal generation circuit of fig. 12.
Fig. 16 is a timing diagram illustrating an operation of the semiconductor device illustrated in fig. 1 to 15.
Fig. 17 is a block diagram showing a configuration of an electronic system employing the semiconductor device shown in fig. 1.
Detailed Description
Various embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, the examples described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.
A semiconductor device including a plurality of banks may provide various bank modes such as a bank group mode, an 8 bank mode, and a 16 bank mode. The plurality of banks may constitute a bank group. For example, four memory banks may constitute one bank group. In the bank group mode, a column operation for one bank included in the bank group may be performed by one command. In the 8-bank mode, column operations for two banks respectively included in two different bank groups may be sequentially performed by one command. In the 16-bank mode, column operations for four banks respectively included in four different bank groups may be sequentially performed by one command. In the bank group mode, column operations may be performed according to burst lengths, respectively. For example, if the burst length is set to '16' in the bank group mode, a column operation for 16-bit data may be performed at a time. However, if the burst length is set to '32' in the bank group mode, a first column operation for 16-bit data may be performed first, and a second column operation for the remaining 16-bit data may be performed after a bubble period (bubble period) elapses when the first column operation is terminated. The bubble period may be the duration of a column operation of another bank group. For example, when a read operation or a write operation is performed in the bank group mode with the burst length set to '32', the bubble period may be a time length of: after the column operation for the first 16-bit data is performed, the column operation for the second 16-bit data is performed in the length of time. The bubble period is required only when the burst length is set to '32' in the bank group mode. The bubble period may be set as a period for performing a column operation for 16-bit data. During the bubble period, a column operation for another bank may also be performed. In this case, a bubble period may be used to sequentially perform a plurality of column operations for a plurality of banks.
As shown in fig. 1, a semiconductor device 1 according to one embodiment may include a command decoder 2, a flag generation circuit 3, an input/output (I/O) control signal generation circuit 4, a pipe circuit 5, an auto-precharge signal generation circuit 6, and an auto-precharge control circuit 7.
The command decoder 2 may decode the command/address signals CA <1: L > to generate the write signal EWT and the read signal ERT. The write signal EWT may be generated to perform a write operation. The read signal ERT may be generated to perform a read operation. The logic level combinations of the command/address signals CA <1: L > for generating the write signal EWT or the read signal ERT may be set differently according to embodiments.
The flag generation circuit 3 may generate a write flag WTTF and an internal write flag IWTTF in response to the write signal EWT. The flag generation circuit 3 may generate the write flag WTTF after the write signal EWT is generated to perform the write operation and when the first write delay period elapses. The flag generation circuit 3 may also generate the internal write flag IWTTF after the write signal EWT is generated to perform the write operation and when the second write delay period has elapsed. The first write delay period may be set by the write latency. The second write delay period may be set by a write latency and a burst length. When the write flag delay period elapses after the write flag WTTF is generated, the internal write flag IWTTF may be generated. The write flag delay period for generating the internal write flag IWTTF may be set differently according to the embodiment. For example, in the case where the burst length is set to '32' in the bank group mode, the write flag delay period may be set to a period required to receive 32-bit data in order to perform a write operation.
The flag generation circuit 3 may generate a read flag RDTF and an internal read flag IRDTF in response to the read signal ERT. The flag generation circuit 3 may generate the read flag RDTF when a first read delay period elapses after the read signal ERT is generated to perform the read operation. The flag generation circuit 3 may also generate the internal read flag IRDTF when a second read delay period elapses after the read signal ERT is generated to perform the read operation. The first read delay period may be set differently according to embodiments. The flag generation circuit 3 may generate the read flag RDTF in synchronization with the read signal ERT. The internal read flag IRDTF may be generated after a read flag delay period has elapsed from a point in time at which the read flag RDTF is generated. The read flag delay period for generating the internal read flag IRDTF may be set differently according to the embodiment. For example, in the case where the burst length is set to '32' in the bank group mode, the read flag delay period may be set to a period required to receive 32-bit data in order to perform a read operation.
The I/O control signal generation circuit 4 may generate first to fourth write-in control signals WPIN <1:4>, first to fourth write-out control signals WPOUT <1:4>, and first to fourth internal write-out control signals IWPOUT <1:4> based on the write signal EWT, the write flag WTTF, and the internal write flag IWTTF. The I/O control signal generation circuit 4 may generate first and second read input control signals RPIN <1:2>, first and second read output control signals RPOUT <1:2>, and first and second internal read output control signals IRPOUT <1:2> based on the read signal ERT, the read flag RDTF, and the internal read flag IRDTF. The I/O control signal generation circuit 4 may include a write input control signal generation circuit 41, a read input control signal generation circuit 42, a write output control signal generation circuit 43, an internal write output control signal generation circuit 44, a read output control signal generation circuit 45, and an internal read output control signal generation circuit 46.
The write input control signal generation circuit 41 may sequentially and repeatedly generate the first to fourth write input control signals WPIN <1:4> whenever the write signal EWT is generated. For example, if the write signal EWT is generated for the first time, the write input control signal generation circuit 41 may generate a first write input control signal WPIN <1>, if the write signal EWT is generated for the second time, the write input control signal generation circuit 41 may generate a second write input control signal WPIN <2>, if the write signal EWT is generated for the third time, the write input control signal generation circuit 41 may generate a third write input control signal WPIN <3>, if the write signal EWT is generated for the fourth time, the write input control signal generation circuit 41 may generate a fourth write input control signal WPIN <4>, and if the write signal EWT is generated for the fifth time, the write input control signal generation circuit 41 may generate the first write input control signal WPIN <1>, and so on. The configuration and operation of the write input control signal generation circuit 41 will be described more fully later with reference to fig. 2.
The read input control signal generation circuit 42 may alternately generate the first read input control signal and the second read input control signal RPIN <1:2> whenever the read signal ERT is generated. For example, if the read signal ERT is generated for the first time, the read input control signal generation circuit 42 may generate the first read input control signal RPIN <1>, if the read signal ERT is generated for the second time, the read input control signal generation circuit 42 may generate the second read input control signal RPIN <2>, and if the read signal ERT is generated for the third time, the read input control signal generation circuit 42 may generate the first read input control signal RPIN <1>, and so on. The configuration and operation of the read input control signal generation circuit 42 will be described more fully later with reference to fig. 3.
The write output control signal generation circuit 43 may sequentially and repeatedly generate the first to fourth write output control signals WPOUT <1:4> whenever the write flag WTTF is generated. For example, if the write flag WTTF is generated for the first time, the write output control signal generation circuit 43 may generate the first write output control signal WPOUT <1>, if the write flag WTTF is generated for the second time, the write output control signal generation circuit 43 may generate the second write output control signal WPOUT <2>, if the write flag WTTF is generated for the third time, the write output control signal generation circuit 43 may generate the third write output control signal WPOUT <3>, if the write flag WTTF is generated for the fourth time, the write output control signal generation circuit 43 may generate the fourth write output control signal WPOUT <4>, and if the write flag WTTF is generated for the fifth time, the write output control signal generation circuit 43 may generate the first write output control signal WPOUT <1>, and so on. The configuration and operation of the write output control signal generation circuit 43 will be described more fully later with reference to fig. 4.
The internal write output control signal generation circuit 44 may generate the first to fourth internal write output control signals IWPOUT <1:4> from the internal write flag IWTTF based on the operation mode signal 4BG and the burst operation mode signal 4BG _ BL 32. The operation mode signal 4BG may include information on whether the semiconductor device 1 enters the bank group mode. The burst operation mode signal 4BG _ BL32 may include information on whether a write operation is performed with a burst length of '32' in the bank group mode. In the case where a write operation is performed with the burst length '32' in the bank group mode, the internal write output control signal generation circuit 44 may sequentially and repeatedly generate the first to fourth internal write output control signals IWPOUT <1:4> whenever the internal write flag IWTTF is generated. For example, if the internal write flag IWTTF is generated for the first time, internal write output control signal generation circuit 44 may generate a first internal write output control signal IWPOUT <1>, if the internal write flag IWTTF is generated for the second time, internal write output control signal generation circuit 44 may generate a second internal write output control signal IWPOUT <2>, if the internal write flag IWTTF is generated for the third time, internal write output control signal generation circuit 44 may generate a third internal write output control signal IWPOUT <3>, if the internal write flag IWTTF is generated for the fourth time, internal write output control signal generation circuit 44 may generate a fourth internal write output control signal IWPOUT <4>, and if the internal write flag IWTTF is generated for the fifth time, internal write output control signal generation circuit 44 may generate a first internal write output control signal IWPOUT <1>, and so on. The configuration and operation of the internal write output control signal generation circuit 44 will be described more fully later with reference to fig. 5.
The read output control signal generation circuit 45 may alternately generate the first read output control signal and the second read output control signal RPOUT <1:2> whenever the read flag RDTF is generated. For example, if the read flag RDTF is generated for the first time, the read output control signal generation circuit 45 may generate the first read output control signal RPOUT <1>, if the read flag RDTF is generated for the second time, the read output control signal generation circuit 45 may generate the second read output control signal RPOUT <2>, and if the read flag RDTF is generated for the third time, the read output control signal generation circuit 45 may generate the first read output control signal RPOUT <1>, and so on. The configuration and operation of the read output control signal generation circuit 45 will be described more fully later with reference to fig. 6.
The internal read output control signal generation circuit 46 may generate first and second internal read output control signals IRPOUT <1:2> from the internal read flag IRDTF based on the operation mode signal 4BG and the burst operation mode signal 4BG _ BL 32. In the case where a read operation is performed with the burst length '32' in the bank group mode, the internal read output control signal generation circuit 46 may alternately generate the first internal read output control signal and the second internal read output control signal IRPOUT <1:2> whenever the internal read flag IRDTF is generated. For example, if the internal read flag IRDTF is generated a first time, the internal read output control signal generation circuit 46 may generate a first internal read output control signal IRPOUT <1>, if the internal read flag IRDTF is generated a second time, the internal read output control signal generation circuit 46 may generate a second internal read output control signal IRPOUT <2>, and if the internal read flag IRDTF is generated a third time, the internal read output control signal generation circuit 46 may generate the first internal read output control signal IRPOUT <1>, and so on. The configuration and operation of the internal read output control signal generation circuit 46 will be described more fully later with reference to fig. 7.
The pipe circuit 5 may store the internal command/address signal ICAF < K > based on the first to fourth write input control signals WPIN <1:4> and may output the stored internal command/address signal ICAF < K > as one of the first write latch signal AP _ WR1, the first internal write latch signal IAP _ WR1, the second write latch signal AP _ WR2, and the second internal write latch signal IAP _ WR2 based on the first to fourth write input control signals WPIN <1:4> and the first to fourth internal write output control signals IWPOUT <1:4 >. The pipe circuit 5 may further store the internal command/address signal ICAF < K > based on the first and second read input control signals RPIN <1:2>, and may output the stored internal command/address signal ICAF < K > as the read latch signal AP _ RD or the internal read latch signal IAP _ RD based on the first and second read output control signals RPOUT <1:2> or the first and second internal read output control signals IRPOUT <1:2 >.
The pipe circuit 5 may include a first write pipe group 51, a second write pipe group 52, and a read pipe group 53.
The first write pipe set 51 may store the internal command/address signal ICAF < K > based on the first and second write input control signals WPIN <1:2> and may output the stored internal command/address signal ICAF < K > as the first write latch signal AP _ WR1 based on the first and second write output control signals WPOUT <1:2> or may output the stored internal command/address signal ICAF < K > as the first internal write latch signal IAP _ WR1 based on the first and second internal write output control signals IWPOUT <1:2 >. The configuration and operation of the first write pipe group 51 will be described more fully later with reference to fig. 8 and 9.
The second write pipe set 52 may store the internal command/address signal ICAF < K > based on the third and fourth write input control signals WPIN <3:4> and may output the stored internal command/address signal ICAF < K > as the second write latch signal AP _ WR2 based on the third and fourth write output control signals WPOUT <3:4> or may output the stored internal command/address signal ICAF < K > as the second internal write latch signal IAP _ WR2 based on the third and fourth internal write output control signals IWPOUT <3:4 >. The configuration and operation of the second write pipe set 52 will be described more fully later with reference to FIG. 10.
The read pipe group 53 may store the internal command/address signal ICAF < K > based on the first and second read input control signals RPIN <1:2> and may output the stored internal command/address signal ICAF < K > as the read latch signal AP _ RD based on the first and second read output control signals RPOUT <1:2> or may output the stored internal command/address signal ICAF < K > as the internal read latch signal IAP _ RD based on the first and second internal read output control signals IRPOUT <1:2 >. The configuration and operation of read pipe group 53 will be described more fully later with reference to FIG. 11.
The auto-precharge signal generation circuit 6 may generate the write auto-precharge signal or the read auto-precharge signal from the first write latch signal AP _ WR1, the first internal write latch signal IAP _ WR1, the second write latch signal AP _ WR2, the second internal write latch signal IAP _ WR2, the read latch signal AP _ RD, and the internal read latch signal IAP _ WR _ RD based on the write flag WTTF, the internal write flag IWTTF, the read flag RDTF, the internal read flag IRDTF, the operation mode signal 4BG, the first to fourth write output control signals WPOUT <1:4>, the first to fourth write output control signals IWPOUT <1:4>, the first to second read output control signals RPOUT <1:2>, the first to second internal read output control signals IRPOUT <1:2>, the first to second burst mode signal BL16, and the second to second burst mode signal BL32 The electrical signal AP _ RDE. The configuration and operation of the auto-precharge signal generation circuit 6 will be described more fully later with reference to fig. 12 to 15.
The auto-precharge control circuit 7 may perform an auto-precharge operation based on the write auto-precharge signal AP _ WRE, the read auto-precharge signal AP _ RDE, and the bank address BA <1: N >. If the write auto-precharge signal AP _ WRE is generated, the auto-precharge control circuit 7 may perform the auto-precharge operation after the write operation of the cell array selected by the bank address BA <1: N >. If the read auto-precharge signal AP _ RDE is generated, the auto-precharge control circuit 7 may perform an auto-precharge operation after a read operation of the cell array selected by the bank addresses BA <1: N >.
Referring to fig. 2, the write input control signal generation circuit 41 may include a write input delay circuit 211, a write input clock generation circuit 212, a first write input latch 213, a first write input control signal output circuit 214, a second write input latch 215, a second write input control signal output circuit 216, a third write input latch 217, a third write input control signal output circuit 218, a fourth write input latch 219, a fourth write input control signal output circuit 220, and a fifth write input latch 221.
The write input delay circuit 211 may delay the write signal EWT to generate a delayed write signal EWTd. The write input clock generation circuit 212 may generate the write input clock signal WICLK from the delayed write signal EWTd. The write input clock generation circuit 212 may delay the delayed write signal EWTd to generate the write input clock signal WICLK. The delay time of the write input delay circuit 211 for delaying the write signal EWT and the delay time of the write input clock generation circuit 212 for delaying the delayed write signal EWTd may be set differently according to embodiments. The write input clock signal WICLK may be generated after the delay times of the write input delay circuit 211 and the write input clock generation circuit 212 have elapsed from the time point at which the write signal EWT is generated.
The first write input latch 213 may be implemented using a D flip-flop having an output terminal Q initialized to have a logic "high" level if the reset signal RST is generated. The reset signal RST may be generated to include a pulse having a logic "high" level to perform an initialization operation. If the first write input control signal WPIN <1> is generated to have a logic "high" level by the write input clock signal WICLK generated for the first time after the initialization operation, the first write input latch 213 may latch a signal input through its input terminal D in synchronization with the write input clock signal WICLK to output the latched signal through the output terminal Q.
The first write input control signal output circuit 214 may be configured to perform a nand operation and an inversion operation. For example, the first write input control signal output circuit 214 may include a NAND gate NAND21 and an inverter IV21, and may perform a logical and operation based on the delayed write signal EWTd and a signal of the output terminal Q of the first write input latch 213 to generate the first write input control signal WPIN <1 >. The first write input control signal output circuit 214 may generate the first write input control signal WPIN <1> having a logic "high" level if the write input clock signal WICLK is generated for the first time after the initialization operation and the delayed write signal EWTd is generated to have a logic "high" level.
The second write input latch 215 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second write input control signal WPIN <2> is generated to have a logic "high" level by the write input clock signal WICLK generated for the second time after the initialization operation, the second write input latch 215 may latch a signal input through its input terminal D in synchronization with the write input clock signal WICLK to output the latched signal through the output terminal Q.
The second write input control signal output circuit 216 may be configured to perform a nand operation and an inversion operation. For example, the second write input control signal output circuit 216 may include a NAND gate NAND22 and an inverter IV22, and may perform a logical and operation based on the delayed write signal EWTd and a signal of the output terminal Q of the second write input latch 215 to generate the second write input control signal WPIN <2 >. If the write input clock signal WICLK is generated for the second time after the initialization operation and the delayed write signal EWTd is generated to have a logic "high" level, the second write input control signal output circuit 216 may generate the second write input control signal WPIN <2> having a logic "high" level.
The third write input latch 217 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the third write input control signal WPIN <3> is generated to have a logic "high" level by the write input clock signal WICLK generated for the third time after the initialization operation, the third write input latch 217 may latch a signal input through its input terminal D in synchronization with the write input clock signal WICLK to output the latched signal through the output terminal Q.
The third write input control signal output circuit 218 may be configured to perform a nand operation and an inversion operation. For example, the third write input control signal output circuit 218 may include a NAND gate NAND23 and an inverter IV23, and may perform a logical and operation of the delayed write signal EWTd and a signal of the output terminal Q of the third write input latch 217 to generate the third write input control signal WPIN <3 >. The third write input control signal output circuit 218 may generate the third write input control signal WPIN <3> having a logic "high" level if the write input clock signal WICLK is generated for a third time after the initialization operation and the delayed write signal EWTd is generated to have a logic "high" level.
The fourth write input latch 219 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the fourth write input control signal WPIN <4> is generated to have a logic "high" level by the write input clock signal WICLK generated fourth time after the initialization operation, the fourth write input latch 219 may latch a signal input through its input terminal D in synchronization with the write input clock signal WICLK to output the latched signal through the output terminal Q.
The fourth write input control signal output circuit 220 may be configured to perform a nand operation and an inversion operation. For example, the fourth write input control signal output circuit 220 may include a NAND gate NAND24 and an inverter IV24, and may perform a logical and operation of the delayed write signal EWTd and a signal of the output terminal Q of the fourth write input latch 219 to generate the fourth write input control signal WPIN <4 >. If the write input clock signal WICLK is generated for the fourth time after the initialization operation and the delayed write signal EWTd is generated to have a logic "high" level, the fourth write input control signal output circuit 220 may generate the fourth write input control signal WPIN <4> having a logic "high" level.
The fifth write-in latch 221 may be implemented using a D flip-flop having an output terminal Q initialized to have a logic "low" level if the reset signal RST is generated. A signal of the output terminal Q of the fifth write input latch 221 may be fed back to the input terminal D of the first write input latch 213.
The write input control signal generation circuit 41 may sequentially and repeatedly generate the first to fourth write input control signals WPIN <1:4> whenever the write signal EWT is generated. The write input control signal generation circuit 41 may generate a first write input control signal WPIN <1> if the write signal EWT is generated for the first time, a second write input control signal WPIN <2> if the write signal EWT is generated for the second time, a third write input control signal WPIN <3> if the write signal EWT is generated for the third time, a fourth write input control signal WPIN <4> if the write signal EWT is generated for the fourth time, and a first write input control signal WPIN <1> if the write signal EWT is generated for the fifth time, and so on.
Referring to fig. 3, the read input control signal generation circuit 42 may include a read input delay circuit 31, a read input clock generation circuit 32, a first read input latch 33, a first read input control signal output circuit 34, a second read input latch 35, a second read input control signal output circuit 36, and a third read input latch 37.
The read input delay circuit 31 may delay the read signal ERT to generate a delayed read signal ERTd. The read input clock generation circuit 32 may generate the read input clock signal RICLK from the delayed read signal ERTd. The read input clock generation circuit 32 may delay the delayed read signal ERTd to generate the read input clock signal RICLK. The delay time of the read input delay circuit 31 for delaying the read signal ERT and the delay time of the read input clock generation circuit 32 for delaying the delayed read signal ERTd may be set differently according to embodiments. The read input clock signal RICLK may be generated after the delay times of the read input delay circuit 31 and the read input clock generation circuit 32 have elapsed from the time point of generation of the read signal ERT.
The first read input latch 33 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "high" level if the reset signal RST is generated. If the first read input control signal RPIN <1> is generated to have a logic "high" level by the read input clock signal RICLK generated for the first time after the initialization operation, the first read input latch 33 may latch a signal input through its input terminal D in synchronization with the read input clock signal RICLK to output the latched signal through the output terminal Q.
The first read input control signal output circuit 34 may be configured to perform a nand operation and an inversion operation. For example, the first read input control signal output circuit 34 may include a NAND gate NAND31 and an inverter IV31, and may perform a logical and operation based on the delayed read signal ERTd and a signal of the output terminal Q of the first read input latch 33 to generate the first read input control signal RPIN <1 >. If the read input clock signal RICLK is generated for the first time after the initialization operation and the delayed read signal ERTd is generated to have a logic 'high' level, the first read input control signal output circuit 34 may generate the first read input control signal RPIN <1> having a logic 'high' level.
The second read input latch 35 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second read input control signal RPIN <2> is generated to have a logic "high" level by the read input clock signal RICLK generated for the second time after the initialization operation, the second read input latch 35 may latch a signal input through its input terminal D in synchronization with the read input clock signal RICLK to output the latched signal through the output terminal Q.
Second read input control signal output circuit 36 may be configured to perform a nand operation and an inversion operation. For example, the second read input control signal output circuit 36 may include a NAND gate NAND32 and an inverter IV32, and may perform a logical and operation based on the delayed read signal ERTd and a signal of the output terminal Q of the second read input latch 35 to generate the second read input control signal RPIN <2 >. If the read input clock signal RICLK is generated for the second time after the initialization operation and the delayed read signal ERTd is generated to have a logic "high" level, the second read input control signal output circuit 36 may generate the second read input control signal RPIN <2> having a logic "high" level.
The third read input latch 37 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. The signal at the output terminal Q of the third read input latch 37 may be fed back to the input terminal D of the first read input latch 33.
The read input control signal generation circuit 42 may alternately generate the first read input control signal and the second read input control signal RPIN <1:2> whenever the read signal ERT is generated. The read input control signal generation circuit 42 may generate the first read input control signal RPIN <1> if the read signal ERT is generated for the first time, the second read input control signal RPIN <2> if the read signal ERT is generated for the second time, the first read input control signal RPIN <1> if the read signal ERT is generated for the third time, and so on.
Referring to fig. 4, the write output control signal generation circuit 43 may include a write output delay circuit 411, a write output clock generation circuit 412, a first write output latch 413, a first write output control signal output circuit 414, a second write output latch 415, a second write output control signal output circuit 416, a third write output latch 417, a third write output control signal output circuit 418, a fourth write output latch 419, a fourth write output control signal output circuit 420, and a fifth write output latch 421.
The write output delay circuit 411 may delay the write flag WTTF to generate a delayed write flag WTTFd. The write output clock generation circuit 412 may generate the write output clock signal WOCLK from the delayed write flag WTTFd. The write output clock generation circuit 412 may delay the delayed write flag WTTFd to generate the write output clock signal WOCLK. The delay time of the write output delay circuit 411 for delaying the write flag WTTF and the delay time of the write output clock generation circuit 412 for delaying the delayed write flag WTTFd may be set differently according to the embodiment. The write output clock signal WOCLK may be generated after the delay times of the write output delay circuit 411 and the write output clock generation circuit 412 have elapsed from the point in time at which the write flag WTTF is generated.
The first write output latch 413 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "high" level if the reset signal RST is generated. If the first write output control signal WPOUT <1> is generated to have a logic "high" level by the write output clock signal WOCLK generated for the first time after the initialization operation, the first write output latch 413 may latch a signal input through its input terminal D in synchronization with the write output clock signal WOCLK to output the latched signal through the output terminal Q.
The first write output control signal output circuit 414 may be configured to perform a nand operation and an inversion operation. For example, the first write output control signal output circuit 414 may include a NAND gate NAND41 and an inverter IV41, and may perform a logical and operation based on the delayed write flag WTTFd and a signal of the output terminal Q of the first write output latch 413 to generate the first write output control signal WPOUT <1 >. If the write output clock signal WOCLK is generated for the first time after the initialization operation and the delayed write flag WTTFd is generated to have a logic "high" level, the first write output control signal output circuit 414 may generate the first write output control signal WPOUT <1> having a logic "high" level.
The second write output latch 415 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second write output control signal WPOUT <2> is generated to have a logic "high" level by the write output clock signal WOCLK generated for the second time after the initialization operation, the second write output latch 415 may latch a signal input through its input terminal D in synchronization with the write output clock signal WOCLK to output the latched signal through the output terminal Q.
The second write output control signal output circuit 416 may be configured to perform a nand operation and an inversion operation. For example, the second write output control signal output circuit 416 may include a NAND gate NAND42 and an inverter IV42, and may perform a logical and operation based on the delayed write flag WTTFd and a signal of the output terminal Q of the second write output latch 415 to generate the second write output control signal WPOUT <2 >. If the write output clock signal WOCLK is generated for the second time after the initialization operation and the delayed write flag WTTFd is generated to have a logic "high" level, the second write output control signal output circuit 416 may generate the second write output control signal WPOUT <2> having a logic "high" level.
The third write output latch 417 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the third write output control signal WPOUT <3> is generated to have a logic "high" level by the write output clock signal WOCLK generated for the third time after the initialization operation, the third write output latch 417 may latch a signal input through its input terminal D in synchronization with the write output clock signal WOCLK to output the latched signal through the output terminal Q.
The third write output control signal output circuit 418 may be configured to perform a nand operation and an inversion operation. For example, the third write output control signal output circuit 418 may include a NAND gate NAND43 and an inverter IV43, and may perform a logical and operation based on the delayed write flag WTTFd and a signal of the output terminal Q of the third write output latch 417 to generate the third write output control signal WPOUT <3 >. If the write output clock signal WOCLK is generated for the third time after the initialization operation and the delayed write flag WTTFd is generated to have a logic "high" level, the third write output control signal output circuit 418 may generate the third write output control signal WPOUT <3> having a logic "high" level.
The fourth write output latch 419 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the fourth write output control signal WPOUT <4> is generated to have a logic "high" level by the write output clock signal WOCLK generated for the fourth time after the initialization operation, the fourth write output latch 419 may latch a signal input through its input terminal D in synchronization with the write output clock signal WOCLK to output the latched signal through the output terminal Q.
The fourth write output control signal output circuit 420 may be configured to perform a nand operation and an inversion operation. For example, the fourth write output control signal output circuit 420 may include a NAND gate NAND44 and an inverter IV44, and may perform a logical and operation based on the delayed write flag WTTFd and a signal of the output terminal Q of the fourth write output latch 419 to generate the fourth write output control signal WPOUT <4 >. If the write output clock signal WOCLK is generated for the fourth time after the initialization operation and the delayed write flag WTTFd is generated to have a logic "high" level, the fourth write output control signal output circuit 420 may generate the fourth write output control signal WPOUT <4> having a logic "high" level.
The fifth write output latch 421 may be implemented using a D flip-flop having an output terminal Q initialized to have a logic "low" level if the reset signal RST is generated. The signal of the output terminal Q of the fifth write output latch 421 may be fed back to the input terminal D of the first write output latch 413.
The write output control signal generation circuit 43 may sequentially and repeatedly generate the first to fourth write output control signals WPOUT <1:4> whenever the write flag WTTF is generated. The write output control signal generation circuit 43 may generate the first write output control signal WPOUT <1> if the write flag WTTF is generated for the first time, the second write output control signal WPOUT <2> if the write flag WTTF is generated for the second time, the third write output control signal WPOUT <3> if the third write flag WTTF is generated, the fourth write output control signal WPOUT <4> if the fourth write flag WTTF is generated, and the first write output control signal WPOUT <1> if the fifth write flag WTTF is generated, and so on.
Referring to fig. 5, the internal write output control signal generation circuit 44 may include a selective write flag generation circuit 431, an internal write output delay circuit 432, an internal write output clock generation circuit 433, a write output signal generation circuit 434, a first internal write output latch 435, a first internal write output control signal output circuit 436, a second internal write output latch 437, a second internal write output control signal output circuit 438, a third internal write output latch 439, a third internal write output control signal output circuit 440, a fourth internal write output latch 441, a fourth internal write output control signal output circuit 442, and a fifth internal write output latch 443.
The selective write flag generation circuit 431 may be configured to perform an inversion operation. For example, the selective write flag generation circuit 431 may include inverters IV431 to IV 434. The inverter IV431 may invert the buffer operation mode signal 4BG to output an inverted buffer signal of the operation mode signal 4 BG. In the bank group mode, the operation mode signal 4BG may be set to have a logic "high" level. In the non-bank group mode, the inverter IV432 may invert the buffered write flag WTTF to output an inverted buffered signal of the write flag WTTF to the node nd 431. In the bank group mode, inverter IV433 may invert the buffered internal write flag IWTTF to output the inverted buffered signal of the internal write flag IWTTF to node nd 431. The inverter IV434 may invert the signal of the buffer node nd431 to output the inverted buffered signal of the node nd431 as the selective write flag SWTTF.
The internal write output delay circuit 432 may delay the select write flag SWTTF to generate a delayed select write flag SWTd. The internal write output clock generation circuit 433 may be implemented using a D flip-flop capable of generating the internal write output clock signal IWOCLK from the burst operation mode signal 4BG _ BL32 in synchronization with the delay selection write flag SWTd. If reset signal RST is generated, internal write output clock generation circuit 433 may initialize internal write output clock signal IWOCLK to a logic "low" level. If a write operation is performed with the burst length set to '32' in the bank group mode, the burst operation mode signal 4BG _ BL32 may be set to have a logic "high" level. The write output signal generation circuit 434 may generate the write output signal WEX if the delay selection write flag SWTd is generated. The write output signal generation circuit 434 may delay the delay selection write flag SWTd to generate the write output signal WEX.
The first internal write output latch 435 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "high" level if the reset signal RST is generated. If the first internal write output control signal IWPOUT <1> is generated to have a logic "high" level by the internal write output clock signal IWOCLK generated for the first time after the initialization operation, the first internal write output latch 435 may latch a signal input through its input terminal D in synchronization with the internal write output clock signal IWOCLK to output the latched signal through the output terminal Q.
The first internal write output control signal output circuit 436 may be configured to perform a nand operation and an inversion operation. For example, the first internal write output control signal output circuit 436 may include a NAND gate NAND441 and an inverter IV441, and may perform a logical and operation based on the delay selection write flag SWTd, the write output signal WEX, and a signal of the output terminal Q of the first internal write output latch 435 to generate the first internal write output control signal IWPOUT <1 >. If the internal write output clock signal IWOCLK is generated for the first time after the initialization operation, and both the delay selection write flag SWTd and the write output signal WEX are generated to have a logic "high" level, the first internal write output control signal output circuit 436 may generate the first internal write output control signal IWPOUT <1> having a logic "high" level.
The second internal write output latch 437 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second internal write output control signal IWPOUT <2> is generated to have a logic "high" level by the internal write output clock signal IWOCLK generated for the second time after the initialization operation, the second internal write output latch 437 may latch a signal input through its input terminal D in synchronization with the internal write output clock signal IWOCLK to output the latched signal through the output terminal Q.
The second internal write output control signal output circuit 438 may be configured to perform a nand operation and an inversion operation. For example, the second internal write output control signal output circuit 438 may include a NAND gate NAND442 and an inverter IV442, and may perform a logical and operation based on the delay selection write flag SWTd, the write output signal WEX, and a signal of the output terminal Q of the second internal write output latch 437 to generate the second internal write output control signal IWPOUT <2 >. If the internal write output clock signal IWOCLK is generated a second time after the initialization operation and both the delay selection write flag SWTd and the write output signal WEX are generated to have a logic "high" level, the second internal write output control signal output circuit 438 may generate the second internal write output control signal IWPOUT <2> having a logic "high" level.
The third internal write output latch 439 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the third internal write output control signal IWPOUT <3> is generated to have a logic "high" level by the internal write output clock signal IWOCLK generated a third time after the initialization operation, the third internal write output latch 439 may latch a signal input through its input terminal D in synchronization with the internal write output clock signal IWOCLK to output the latched signal through the output terminal Q.
The third internal write output control signal output circuit 440 may be configured to perform a nand operation and an inversion operation. For example, the third internal write output control signal output circuit 440 may include a NAND gate NAND443 and an inverter IV443, and may perform a logical and operation based on the delay selection write flag SWTd, the write output signal WEX, and a signal of the output terminal Q of the third internal write output latch 439 to generate the third internal write output control signal IWPOUT <3 >. If the internal write output clock signal IWOCLK is generated for the third time after the initialization operation and both the delay selection write flag SWTd and the write output signal WEX are generated to have a logic "high" level, the third internal write output control signal output circuit 440 may generate the third internal write output control signal IWPOUT <3> having a logic "high" level.
The fourth internal write output latch 441 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the fourth internal write output control signal IWPOUT <4> is generated to have a logic "high" level by the internal write output clock signal IWOCLK generated for the fourth time after the initialization operation, the fourth internal write output latch 441 may latch a signal input through its input terminal D in synchronization with the internal write output clock signal IWOCLK to output the latched signal through the output terminal Q.
The fourth internal write output control signal output circuit 442 may be configured to perform a nand operation and an inversion operation. For example, the fourth internal write output control signal output circuit 442 may include a NAND gate NAND444 and an inverter IV444, and may perform a logical and operation based on the delay selection write flag SWTd, the write output signal WEX, and a signal of the output terminal Q of the fourth internal write output latch 441 to generate the fourth internal write output control signal IWPOUT <4 >. If the internal write output clock signal IWOCLK is generated a fourth time after the initialization operation, and both the delay selection write flag SWTd and the write output signal WEX are generated to have a logic "high" level, the fourth internal write output control signal output circuit 442 may generate the fourth internal write output control signal IWPOUT <4> having a logic "high" level.
The fifth internal write output latch 443 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. The signal at the output terminal Q of the fifth internal write-output latch 443 may be fed back to the input terminal D of the first internal write-output latch 435.
The internal write output control signal generation circuit 44 may sequentially and repeatedly generate the first to fourth internal write output control signals IWPOUT <1:4> whenever the internal write flag IWTTF is generated for a write operation performed with the burst length set to '32' in the bank group mode. For example, if the internal write flag IWTTF is generated for the first time, internal write output control signal generation circuit 44 may generate a first internal write output control signal IWPOUT <1>, if the internal write flag IWTTF is generated for the second time, internal write output control signal generation circuit 44 may generate a second internal write output control signal IWPOUT <2>, if the internal write flag IWTTF is generated for the third time, internal write output control signal generation circuit 44 may generate a third internal write output control signal IWPOUT <3>, if the internal write flag IWTTF is generated for the fourth time, internal write output control signal generation circuit 44 may generate a fourth internal write output control signal IWPOUT <4>, and if the internal write flag IWTTF is generated for the fifth time, internal write output control signal generation circuit 44 may generate a first internal write output control signal IWPOUT <1>, and so on.
Referring to fig. 6, the read output control signal generation circuit 45 may include a read output delay circuit 451, a read output clock generation circuit 452, a first read output latch 453, a first read output control signal output circuit 454, a second read output latch 455, a second read output control signal output circuit 456, and a third read output latch 457.
The read output delay circuit 451 may delay the read flag RDTF to generate a delayed read flag RDTFd. The read output clock generation circuit 452 may generate the read output clock signal ROCLK from the delayed read flag RDTFd. The read output clock generation circuit 452 may delay the delayed read flag RDTFd to generate the read output clock signal ROCLK. The delay time of the read output delay circuit 451 for delaying the read flag RDTF and the delay time of the read output clock generation circuit 452 for delaying the delayed read flag RDTFd may be set differently according to the embodiment. The read output clock signal ROCLK may be generated after the delay times of the read output delay circuit 451 and the read output clock generation circuit 452 have elapsed from the time point at which the read flag RDTF is generated.
The first read output latch 453 may be implemented using a D flip-flop having an output terminal Q initialized to have a logic "high" level if the reset signal RST is generated. If the first read output control signal RPOUT <1> is generated to have a logic "high" level by the read output clock signal ROCLK generated for the first time after the initialization operation, the first read output latch 453 may latch a signal input through an input terminal D thereof in synchronization with the read output clock signal ROCLK to output the latched signal through an output terminal Q.
The first read output control signal output circuit 454 may be configured to perform a nand operation and an inversion operation. For example, the first read output control signal output circuit 454 may include a NAND gate NAND451 and an inverter IV451, and may perform a logical and operation based on the delayed read flag RDTFd and a signal of the output terminal Q of the first read output latch 453 to generate the first read output control signal RPOUT <1 >. If the read output clock signal ROCLK is generated for the first time after the initialization operation and the delayed read flag RDTFd is generated to have a logic "high" level, the first read output control signal output circuit 454 may generate the first read output control signal RPOUT <1> having a logic "high" level.
The second read output latch 455 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second read output control signal RPOUT <2> is generated to have a logic "high" level by the read output clock signal ROCLK generated for the second time after the initialization operation, the second read output latch 455 may latch a signal input through its input terminal D in synchronization with the read output clock signal ROCLK to output the latched signal through the output terminal Q.
The second read output control signal output circuit 456 may be configured to perform a nand operation and an inversion operation. For example, the second read output control signal output circuit 456 may include a NAND gate NAND452 and an inverter IV452, and may perform a logical and operation based on the delayed read flag RDTFd and a signal of the output terminal Q of the second read output latch 455 to generate the second read output control signal RPOUT <2 >. If the read output clock signal ROCLK is generated a second time after the initialization operation and the delayed read flag RDTFd is generated to have a logic "high" level, the second read output control signal output circuit 456 may generate the second read output control signal RPOUT <2> having a logic "high" level.
The third read output latch 457 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. A signal of the output terminal Q of the third read output latch 457 may be fed back to the input terminal D of the first read output latch 453.
The read output control signal generation circuit 45 may alternately generate the first read output control signal and the second read output control signal RPOUT <1:2> whenever the read flag RDTF is generated. The read output control signal generation circuit 45 may generate the first read output control signal RPOUT <1> if the read flag RDTF is generated for the first time, the read output control signal generation circuit 45 may generate the second read output control signal RPOUT <2> if the read flag RDTF is generated for the second time, the read output control signal generation circuit 45 may generate the first read output control signal RPOUT <1> if the read flag RDTF is generated for the third time, and so on.
Referring to fig. 7, the internal read output control signal generation circuit 46 may include a selective read flag generation circuit 461, an internal read output delay circuit 462, an internal read output clock generation circuit 463, a read output signal generation circuit 464, a first internal read output latch 465, a first internal read output control signal output circuit 466, a second internal read output latch 467, a second internal read output control signal output circuit 468, and a third internal read output latch 469.
The selective reading flag generation circuit 461 may be configured to perform an inversion operation. For example, the selective read flag generation circuit 461 may include inverters IV461 to IV 464. The inverter IV461 may invert the buffered operation mode signal 4BG to output an inverted buffered signal of the operation mode signal 4 BG. In the non-bank group mode, the inverter IV462 may invert the buffered read flag RDTF to output an inverted buffered signal of the read flag RDTF to the node nd 461. In the bank group mode, the inverter IV463 may invert the buffered internal read flag IRDTF to output an inverted buffered signal of the internal read flag IRDTF to the node nd 461. The inverter IV464 may invert the signal of the buffer node nd461 to output the inverted buffered signal of the node nd461 as the selected read flag SRDTF.
The internal read output delay circuit 462 may delay the selected read flag SRDTF to generate a delayed selected read flag SRTd. The internal read output clock generation circuit 463 may be implemented using a D flip-flop capable of generating the internal read output clock signal IROCLK from the burst operation mode signal 4BG _ BL32 in synchronization with the delay selection read flag SRTd. The internal read output clock signal IROCLK may be initialized to a logic "low" level by the internal read output clock generation circuit 463 if the reset signal RST is generated. If a read operation is performed with the burst length set to '32' in the bank group mode, the burst operation mode signal 4BG _ BL32 may be set to have a logic "high" level. The read output signal generation circuit 464 may generate the read output signal REX if the delay selection read flag SRTd is generated. The read output signal generation circuit 464 may delay the delay selection read flag SRTd to generate the read output signal REX.
The first internal read output latch 465 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "high" level if the reset signal RST is generated. If the first internal read output control signal IRPOUT <1> is generated to have a logic "high" level by the internal read output clock signal IROCLK generated for the first time after the initialization operation, the first internal read output latch 465 may latch a signal input through the input terminal D thereof in synchronization with the internal read output clock signal IROCLK to output the latched signal through the output terminal Q.
The first internal read output control signal output circuit 466 may be configured to perform a nand operation and an inversion operation. For example, the first internal read output control signal output circuit 466 may include a NAND gate NAND471 and an inverter IV471, and may perform a logical and operation of delaying the selection read flag SRTd, the read output signal REX, and a signal of the output terminal Q of the first internal read output latch 465 to generate the first internal read output control signal IRPOUT <1 >. If the internal read output clock signal IROCLK is generated for the first time after the initialization operation and both the delayed select read flag SRTd and the read output signal REX are generated to have a logic "high" level, the first internal read output control signal output circuit 466 may generate the first internal read output control signal IRPOUT <1> having a logic "high" level.
The second internal read output latch 467 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. If the second internal read output control signal IRPOUT <2> is generated to have a logic "high" level by the internal read output clock signal IROCLK generated for the second time after the initialization operation, the second internal read output latch 467 may latch a signal input through its input terminal D in synchronization with the internal read output clock signal IROCLK to output the latched signal through the output terminal Q. The second internal read output control signal output circuit 468 may include a NAND gate NAND481 and an inverter IV481, and may perform a logical and operation of delaying the selection read flag SRTd, the read output signal REX, and a signal of the output terminal Q of the second internal read output latch 467 to generate the second internal read output control signal IRPOUT <2 >. If the internal read output clock signal IROCLK is generated a second time after the initialization operation and the delayed selection read flag SRTd and the read output signal REX are generated to have a logic "high" level, the second internal read output control signal output circuit 468 may generate the second internal read output control signal IRPOUT <2> having a logic "high" level.
The third internal read output latch 469 may be implemented using a D flip-flop having an output terminal Q that is initialized to have a logic "low" level if the reset signal RST is generated. The signal at the output terminal Q of the third internal read output latch 469 may be fed back to the input terminal D of the first internal read output latch 465.
The internal read output control signal generation circuit 46 may alternately generate the first internal read output control signal and the second internal read output control signal IRPOUT <1:2> whenever the internal read flag IRDTF is generated for a read operation performed with the burst length set to '32' in the bank group mode. For example, if the internal read flag IRDTF is generated a first time, the internal read output control signal generation circuit 46 may generate a first internal read output control signal IRPOUT <1>, if the internal read flag IRDTF is generated a second time, the internal read output control signal generation circuit 46 may generate a second internal read output control signal IRPOUT <2>, and if the internal read flag IRDTF is generated a third time, the internal read output control signal generation circuit 46 may generate the first internal read output control signal IRPOUT <1>, and so on.
Referring to fig. 8, the first write pipe group 51 may include a first write pipe 511 and a second write pipe 512.
The first write pipe 511 may store the internal command/address signal ICAF < K > based on the first write input control signal WPIN <1> and may output the stored internal command/address signal ICAF < K > as the first write latch signal AP _ WR1 based on the first write output control signal WPOUT <1> or may output the stored internal command/address signal ICAF < K > as the first internal write latch signal IAP _ WR1 based on the first internal write output control signal wppout <1 >.
The second write pipe 512 may store the internal command/address signal ICAF < K > based on the second write input control signal WPIN <2> and may output the stored internal command/address signal ICAF < K > as the first write latch signal AP _ WR1 based on the second write output control signal WPOUT <2> or may output the stored internal command/address signal ICAF < K > as the first internal write latch signal IAP _ WR1 based on the second internal write output control signal wppout <2 >.
Referring to fig. 9, the first write pipe 511 may include a write input inverting circuit 514, a write input control signal latch circuit 515, and a write select output circuit 516. The write input inverting circuit 514 may be configured to perform an inverting operation. For example, the write input inverting circuit 514 may include an inverter IV51 and may invert the buffered first write input control signal WPIN <1> to generate the first inverted write input control signal WPINB <1 >. The write input control signal latch circuit 515 may be configured to perform an inversion operation. For example, the write input control signal latch circuit 515 may include inverters IV 52-IV 57. Without generating the first write input control signal WPIN <1>, the inverter IV52 may invert the buffered internal command/address signal ICAF < K > to output an inverted buffered signal of the internal command/address signal ICAF < K > to the node nd 51. The inverter IV53 may invert the signal of the buffer node nd51 to output an inverted buffered signal of the node nd51 to the node nd 52. If the first write input control signal WPIN <1> is generated to have a logic "high" level, the inverter IV54 may invert the signal of the buffer node nd52 to output an inverted buffered signal of the node nd52 to the node nd 51. If the first write input control signal WPIN <1> is generated to have a logic "high" level, the inverter IV55 may invert the signal of the buffer node nd52 to output an inverted buffered signal of the node nd52 to the node nd 53. The inverter IV56 may invert the signal of the buffer node nd53 to output an inverted buffered signal of the node nd53 to the node nd 54. Without generating the first write input control signal WPIN <1>, the inverter IV57 may invert the signal of the buffer node nd54 to output an inverted buffered signal of the node nd54 to the node nd 53. The write select output circuit 516 may be configured to perform an inversion operation. For example, the write select output circuit 516 may include inverters IV 571-IV 574. The inverter IV571 may invert the buffer signal of the first write output control signal WPOUT <1> to output the inverted buffer signal of the first write output control signal WPOUT <1 >. If the first write output control signal WPOUT <1> is generated to have a logic "low" level, the inverter IV572 may invert the signal of the buffer node nd54 to output an inverted buffered signal of the node nd54 as the first write latch signal AP _ WR 1. Inverter IV573 may invert the buffered first internal write output control signal IWPOUT <1> to output an inverted buffered signal of the first internal write output control signal IWPOUT <1 >. If the first internal write output control signal IWPOUT <1> is generated to have a logic "low" level, the inverter IV574 may invert the signal of the buffer node nd54 to output an inverted buffered signal of the node nd54 as the first internal write latch signal IAP _ WR 1.
Referring to fig. 10, the second write pipe group 52 may include a third write pipe 521 and a fourth write pipe 522.
The third write pipe 521 may store the internal command/address signal ICAF < K > based on the third write input control signal WPIN <3> and may output the stored internal command/address signal ICAF < K > as the second write latch signal AP _ WR2 based on the third write output control signal WPOUT <3> or may output the stored internal command/address signal ICAF < K > as the second internal write latch signal IAP _ WR2 based on the third internal write output control signal WPPOIWPOUT <3 >.
The fourth write pipe 522 may store the internal command/address signal ICAF < K > based on the fourth write input control signal WPIN <4> and may output the stored internal command/address signal ICAF < K > as the second write latch signal AP _ WR2 based on the fourth write output control signal WPOUT <4> or may output the stored internal command/address signal ICAF < K > as the second internal write latch signal IAP _ WR2 based on the fourth internal write output control signal WPPOIWPOUT <4 >.
Referring to fig. 11, the read tunnel group 53 may include a first read tunnel 531 and a second read tunnel 532.
The first read pipe 531 may store the internal command/address signal ICAF < K > based on the first read input control signal RPIN <1>, and may output the stored internal command/address signal ICAF < K > as the read latch signal AP _ RD based on the first read output control signal RPOUT <1> or may output the stored internal command/address signal ICAF < K > as the internal read latch signal IAP _ RD based on the first internal read output control signal IRPOUT <1 >.
The second read pipe 532 may store the internal command/address signal ICAF < K > based on the second read input control signal RPIN <2> and may output the stored internal command/address signal ICAF < K > as the read latch signal AP _ RD based on the second read output control signal RPOUT <2> or may output the stored internal command/address signal ICAF < K > as the internal read latch signal IAP _ RD based on the second internal read output control signal IRPOUT <2 >.
Referring to fig. 12, the auto-precharge signal generation circuit 6 may include a selection signal generation circuit 61, a precharge signal generation circuit 62, and an auto-precharge signal output circuit 63.
The selection signal generation circuit 61 may generate the first write selection signal and the second write selection signal WSEL <1:2> based on the first to fourth write output control signals WPOUT <1:4 >. The selection signal generation circuit 61 may generate the first write selection signal WSEL <1> if the first write output control signal WPOUT <1> or the second write output control signal WPOUT <2> is generated. The selection signal generation circuit 61 may generate the second write selection signal WSEL <2> if the third write output control signal WPOUT <3> or the fourth write output control signal WPOUT <4> is generated.
The selection signal generation circuit 61 may generate the first internal write selection signal and the second internal write selection signal IWSEL <1:2> based on the first to fourth internal write output control signals IWPOUT <1:4 >. If the first internal write output control signal IWPOUT <1> or the second internal write output control signal IWPOUT <2> is generated, the selection signal generation circuit 61 may generate the first internal write selection signal IWSEL <1 >. If either the third internal write output control signal IWPOUT <3> or the fourth internal write output control signal IWPOUT <4> is generated, the selection signal generation circuit 61 may generate the second internal write selection signal IWSEL <2 >.
The selection signal generation circuit 61 may generate the read selection signal RSEL based on the first read output control signal and the second read output control signal RPOUT <1:2 >. The selection signal generation circuit 61 may generate the read selection signal RSEL if the first read output control signal RPOUT <1> or the second read output control signal RPOUT <2> is generated.
The selection signal generation circuit 61 may generate the internal read selection signal IRSEL based on the first and second internal read output control signals IRPOUT <1:2 >. The selection signal generation circuit 61 may generate the internal read selection signal IRSEL if the first internal read output control signal IRPOUT <1> or the second internal read output control signal IRPOUT <2> is generated.
The precharge signal generation circuit 62 may generate the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE from the first write latch signal AP _ WR1, the first internal write latch signal IAP _ WR1, the second write latch signal AP _ WR2, the second internal write latch signal IAP _ WR2, the read latch signal AP _ RD, or the internal read latch signal IAP _ RD based on the first and second write select signals WSEL <1:2>, the first and second internal write select signals IWSEL <1:2>, the read select signal RSEL, the internal read select signal IRSEL, and the operation mode signal 4 BG.
If the first write select signal WSEL <1> is generated in the non-bank group mode, the precharge signal generation circuit 62 may buffer the first write latch signal AP _ WR1 to generate the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE. If the first write select signal WSEL <1> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the first write latch signal AP _ WR1 to generate the precharge signal AP _ PRE.
If the second write select signal WSEL <2> is generated in the non-bank group mode, the precharge signal generation circuit 62 may buffer the second write latch signal AP _ WR2 to generate the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE. If the second write select signal WSEL <2> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the second write latch signal AP _ WR2 to generate the precharge signal AP _ PRE.
If the read select signal RSEL is generated in the non-bank group mode, the precharge signal generation circuit 62 may buffer the read latch signal AP _ RD to generate the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE. If the read select signal RSEL is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the read latch signal AP _ RD to generate the precharge signal AP _ PRE.
If the first internal write select signal IWSEL <1> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the first internal write latch signal IAP _ WR1 to generate the internal precharge signal IAP _ PRE. If the second internal write select signal IWSEL <2> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the second internal write latch signal IAP _ WR2 to generate the internal precharge signal IAP _ PRE. If the internal read select signal IRSEL is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the internal read latch signal IAP _ RD to generate the internal precharge signal IAP _ PRE.
The auto-precharge signal output circuit 63 may generate the write auto-precharge signal AP _ WRE and the read auto-precharge signal AP _ RDE from the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE based on the write flag WTTF, the internal write flag IWTTF, the read flag RDTF, the internal read flag IRDTF, the first burst mode signal BL16, and the second burst mode signal BL 32.
If the write flag WTTF is generated, the auto-precharge signal output circuit 63 may generate a write auto-precharge signal AP _ WRE from the precharge signal AP _ PRE. The auto-precharge signal output circuit 63 may generate the read auto-precharge signal AP _ RDE from the precharge signal AP _ PRE if the read flag RDTF is generated. If the internal write flag IWTTF is generated, the auto-precharge signal output circuit 63 may generate a write auto-precharge signal AP _ WRE from the internal precharge signal IAP _ PRE. The auto-precharge signal output circuit 63 may generate a read auto-precharge signal AP _ RDE from the internal precharge signal IAP _ PRE if the internal read flag IRDTF is generated.
Referring to fig. 13, the selection signal generation circuit 61 may be configured to perform an or operation. For example, the selection signal generation circuit 61 may include OR gates OR611 to OR 616. The OR gate OR611 may perform a logical OR operation of the first and second write output control signals WPOUT <1:2> to generate the first write select signal WSEL <1 >. The OR gate OR611 may generate the first write select signal WSEL <1> if the first write output control signal WPOUT <1> OR the second write output control signal WPOUT <2> is generated. The OR gate OR612 may perform a logical OR operation based on the third and fourth write output control signals WPOUT <3:4> to generate the second write select signal WSEL <2 >. The OR gate OR612 may generate the second write select signal WSEL <2> if the third write output control signal WPOUT <3> OR the fourth write output control signal WPOUT <4> is generated. The OR gate OR613 may perform a logical OR operation based on the first and second read output control signals RPOUT <1:2> to generate the read select signal RSEL. The OR gate OR613 may generate the read select signal RSEL if the first read output control signal RPOUT <1> OR the second read output control signal RPOUT <2> is generated. OR gate OR614 may perform a logical OR operation based on the first and second internal write output control signals IWPOUT <1:2> to generate a first internal write select signal IWSEL <1 >. OR gate OR614 may generate first internal write select signal IWSEL <1> if either first internal write output control signal IWPOUT <1> OR second internal write output control signal IWPOUT <2> is generated. OR gate OR615 may perform a logical OR operation based on the third internal write output control signal and the fourth internal write output control signal IWPOUT <3:4> to generate a second internal write select signal IWSEL <2 >. OR gate OR615 may generate second internal write select signal IWSEL <2> if either third internal write output control signal IWPOUT <3> OR fourth internal write output control signal IWPOUT <4> is generated. The OR gate OR616 may perform a logical OR operation based on the first and second internal read output control signals IRPOUT <1:2> to generate the internal read select signal IRSEL. The OR gate OR616 may generate the internal read select signal IRSEL if the first internal read output control signal IRPOUT <1> OR the second internal read output control signal IRPOUT <2> is generated.
Referring to fig. 14, the precharge signal generation circuit 62 may include a write latch signal selection input circuit 71, a read latch signal selection input circuit 72, an internal write latch signal selection input circuit 73, an internal read latch signal selection input circuit 74, a selection latch circuit 75, and a pre-output circuit 76.
The write latch signal selection input circuit 71 may be configured to perform an inversion operation. For example, the write latch signal selection input circuit 71 may include inverters IV711 to IV 718. The inverter IV711 may invert-buffer the first write latch signal AP _ WR1 input through the node nd711 to output an inverted-buffered signal of the first write latch signal AP _ WR1 to the node nd 712. The inverter IV712 may invert the signal of the buffer node nd712 to output the inverted buffered signal of the node nd712 to the node nd 711. The inverter IV713 may invert the buffered first write select signal WSEL <1> to output an inverted buffered signal of the first write select signal WSEL <1 >. If the first write select signal WSEL <1> is generated to have a logic "high" level, the inverter IV714 may invert the signal of the buffer node nd712 to output the inverted buffered signal of the node nd712 to the node nd 71. The inverter IV715 may invert-buffer the second write latch signal AP _ WR2 input via the node nd713 to output an inverted-buffered signal of the second write latch signal AP _ WR2 to the node nd 714. The inverter IV716 may invert the signal of the buffer node nd714 to output the inverted buffered signal of the node nd714 to the node nd 713. Inverter IV717 may invert the buffered second write select signal WSEL <2> to output an inverted buffered signal of the second write select signal WSEL <2 >. If the second write select signal WSEL <2> is generated to have a logic "high" level, the inverter IV718 may invert the signal of the buffer node nd714 to output an inverted buffered signal of the node nd714 to the node nd 71. The write latch signal selection input circuit 71 may buffer the first write latch signal AP _ WR1 to output the buffered signal of the first write latch signal AP _ WR1 to the node nd71 if the first write select signal WSEL <1> is generated, and the write latch signal selection input circuit 71 may buffer the second write latch signal AP _ WR2 to output the buffered signal of the second write latch signal AP _ WR2 to the node nd71 if the second write select signal WSEL <2> is generated.
The read latch signal selection input circuit 72 may be configured to perform an inversion operation. For example, the read latch signal selection input circuit 72 may include inverters IV721 to IV 724. The inverter IV721 may invert the read latch signal AP _ RD input through the node nd721 to output an inverted buffered signal of the read latch signal AP _ RD to the node nd 722. The inverter IV722 may invert the signal of the buffer node nd722 to output the inverted buffered signal of the node nd722 to the node nd 721. The inverter IV723 may invert the buffered read select signal RSEL to output an inverted buffered signal of the read select signal RSEL. If the read select signal RSEL is generated to have a logic "high" level, the inverter IV724 may invert the signal of the buffer node nd722 to output the inverted buffered signal of the node nd722 to the node nd 71. The read latch signal selection input circuit 72 may buffer the read latch signal AP _ RD to output a buffered signal of the read latch signal AP _ RD to the node nd71 if the read select signal RSEL is generated.
The internal write latch signal selection input circuit 73 may be configured to perform an inversion operation. For example, the internal write latch signal selection input circuit 73 may include inverters IV731 to IV 738. The inverter IV731 may invert-buffer the first internal write latch signal IAP _ WR1 input via the node nd731 to output an inverted-buffered signal of the first internal write latch signal IAP _ WR1 to the node nd 732. The inverter IV732 may invert the signal of the buffer node nd732 to output an inverted buffered signal of the node nd732 to the node nd 731. Inverter IV733 may invert the buffered first internal write select signal IWSEL <1> to output an inverted buffered signal of the first internal write select signal IWSEL <1 >. If the first internal write select signal IWSEL <1> is generated to have a logic "high" level, the inverter IV734 may invert the signal of the buffer node nd732 to output an inverted buffered signal of the node nd732 to the node nd 72. The inverter IV735 may invert-buffer the second internal write latch signal IAP _ WR2 input via the node nd733 to output an inverted buffered signal of the second internal write latch signal IAP _ WR2 to the node nd 734. The inverter IV736 may invert the signal of the buffer node nd734 to output the inverted buffered signal of the node nd734 to the node nd 733. The inverter IV737 may invert the buffered second internal write select signal IWSEL <2> to output an inverted buffered signal of the second internal write select signal IWSEL <2 >. If the second internal write select signal IWSEL <2> is generated to have a logic "high" level, the inverter IV738 may invert the signal of the buffer node nd734 to output an inverted buffered signal of the node nd734 to the node nd 72. The internal write latch signal selection input circuit 73 may buffer the first internal write latch signal IAP _ WR1 to output the buffered signal of the first internal write latch signal IAP _ WR1 to the node nd72 if the first internal write select signal IWSEL <1> is generated, and the internal write latch signal selection input circuit 73 may buffer the second internal write latch signal IAP _ WR2 to output the buffered signal of the second internal write latch signal IAP _ WR2 to the node nd72 if the second internal write select signal IWSEL <2> is generated.
The internal read latch signal selection input circuit 74 may be configured to perform an inversion operation. For example, the internal read latch signal selection input circuit 74 may include inverters IV741 to IV 744. The inverter IV741 may invert-buffer the internal read latch signal IAP _ RD input via the node nd741 to output an inverted-buffered signal of the internal read latch signal IAP _ RD to the node nd 742. The inverter IV742 may invert the signal of the buffer node nd742 to output the inverted buffered signal of the node nd742 to the node nd 741. The inverter IV743 may invert the buffered internal read select signal IRSEL to output an inverted buffered signal of the internal read select signal IRSEL. If the internal read select signal IRSEL is generated to have a logic "high" level, the inverter IV744 may invert the signal of the buffer node nd742 to output an inverted buffered signal of the node nd742 to the node nd 72. The internal read latch signal selection input circuit 74 may buffer the internal read latch signal IAP _ RD to output the buffered signal of the internal read latch signal IAP _ RD to the node nd72 if the internal read select signal IRSEL is generated.
The selection latch circuit 75 may be configured to perform a nor operation and an inversion operation. For example, the selection latch circuit 75 may include NOR gates NOR751 and NOR752 and inverters IV751 and IV 752. The NOR gate NOR751 may perform a logical NOR operation based on the signal of the node nd71 and the reset signal RST. The inverter IV751 may invert the output signal of the NOR gate NOR751 to output an inverted buffered signal of the output signal of the NOR gate NOR751 to the node nd 71. The NOR gate NOR752 may perform a logical NOR operation based on the signal of the node nd72 and the reset signal RST. The inverter IV752 may invert the output signal of the NOR gate NOR752 to output the inverted buffered signal of the output signal of the NOR gate NOR752 to the node nd 72. The selection latch circuit 75 may latch the signals of the nodes nd71 and nd72, and may buffer the signals of the nodes nd71 and nd72 to output one of the buffered signals of the nodes nd71 and nd72 as the precharge signal AP _ PRE.
The pre-output circuit 76 may be configured to perform an inversion operation. For example, the pre-output circuit 76 may include inverters IV761 to IV 768. The inverters IV761, IV762, and IV763 may be coupled in series, and may invert the output signal of the NOR gate NOR751 to output an inverted buffer signal of the output signal of the NOR gate NOR751 as the precharge signal AP _ PRE. The inverter IV764 may invert the buffered operation mode signal 4BG to output an inverted buffered signal of the operation mode signal 4 BG. In the bank group mode, the inverter IV765 may invert the output signal of the NOR gate NOR752 to output an inverted buffered signal of the output signal of the NOR gate NOR 752. In the non-bank group mode, the inverter IV766 may invert the output signal of the NOR gate NOR751 to output an inverted buffered signal of the output signal of the NOR gate NOR 751. The inverters IV767 and IV768 may be coupled in series, and may buffer the output signal of the inverter IV765 or IV766 to output the buffered signal of the output signal of the inverter IV765 or IV766 as the internal precharge signal IAP _ PRE.
If the first internal write select signal IWSEL <1> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the first internal write latch signal IAP _ WR1 to generate the internal precharge signal IAP _ PRE. If the second internal write select signal IWSEL <2> is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the second internal write latch signal IAP _ WR2 to generate the internal precharge signal IAP _ PRE. If the internal read select signal IRSEL is generated in the bank group mode, the precharge signal generation circuit 62 may buffer the internal read latch signal IAP _ RD to generate the internal precharge signal IAP _ PRE.
Referring to fig. 15, the auto-precharge signal output circuit 63 may include a pre-pulse generating circuit 631, a pulse generating circuit 632, a latch pulse generating circuit 633, and a latch pulse synthesizing circuit 634.
The pre-pulse generating circuit 631 may include a write pre-pulse generating circuit 641, a read pre-pulse generating circuit 642, an internal write pre-pulse generating circuit 643, and an internal read pre-pulse generating circuit 644. The write pre-pulse generating circuit 641 may generate a write pre-pulse WPRE from the write flag WTTF. The write pre-pulse generating circuit 641 may delay the write flag WTTF to generate the write pre-pulse WPRE. The delay time of the write pre-pulse generating circuit 641 for delaying the write flag WTTF may be set differently according to the embodiment. The read pre-pulse generating circuit 642 may generate the read pre-pulse RPRE from the read flag RDTF. The read pre-pulse generating circuit 642 may delay the read flag RDTF to generate the read pre-pulse RPRE. The delay time of the read pre-pulse generation circuit 642 for delaying the read flag RDTF may be set differently according to embodiments. The internal write pre-pulse generation circuit 643 may generate an internal write pre-pulse IWPRE from the internal write flag IWTTF. The internal write pre-pulse generation circuit 643 may delay the internal write flag IWTTF to generate the internal write pre-pulse IWPRE. The delay time of the internal write pre-pulse generation circuit 643 for delaying the internal write flag IWTTF may be set differently according to the embodiment. The internal read pre-pulse generating circuit 644 may generate an internal read pre-pulse IRPRE from the internal read flag IRDTF. The internal read pre-pulse generation circuit 644 may delay the internal read flag IRDTF to generate the internal read pre-pulse IRPRE. The delay time of the internal read pre-pulse generation circuit 644 for delaying the internal read flag IRDTF may be set differently according to the embodiment.
The pulse generation circuit 632 may be configured to perform an and operation. For example, the pre-pulse generating circuit 632 may include AND gates AND631 to AND 634. The AND gate AND631 may perform a logical AND operation based on the write pre-pulse WPRE AND the first burst mode signal BL16 to generate the write pulse WP. If the write pre-pulse WPRE is generated with the burst length set to '16', the AND gate AND631 may generate the write pulse WP. The AND gate AND632 may perform a logical AND operation based on the read pre-pulse RPRE AND the first burst mode signal BL16 to generate the read pulse RP. If the read pre-pulse RPRE is generated with the burst length set to '16', the AND gate AND632 may generate the read pulse RP. The AND gate AND633 may perform a logical AND operation based on the internal write pre-pulse IWPRE AND the second burst mode signal BL32 to generate the internal write pulse IWP. If the internal write pre-pulse IWPRE is generated with the burst length set to '32', the AND gate AND633 may generate the internal write pulse IWP. The AND gate AND634 may perform a logical AND operation based on the internal read pre-pulse IRPRE AND the second burst mode signal BL32 to generate the internal read pulse IRP. If the internal read pre-pulse IRPRE is generated with the burst length set to '32', the AND gate AND634 may generate the internal read pulse IRP.
The latch pulse generating circuit 633 may include a write latch pulse generating circuit 651, a read latch pulse generating circuit 652, an internal write latch pulse generating circuit 653, and an internal read latch pulse generating circuit 654. If the write pulse WP is generated, the write latch pulse generation circuit 651 may latch the precharge signal AP _ PRE to output a latch signal of the precharge signal AP _ PRE as the write latch pulse WLAP. The read latch pulse generation circuit 652 may latch the precharge signal AP _ PRE to output a latch signal of the precharge signal AP _ PRE as the read latch pulse RLAP if the read pulse RP is generated. The internal write latch pulse generation circuit 653, if the internal write pulse IWP is generated, may latch the internal precharge signal IAP _ PRE to output a latch signal of the internal precharge signal IAP _ PRE as the internal write latch pulse IWLAP. The internal read latch pulse generation circuit 654 may latch the internal precharge signal IAP _ PRE to output a latch signal of the internal precharge signal IAP _ PRE as the internal read latch pulse IRLAP if the internal read pulse IRP is generated. Each of the write latch pulse generation circuit 651, the read latch pulse generation circuit 652, the internal write latch pulse generation circuit 653, and the internal read latch pulse generation circuit 654 may be implemented using a D flip-flop.
The latch pulse synthesizing circuit 634 may be configured to perform an and operation. For example, the latch pulse synthesizing circuit 634 may include OR gates OR631 and OR 632. The OR gate OR631 may perform a logical OR operation based on the write latch pulse WLAP and the internal write latch pulse IWLAP to generate the write auto-precharge signal AP _ WRE. The OR gate OR631 may generate the write auto-precharge signal AP _ WRE if the write latch pulse WLAP OR the internal write latch pulse IWLAP is generated. The OR gate OR632 may perform a logical OR operation based on the read latch pulse RLAP and the internal read latch pulse IRLAP to generate the read auto-precharge signal AP _ RDE. The OR gate OR632 may generate the read auto-precharge signal AP _ RDE if the read latch pulse RLAP OR the internal read latch pulse IRLAP is generated.
The operation of the semiconductor device having the above-described configuration will be described hereinafter with reference to fig. 16 in conjunction with an example in which the write auto-precharge signal AP _ WRE is generated for the purpose of performing the auto-precharge operation in the case where the write operation with the burst length of '32' and the write operation with the burst length of '16' are sequentially performed in the bank group mode.
The write signal EWT may be generated for the first time if a first command WR/BL32_ BG1 is input to the semiconductor device 1 via the command/address signals CA <1: L > to perform a write operation of the first bank group with a burst length of '32' in the bank group mode. The write signal EWT may be generated a second time if a second command WR/BL16_ BG2 is input to the semiconductor device 1 via the command/address signals CA <1: L > to perform a write operation of the second bank group with the burst length '16' in the bank group mode. When the write signal EWT is generated for the first time, the internal command/address signal ICAF < K > may be generated to have a logic "high" level for performing an auto-precharge operation.
The write flag WTTF may be generated by delaying the write signal EWT by the first write delay period td1 set by the write latency. The internal write flag IWTTF may be generated by delaying the write signal EWT by a second write delay period td2 set by the write latency and the burst length.
The first write input control signal WPIN <1> may be generated if the write signal EWT is generated for the first time, and the second write input control signal WPIN <2> may be generated if the write signal EWT is generated for the second time. The first write output control signal WPOUT <1> may be generated if the write flag WTTF is generated for the first time, and the second write output control signal WPOUT <2> may be generated if the write flag WTTF is generated for the second time. If the internal write flag IWTTF is generated for the first time, a first internal write output control signal IWPOUT <1> may be generated. Even when the internal write flag IWTTF is generated for the second time, the second internal write output control signal IWPOUT <2> is not generated. This is because the second-generated internal write flag IWTTF is generated by a write operation performed in the bank group at the burst length '16'.
The internal command/address signal ICAF < K > having a logic "high" level may be latched by the first write input control signal WPIN <1>, a latch signal of the internal command/address signal ICAF < K > may be output as the precharge signal AP _ PRE by the first write output control signal WPOUT <1>, and a latch signal of the internal command/address signal ICAF < K > may be output as the internal precharge signal IAP _ PRE by the first internal write output control signal IWPOUT <1 >. Since the write operation performed with the burst length '32' in the bank group mode generates the precharge signal AP _ PRE and the internal precharge signal IAP _ PRE, the internal write latch pulse IWLAP can be generated to have a logic "high" level by the internal precharge signal IAP _ PRE without generating the write latch pulse WLAP by the precharge signal AP _ PRE. Accordingly, an auto-precharge operation may be performed after a write operation is performed with a burst length of "32" in the bank group mode.
As described above, the semiconductor device according to one embodiment can be controlled in the following manner: when a write operation is performed with a burst length of '32' in the bank group mode, a first column operation for first 16-bit data is performed before a bubble period, and an auto-precharge operation is performed after the bubble period by an internal precharge signal IAP _ PRE generated after a second column operation for second 16-bit data is performed. Accordingly, when a write operation set at the burst length '16' and a write operation set at the burst length '32' are sequentially performed in the bank group mode, it may be determined that an auto-precharge operation of a write operation performed at the burst length '32' is performed or not performed after a bubble period after it is determined that an auto-precharge operation for a write operation performed at the burst length '16' is performed or not performed during the bubble period. That is, according to the embodiment, when the write operation is continuously performed, the execution or non-execution of the auto-precharge operation can be controlled in consideration of the burst length and the bubble period.
The semiconductor device 1 described with reference to fig. 1 to 16 may be applied to an electronic system including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, as shown in fig. 17, an electronic system 1000 according to an embodiment may include a data storage circuit 1001, a memory controller 1002, a buffer memory 1003, and an input/output (I/O) interface 1004.
The data storage circuit 1001 may store data output from the memory controller 1002 or may read and output the stored data to the memory controller 1002 according to a control signal output from the memory controller 1002. The data storage circuit 1001 may include the semiconductor device shown in fig. 1. Meanwhile, the data storage circuit 1001 may include a nonvolatile memory capable of retaining its stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), or the like.
The memory controller 1002 may receive a command output from an external device (e.g., a host device) via the I/O interface 1004 and may decode the command output from the host device to control an operation for inputting data into the data storage circuit 1001 or the buffer memory 1003 or an operation for outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 17 shows the memory controller 1002 having a single block, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 and another controller for controlling the buffer memory 1003 including a volatile memory.
The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002. That is, the buffer memory 1003 can temporarily store data output from the data storage circuit 1001 or data to be input to the data storage circuit 1001. The buffer memory 1003 may store data output from the memory controller 1002 according to a control signal. The buffer memory 1003 can read out data stored therein and output the data to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM). The buffer memory 1003 may include the semiconductor device 1 shown in fig. 1.
The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and data provided from an external device (i.e., a host) via the I/O interface 1004 and may output data output from the memory controller 1002 to the external device (i.e., the host) via the I/O interface 1004. That is, electronic system 1000 may communicate with a host via I/O interfaces 1004. The I/O interface 1004 may include any of a variety of interface protocols, such as Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-E), serial attached SCSI (sas), serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).
The electronic system 1000 may be used as an external storage device or an auxiliary storage device for a host. The electronic system 1000 may include a Solid State Disk (SSD), a USB memory, a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), or a Compact Flash (CF) card, etc.

Claims (20)

1. A semiconductor device, comprising:
an input/output I/O control signal generation circuit configured to generate an input control signal, an output control signal, and an internal output control signal based on a bank mode and a burst length;
a pipe circuit configured to latch an internal command/address signal based on the input control signal, and configured to: outputting the latched internal command/address signal as a latch signal based on the output control signal, and outputting the latched internal command/address signal as an internal latch signal based on the internal output control signal; and
an auto-precharge signal generation circuit configured to generate an auto-precharge signal from the latch signal and the internal latch signal based on the bank mode and the burst length.
2. The semiconductor device according to claim 1, wherein the input/output I/O control signal generation circuit generates the internal output control signal in a bank group mode, performs column operations before and after a bubble period in the bank group mode, and
wherein the bubble period is a duration of other column operations.
3. The semiconductor device according to claim 2, wherein the input/output I/O control signal generation circuit inhibits generation of the internal output control signal if the following operations are performed without the bubble period in the bank group mode and in a non-bank group mode.
4. The semiconductor device according to claim 1, wherein the input/output I/O control signal generation circuit generates a write input control signal based on a write signal, and generates a write output control signal and an internal write output control signal based on a write flag and an internal write flag.
5. The semiconductor device as set forth in claim 4,
wherein the write flag is generated by delaying the write signal by a period set according to a write latency; and
wherein the internal write flag is generated by delaying the write flag by a period set according to the burst length.
6. The semiconductor device as set forth in claim 4,
wherein the write input control signal comprises a first write input control signal and a second write input control signal; and
wherein the input/output I/O control signal generation circuit comprises a write-in control signal generation circuit configured to: the first write input control signal and the second write input control signal are sequentially and repeatedly generated whenever the write signal is generated.
7. The semiconductor device as set forth in claim 4,
wherein the write output control signal comprises a first write output control signal and a second write output control signal; and
wherein the input/output I/O control signal generation circuit comprises a write output control signal generation circuit configured to: the first write output control signal and the second write output control signal are sequentially and repeatedly generated whenever the write flag is generated.
8. The semiconductor device as set forth in claim 4,
wherein the internal write output control signals include a first internal write output control signal and a second internal write output control signal; and
wherein the input/output I/O control signal generation circuit comprises an internal write output control signal generation circuit configured to: sequentially and repeatedly generating the first internal write output control signal and the second internal write output control signal whenever the internal write flag is generated in the bank group mode in which column operations are performed before and after a bubble period, and
wherein the bubble period is a duration of other column operations.
9. The semiconductor device as set forth in claim 4,
wherein the pipeline circuitry is synchronized with the write input control signal to latch the internal command/address signal; and
wherein the pipe circuit is synchronized with the write output control signal to output the latched internal command/address signal as a write latch signal, and the pipe circuit is synchronized with the internal write output control signal to output the latched internal command/address signal as an internal write latch signal.
10. The semiconductor device according to claim 9, wherein the auto-precharge signal generation circuit generates a write auto-precharge signal based on the internal write latch signal in a bank group mode in which column operations are performed before and after a bubble period.
11. The semiconductor device of claim 10, wherein the auto-precharge signal generation circuit generates the write auto-precharge signal based on the write latch signal if the semiconductor device leaves the bank group mode.
12. The semiconductor device of claim 9, wherein the auto-precharge signal generation circuit comprises:
a selection signal generation circuit configured to generate a write selection signal and an internal write selection signal based on the write output control signal and the internal write output control signal;
a precharge signal generation circuit configured to generate a precharge signal and an internal precharge signal from the write latch signal and the internal write latch signal based on the write select signal and the internal write select signal; and
an auto-precharge signal output circuit configured to generate a write auto-precharge signal based on the precharge signal and the internal precharge signal.
13. The semiconductor device as set forth in claim 1,
wherein the input control signal comprises a read input control signal;
wherein the output control signal comprises a read output control signal;
wherein the internal output control signal comprises an internal read output control signal; and
wherein the input/output I/O control signal generation circuit generates the read input control signal based on a read signal, and generates the read output control signal and the internal read output control signal based on a read flag and an internal read flag.
14. The semiconductor device as set forth in claim 13,
wherein the pipeline circuitry is synchronized with the read input control signal to latch the internal command/address signal; and
wherein the pipe circuit is synchronized with the read output control signal to output the latched internal command/address signal as a read latch signal, and the pipe circuit is synchronized with the internal read output control signal to output the latched internal command/address signal as an internal read latch signal.
15. The semiconductor device as set forth in claim 14,
wherein the auto-precharge signal generation circuit generates a read auto-precharge signal based on the internal read latch signal in a bank group mode in which column operations are performed before and after a bubble period; and
wherein the auto-precharge signal generation circuit generates the read auto-precharge signal based on the read latch signal if the semiconductor device leaves the bank group mode.
16. A semiconductor device, comprising:
an input/output I/O control signal generation circuit configured to generate a write input control signal based on the write signal, and configured to generate a write output control signal and an internal write output control signal based on the write flag and the internal write flag;
a pipe circuit configured to be synchronized with the write input control signal to latch an internal command/address signal, and configured to be synchronized with the write output control signal to output the latched internal command/address signal as a write latch signal, and configured to be synchronized with the internal write output control signal to output the latched internal command/address signal as an internal write latch signal; and
an auto-precharge signal generation circuit configured to: generating a write auto-precharge signal based on the internal write latch signal in a bank group mode in which column operations are performed before and after a bubble period; and is configured to: generating the write auto-precharge signal based on the write latch signal when the semiconductor device transitions to a different bank mode.
17. The semiconductor device according to claim 16, wherein in the bank group mode, the input/output I/O control signal generation circuit generates the internal write output control signal, and
wherein the bubble period is a duration of other column operations.
18. The semiconductor device as set forth in claim 17,
wherein the internal write output control signals include a first internal write output control signal and a second internal write output control signal; and
wherein the input/output I/O control signal generation circuit comprises an internal write output control signal generation circuit configured to: the first internal write output control signal and the second internal write output control signal are sequentially and repeatedly generated whenever the internal write flag is generated.
19. The semiconductor device as set forth in claim 16,
wherein the input/output I/O control signal generation circuit generates a read input control signal based on the read signal and generates a read output control signal and an internal read output control signal based on the read flag and the internal read flag;
wherein the pipe circuit is synchronized with the read input control signal to latch the internal command/address signal, and is synchronized with the read output control signal to output the latched internal command/address signal as a read latch signal, and is synchronized with the internal read output control signal to output the latched internal command/address signal as an internal read latch signal; and
wherein the auto-precharge signal generation circuit generates a read auto-precharge signal based on the read latch signal and the internal read latch signal.
20. A semiconductor device, comprising:
an input/output I/O control signal generation circuit configured to generate a read input control signal based on the read signal and configured to generate a read output control signal and an internal read output control signal based on the read flag and the internal read flag;
a pipe circuit configured to be synchronized with the read input control signal to latch an internal command/address signal, and configured to be synchronized with the read output control signal to output the latched internal command/address signal as a read latch signal, and configured to be synchronized with the internal read output control signal to output the latched internal command/address signal as an internal read latch signal; and
an auto-precharge signal generation circuit configured to: generating a read auto-precharge signal based on the internal read latch signal in a bank group mode in which column operations are performed before and after a bubble period; and is configured to: generating the read auto-precharge signal based on the read latch signal if the semiconductor device is transitioned to a different bank mode.
CN201910796473.XA 2018-12-03 2019-08-27 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Active CN111261207B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180153937A KR102576767B1 (en) 2018-12-03 2018-12-03 Semiconductor device
KR10-2018-0153937 2018-12-03

Publications (2)

Publication Number Publication Date
CN111261207A true CN111261207A (en) 2020-06-09
CN111261207B CN111261207B (en) 2023-08-01

Family

ID=70850953

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910796473.XA Active CN111261207B (en) 2018-12-03 2019-08-27 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Country Status (3)

Country Link
US (1) US10734042B2 (en)
KR (1) KR102576767B1 (en)
CN (1) CN111261207B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210029614A (en) * 2019-09-06 2021-03-16 에스케이하이닉스 주식회사 Semiconductor device
KR20210079122A (en) * 2019-12-19 2021-06-29 에스케이하이닉스 주식회사 Semiconductor device
KR20220015218A (en) * 2020-07-30 2022-02-08 에스케이하이닉스 주식회사 Electronic device for executing auto-precharge operation
KR20220135980A (en) * 2021-03-31 2022-10-07 에스케이하이닉스 주식회사 Elecronic device for performing read operation using pipe circuit

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6055615A (en) * 1996-02-02 2000-04-25 Fujitsu Limited Pipeline memory access using DRAM with multiple independent banks
US20010021136A1 (en) * 2000-02-24 2001-09-13 Bae Yong Cheol Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods
US6801468B1 (en) * 2002-06-28 2004-10-05 Hynix Semiconductor Inc. Pseudo static RAM capable of performing page write mode
CN101060008A (en) * 2006-04-13 2007-10-24 海力士半导体有限公司 Multi-port memory device with serial input/output interface and control method thereof
US20100110813A1 (en) * 2008-11-06 2010-05-06 Micron Technology, Inc. Precharge control circuits and methods for memory having buffered write commands
US20110158020A1 (en) * 2009-12-30 2011-06-30 Hynix Semiconductor Inc. Circuit and method for controlling precharge in semiconductor memory apparatus
CN103198859A (en) * 2012-01-05 2013-07-10 爱思开海力士有限公司 Semiconductor system and command address setup/hold time control method
CN106856097A (en) * 2015-12-09 2017-06-16 爱思开海力士有限公司 Semiconductor devices and the semiconductor system including it
US20180018219A1 (en) * 2016-07-18 2018-01-18 SK Hynix Inc. Semiconductor devices and semiconductor systems
CN107919146A (en) * 2016-10-06 2018-04-17 爱思开海力士有限公司 Semiconductor devices
CN107919149A (en) * 2016-10-06 2018-04-17 爱思开海力士有限公司 Semiconductor devices
US9953688B1 (en) * 2016-10-04 2018-04-24 SK Hynix Inc. Precharge control device and semiconductor device including the same
CN110970070A (en) * 2018-10-01 2020-04-07 爱思开海力士有限公司 Semiconductor device with a plurality of transistors
CN111312308A (en) * 2018-12-11 2020-06-19 爱思开海力士有限公司 Semiconductor device and semiconductor system including the same
CN111383677A (en) * 2018-12-27 2020-07-07 爱思开海力士有限公司 Semiconductor device with a plurality of transistors

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443910B1 (en) * 2001-12-17 2004-08-09 삼성전자주식회사 Semiconductor memory device and method of accessing memory cells thereof
KR100892670B1 (en) * 2007-09-05 2009-04-15 주식회사 하이닉스반도체 Circuit for Controlling Precharge in Semiconductor Memory Apparatus
KR101226272B1 (en) * 2011-01-28 2013-01-25 에스케이하이닉스 주식회사 Auto precharge control circuit
KR20150089539A (en) * 2014-01-28 2015-08-05 에스케이하이닉스 주식회사 Precharge circuit and semiconductor memory apparatus using the same
KR102576763B1 (en) * 2016-03-17 2023-09-12 에스케이하이닉스 주식회사 Semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6055615A (en) * 1996-02-02 2000-04-25 Fujitsu Limited Pipeline memory access using DRAM with multiple independent banks
US20010021136A1 (en) * 2000-02-24 2001-09-13 Bae Yong Cheol Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods
US6801468B1 (en) * 2002-06-28 2004-10-05 Hynix Semiconductor Inc. Pseudo static RAM capable of performing page write mode
CN101060008A (en) * 2006-04-13 2007-10-24 海力士半导体有限公司 Multi-port memory device with serial input/output interface and control method thereof
US20100110813A1 (en) * 2008-11-06 2010-05-06 Micron Technology, Inc. Precharge control circuits and methods for memory having buffered write commands
US20110158020A1 (en) * 2009-12-30 2011-06-30 Hynix Semiconductor Inc. Circuit and method for controlling precharge in semiconductor memory apparatus
CN103198859A (en) * 2012-01-05 2013-07-10 爱思开海力士有限公司 Semiconductor system and command address setup/hold time control method
CN106856097A (en) * 2015-12-09 2017-06-16 爱思开海力士有限公司 Semiconductor devices and the semiconductor system including it
US20180018219A1 (en) * 2016-07-18 2018-01-18 SK Hynix Inc. Semiconductor devices and semiconductor systems
US9953688B1 (en) * 2016-10-04 2018-04-24 SK Hynix Inc. Precharge control device and semiconductor device including the same
CN107919146A (en) * 2016-10-06 2018-04-17 爱思开海力士有限公司 Semiconductor devices
CN107919149A (en) * 2016-10-06 2018-04-17 爱思开海力士有限公司 Semiconductor devices
CN110970070A (en) * 2018-10-01 2020-04-07 爱思开海力士有限公司 Semiconductor device with a plurality of transistors
CN111312308A (en) * 2018-12-11 2020-06-19 爱思开海力士有限公司 Semiconductor device and semiconductor system including the same
CN111383677A (en) * 2018-12-27 2020-07-07 爱思开海力士有限公司 Semiconductor device with a plurality of transistors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
N SATISH REDDY等: "ASIC implementation of high speed pipelined DDR SDRAM controller", 《INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES2014)》, pages 1 - 5 *
龚书涛: "自由立体显示硬件电路设计", 《中国优秀博硕士学位论文全文数据库(硕士)-信息科技辑》, no. 08, pages 135 - 69 *

Also Published As

Publication number Publication date
CN111261207B (en) 2023-08-01
KR20200067312A (en) 2020-06-12
US20200176035A1 (en) 2020-06-04
US10734042B2 (en) 2020-08-04
KR102576767B1 (en) 2023-09-12

Similar Documents

Publication Publication Date Title
CN111261207B (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
US10614871B2 (en) Semiconductor devices and semiconductor systems including the semiconductor devices
US11037609B2 (en) Semiconductor devices
CN106856097B (en) Semiconductor device and semiconductor system including the same
US11133054B2 (en) Semiconductor devices performing for column operation
CN110265073B (en) Semiconductor device with a plurality of transistors
CN110060714B (en) Semiconductor device and semiconductor system including the same
US10726889B2 (en) Semiconductor devices
KR102634962B1 (en) Semiconductor device
US9672884B1 (en) Semiconductor devices and semiconductor systems including the same
TWI775989B (en) Semiconductor devices
CN111199760B (en) Semiconductor device with a plurality of transistors
CN110196821B (en) Semiconductor device with a plurality of transistors
US10990522B2 (en) Electronic devices relating to a mode register information signal
US10559332B1 (en) Semiconductor devices
CN110459251B (en) Semiconductor device with a plurality of transistors
KR20180086817A (en) Semiconductor device
CN111696594A (en) Semiconductor device with a plurality of transistors

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant