CN111259609A - Optimal implication logic representation method of digital circuit logic function - Google Patents

Abstract

The invention discloses an optimal implication logic representation method of a digital circuit logic function, which comprises the steps of describing constraint conditions in implication logic according to defined Boolean variables, obtaining a constraint file represented by a conjunctive normal form CNF, setting different substantial implication logic operands, coding to obtain the CNF constraint file, transmitting the CNF constraint file to an SAT solver until the SAT solver finds Boolean variable assignment meeting the constraint conditions and returns a result SAT representing an optimal solution, thereby ensuring that the optimal implication logic representation form of the digital circuit logic function is found. The method optimizes 74 functions in all logic functions of the three-input digital circuit. The method can effectively reduce the number of nodes in a logic graph structure taking the essential inclusion as a basic operation set, can reduce the number of memristors when being applied to a memristor circuit, reduces the design cost of the memristor circuit, and enriches the research method of the essential inclusion logic in logic synthesis.

Description

Optimal implication logic representation method of digital circuit logic function

Technical Field

The invention relates to an implication logic representation method, in particular to an optimal implication logic representation method of a digital circuit logic function.

Background

In 1971, professor zeisure speculates a novel basic circuit element on the basis of circuit theory and symmetry principle, and the basic circuit element is called as a memristor, namely a resistor with memorability. Subsequently, HP (hewlett-packard) laboratories developed nano memristors in developing molecular-scale products to replace transistor switches, and implemented substantial implications (IMP, logical expressions) using the switching characteristics of dual memristors

And (4) logical operation. The essence implication is one of two-variable basic logic operations, and can also form the complete basis of the logic operation together with a logic constant "0", which means that any logic operation can be realized by using the implication operation. If the memory function of the memristor is combined with the memory function of the memristor, a new calculation paradigm can be formed, namely, calculation tasks are executed when data are stored in the same chip, and therefore dynamic switching between storage and calculation is achieved.

Researchers previously obtain the implication logic representation of a circuit by using an academic logic synthesis tool ABC, firstly read in a circuit AND store the circuit as a logic graph structure (AND-observer Graphs, AIG) with 'AND, INV' as a basic operation set, AND then obtain the logic graph structure with 'IMP' as the basic operation set through mapping. However, the results obtained with this approach are not optimal because of the redundancy that is created by the fact that a substantial implication logic is required to implement the inverter one-to-one mapping in the AIG.

Disclosure of Invention

The invention aims to solve the technical problem that aiming at the defects of the prior art, the optimal implication logic expression of the logic function of the digital circuit is solved by utilizing a precise synthesis algorithm based on the Boolean Satisfiability (SAT) to obtain the optimal implication logic expression method of the logic function of the digital circuit.

The technical scheme adopted by the invention for solving the technical problems is as follows: a method for optimally implied logic representation of a digital circuit logic function, comprising the steps of:

step ①, define Boolean variables

Three boolean variables are defined: x is the number of_it、g_hiAnd s_ijkWherein x is_itRepresenting the ith logic gate x in a digital circuit_iValues in the t-th row of the truth table of the logic function of the digital circuit; if logic gate x_iIs the h-th original output g in the digital circuit_hThen the boolean variable g_hiIs true, otherwise is false; if logic gate x_iAre each x_jAnd x_kAnd logic gate x_iPerforming a substantial implication logic operation, then the Boolean variable s_ijkIs true, otherwise is false; wherein, the value ranges of j and k are as follows: j is not less than 1<i,0≤k<i,j≠k；

Step ②, converting the constraint problem in the implication logic into conjunctive normal form formula, i.e. CNF formula

The logical graph structure containing only the "IMP" operation is taken as a logical function to represent, that is, in the logical graph structure taking the "IMP" as a basic operation set, except for an original input and an original output, each logic gate executes a substantial logic implication operation, so that the main constraint conditions in the implication logic are as follows:

in the formula (1), the symbol "→" represents a substantial logical operation, and the symbol

Indicates a strict equivalence; equation (1) shows if the logic gate x_iAre each x_jAnd x_kAnd logic gate x_iPerforming substantive implication logic operations, i.e. x_it＝x_jt→x_ktThen logic gate x_iValue of (a) x_itIs shown as

Converting the logic gate in the digital circuit into the description form of the CNF formula by using the Tseytin conversion method to obtain the logic gate

CNF formula (i):

(x_it→(x_jt→x_kt))∧((x_jt→x_kt)→x_it) (2)

in the formula (2), the symbol Λ represents the conjunctive value (i.e. logical and), and only the combination of the assignments in the truth table of the logic gate satisfies the formula (2), the combination formula (2) and the equation

Wherein the horizontal line above the boolean variable represents a logical negation, expanding equation (1) to:

converting the formula (3) into a CNF form, and use

Wherein the symbol "V-V" represents a logical OR, resulting in a constraint of the CNF form:

for the NOR logic gate contained in equation (4)

Defining a Boolean variable

Rewriting formula (4) as:

the NOR logic gate contained in the formula (4) is converted by using the Tseytin conversion method

Conversion to CNF form:

in summary, the primary CNF constraint equations for the substantive implication logic are:

to ensure the original output g in digital circuits_hMust be a logic gate x_iDefining a constraint formula as:

V_ig_hi(8)

"V" in the formula (8) represents a logical OR;

to ensure logic gates x in digital circuits_iMust have two inputs x_jAnd x_kDefining a constraint formula as follows:

V_j,ks_ijk(9)

in the formula (9), j is not equal to k, and j is not equal to 0;

to constrain the raw output values of a digital circuit to a specified logic gate, a constraint formula is defined as:

in the formula (10)

Represents a logical exclusive OR, (t)₁,…,t_n)₂Binary coding representing line number t in a truth table of logic functions of the digital circuit;

③, on the basis of the constraint condition obtained in step ②, firstly setting the number of required essential implication logic gates as 0, coding to obtain a CNF constraint file, and transmitting the obtained CNF constraint file to an SAT solver;

step ④, an SAT solver assigns values to the Boolean variables in the received CNF constraint file, and finds a group of Boolean variable assignments satisfying the formulas (7) to (10) of true values;

if the SAT solver finds such a set of Boolean variable assignments, the returned result is SAT, which means that the optimal solution is found; otherwise, adding 1 to the required substance inclusion logic gate number, recoding and solving until the result returned by the SAT solver is SAT.

Compared with the prior art, the invention has the following advantages:

1. the invention discloses an optimal implication logic expression method of a digital circuit logic function, which solves the optimal implication logic expression of the digital circuit logic function by utilizing a precise comprehensive algorithm based on Boolean Satisfiability (SAT). The method of the invention does not pass intermediate steps such as other logic structure transformation, etc., but directly obtains the optimal substance implication logic expression form from the logic function of the digital circuit. The method comprises the steps of describing constraint conditions in the implication logic according to defined Boolean variables, obtaining a constraint file expressed by a Conjunctive Normal Form (CNF), setting different substantial implication logic operands, coding to obtain the CNF constraint file, and transmitting the CNF constraint file to an SAT solver until the SAT solver finds Boolean variable assignment meeting the constraint conditions and returns a result SAT representing an optimal solution, so that the optimal implication logic expression Form of a digital circuit logic function is ensured to be found.

2. The method of the invention obtains an optimal implication logic representation form of the logic function of the digital circuit on the premise of ensuring the consistent functions of the logic functions of the digital circuit in the whole solving process. The method of the invention is applied to all three-input digital circuit logic functions (in common)

One function), 74 functions were optimized. The method of the invention can be effectively usedThe number of nodes in a logic graph structure with the essential implication as a basic operation set is reduced, when the method is applied to a memristor circuit, the number of memristors can be reduced, the design cost of the memristor circuit is reduced, and meanwhile, the research method of the essential implication logic in logic synthesis is enriched.

Drawings

FIG. 1 is a structure of a virtual implication logic circuit consisting of dual memristors;

FIG. 2 is a truth table of logic functions for a virtual implication logic circuit consisting of dual memristors;

FIG. 3 is a diagram of a logic graph structure with "IMP" as a basic operation set obtained by one-to-one mapping of AIG for an exemplary digital circuit;

fig. 4 is a logic graph structure with IMP as a basic operation set obtained by the method of the present invention for an exemplary digital circuit.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

Fig. 1 and 2 show a corresponding logic circuit structure and a truth table of logic functions of a substantially implicit logic circuit, respectively. Connecting a conventional resistor in series with two parallel memristors P, Q forms a digital switching circuit, the hybrid circuit may form a virtual implied operation. The initial resistance state of the memristor P, Q is the input of the logic gate, and the memristor Q is simultaneously used as the output of the logic gate through the voltage v_set、v_condThe combined action of the two signals is that the resistance state of the memristor Q is changed and serves as the output of the logic gate, and the final result is written into the memristor Q to be stored.

Using a Boolean expression as

For example, the truth table of the logic function of the digital circuit is (00001011)₂. For the digital circuit, fig. 3 is a schematic diagram of a conventional logic graph structure with IMP as a basic operation set obtained by AIG one-to-one mapping, and in fig. 3, all nodes are substantial implication logic gates (i.e., IMP nodes). FIG. 4 shows the present inventionThe method aims at the logic graph structure which is obtained by the digital circuit and takes IMP as a basic operation set. The method has the advantage that the optimal implication logic expression of the digital circuit logic function is obtained through an SAT-based precise comprehensive algorithm under the condition that the logic function of the digital circuit function is not changed.

For the Boolean expression of

The implementation process of solving the optimal implication logic expression of the logic function of the digital circuit by adopting the method comprises the following steps:

step ①, define Boolean variables

Three boolean variables are defined: x is the number of_it、g_hiAnd s_ijkThe original input to the digital circuit is x, as shown in FIG. 4₁(i.e., variables a), x₂(i.e., variables b), x₃(i.e., variable c) with the middle logic gate being x₄、x₅、x₆The original output is g₁；

Step ②, converting the constraint problem in the implication logic into conjunctive normal form formula, i.e. CNF formula

The constraint formula for the substantive implication logic is obtained as follows:

wherein i is more than or equal to 4 and less than or equal to 6, j is more than or equal to 1 and less than or equal to i, k is more than or equal to 0 and less than or equal to i, h is 1, and t is more than or equal to 0 and less than or equal to 7;

③, on the basis of the constraint condition obtained in step ②, firstly setting the number of required essential implication logic gates as 0, coding to obtain a CNF constraint file, and transmitting the obtained CNF constraint file to an SAT solver;

step ④, an SAT solver assigns values to Boolean variables in the received CNF constraint file, and finds a group of Boolean variable assignments which satisfy the constraint condition formula values of true;

if the SAT solver finds such a set of Boolean variable assignments, the returned result is SAT, which means that the optimal solution is found; otherwise, adding 1 to the required substance inclusion logic gate number, recoding and solving until the result returned by the SAT solver is SAT. The final results are shown in FIG. 4.

In the above simple digital circuit, the logic gate x₄、x₅、x₆All are true inclusion logic gates whose true inclusion table is:

t＝7 6 5 4 3 2 1 0

x_4t＝1 0 1 1 1 0 1 1

x_5t＝1 1 1 1 0 1 0 0

x_6t＝0 0 0 0 1 0 1 1

in the Boolean variable g_hiIn (g)₁₆Is 1, the remainder being g_hiIs 0; in the Boolean variable s_ijkIn, s₄₂₁、s₅₄₃、s₆₅₀Is 1, the remainder s_ijkIs 0.

For all three-input digital circuit logic functions (common)

Individual function) respectively adopting the method of the invention to obtain the optimal implied logic expression of the digital circuit logic function, and comparing the optimal implied logic expression with the existing AIG one-to-one mapping method, and the comparison result is shown in Table 1. In Table 1, N_img(f) The number of nodes in the logic graph structure of digital circuit logic function f obtained by the method of the present invention and using IMP as basic operation set, N_aig(f) The number of nodes of the logical graph structure which is transformed into AIG and then mapped into the basic operation set by IMP is represented. The second column in table 1 shows the same number of functions with the same number of nodes obtained in the two conversion modes, and the third column shows that the number of IMP nodes obtained by the method of the present invention is superior to that of functions obtained by the existing method, and the method of the present invention makes 74 functions out of 256 three-input digital circuit logic functions obtain the best substantial implication logic expression.

In FIG. 3N_aig((00001011)₂) (ii) 5; n in FIG. 4_img((00001011)₂) The number of nodes is reduced by two, 3. Accordingly, the present inventionThe method can effectively reduce the number of nodes in a logic graph structure taking IMP as a basic operation set to obtain the optimal inclusion logic expression of the logic function of the digital circuit, and when the method is applied to a memristor circuit, the cost can be reduced for the design of the memristor circuit, and meanwhile, the research method of the substantial inclusion logic in logic synthesis is enriched.

TABLE 1

Claims (1)

1. A method for optimally implied logic representation of a logic function of a digital circuit, comprising the steps of:

step ①, define Boolean variables

Three boolean variables are defined: x is the number of_it、g_hiAnd s_ijkWherein x is_itRepresenting the ith logic gate x in a digital circuit_iValues in the t-th row of the truth table of the logic function of the digital circuit; if logic gate x_iIs the h-th original output g in the digital circuit_hThen the boolean variable g_hiIs true, otherwise is false; if logic gate x_iAre each x_jAnd x_kAnd logic gate x_iPerforming a substantial implication logic operation, then the Boolean variable s_ijkIs true, otherwise is false; wherein, the value ranges of j and k are as follows: j is not less than 1<i,0≤k<i,j≠k；

Step ②, converting the constraint problem in the implication logic into conjunctive normal form formula, i.e. CNF formula

The logical graph structure containing only the "IMP" operation is taken as a logical function to represent, that is, in the logical graph structure taking the "IMP" as a basic operation set, except for an original input and an original output, each logic gate executes a substantial logic implication operation, so that the main constraint conditions in the implication logic are as follows:

in the formula (1), the symbol "→" represents a substantial logical operation, and the symbol

Indicates a strict equivalence; equation (1) shows if the logic gate x_iAre each x_jAnd x_kAnd logic gate x_iPerforming substantive implication logic operations, i.e. x_it＝x_jt→x_ktThen logic gate x_iValue of (a) x_itIs shown as

Converting the logic gate in the digital circuit into the description form of the CNF formula by using the Tseytin conversion method to obtain the logic gate

CNF formula (i):

(x_it→(x_jt→x_kt))∧((x_jt→x_kt)→x_it) (2)

in the formula (2), the symbol Λ represents the conjunctive value, and only the combination of the assigned values in the truth table of the logic gate satisfies the formula (2), the conjunctive formula (2) and the equation

Wherein the horizontal line above the boolean variable represents a logical negation, expanding equation (1) to:

converting the formula (3) into a CNF form, and use

Wherein the symbol "V-V" represents a logical OR, resulting in a constraint of the CNF form:

for the NOR logic gate contained in equation (4)

Defining a Boolean variable

Rewriting formula (4) as:

the NOR logic gate contained in the formula (4) is converted by using the Tseytin conversion method

Conversion to CNF form:

in summary, the primary CNF constraint equations for the substantive implication logic are:

to ensure the original output g in digital circuits_hMust be a logic gate x_iDefining a constraint formula as:

V_ig_hi(8)

"V" in the formula (8) represents a logical OR;

to ensure logic gates x in digital circuits_iMust have two inputs x_jAnd x_kDefining a constraint formula as follows:

V_j,ks_ijk(9)

in the formula (9), j is not equal to k, and j is not equal to 0;

to constrain the raw output values of a digital circuit to a specified logic gate, a constraint formula is defined as:

in the formula (10)

Represents a logical exclusive OR, (t)₁,…,t_n)₂Binary coding representing line number t in a truth table of logic functions of the digital circuit;

③, on the basis of the constraint condition obtained in step ②, firstly setting the number of required essential implication logic gates as 0, coding to obtain a CNF constraint file, and transmitting the obtained CNF constraint file to an SAT solver;

step ④, an SAT solver assigns values to the Boolean variables in the received CNF constraint file, and finds a group of Boolean variable assignments satisfying the formulas (7) to (10) of true values;

if the SAT solver finds such a set of Boolean variable assignments, the returned result is SAT, which means that the optimal solution is found; otherwise, adding 1 to the required substance inclusion logic gate number, recoding and solving until the result returned by the SAT solver is SAT.

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