CN111258731A - RISC-V based multi-core program scheduling system and method - Google Patents
RISC-V based multi-core program scheduling system and method Download PDFInfo
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Abstract
The invention provides a multi-core program scheduling system and method based on RISC-V, the said system includes RISC-V chip and software system, the said software system includes the operating system running on RISC-V chip and application program running on operating system; the RISC-V chip comprises a RISC-V quick response processor; the system also comprises a scheduler module for scheduling the system kernel and a configuration program module for performing quick response configuration on the program; the scheduling program module is used for detecting the configuration information of the program and distributing the program to the quick response processor for execution when the quick response configuration information is detected.
Description
Technical Field
The invention relates to the technical field of multi-core program scheduling of RISC-V processors, in particular to a multi-core program scheduling system and method based on RISC-V.
Background
RISC-V's multi-core program scheduling mechanism. The existing operating system adopts unified task scheduling, the multi-core program design adopts a parallel program design model to design an application program, and the application program is divided into a plurality of independent tasks. Both thread start-stop and thread context switch cause additional overhead, which results in more time consuming than a single thread. Meanwhile, for some programs requiring harsh response time, a unified scheduling mode is adopted on the multi-core processor, so that increasingly harsh response time requirements are difficult to meet.
The traditional task scheduling strategy can cause the interruption of tasks, cannot ensure the continuous execution, and cannot meet the requirements of the tasks with extremely high real-time requirements. Different tasks require different hardware resources and run on a general processor core, so that the efficiency cannot be improved, the effective adaptation of the tasks and the processor core cannot be realized, and the overall performance of the system cannot be effectively improved.
Disclosure of Invention
Aiming at the problems that the interruption of tasks can be caused by adopting the traditional task scheduling strategy, the continuous execution can not be ensured, and the requirements can not be met for the tasks with extremely high real-time requirements, the invention provides a RISC-V-based multi-core program scheduling system and method
The technical scheme of the invention is as follows:
on one hand, the technical scheme of the invention provides a multi-core program scheduling system based on RISC-V, which comprises a RISC-V chip and a software system, wherein the software system comprises an operating system running on the RISC-V chip and an application program running on the operating system;
the RISC-V chip comprises a RISC-V quick response processor;
the system also comprises a scheduler module for scheduling the system kernel and a configuration program module for performing quick response configuration on the program;
the scheduling program module is used for detecting the configuration information of the program and distributing the program to the quick response processor for execution when the quick response configuration information is detected.
The RISC-V chip is a chip using RISC-V as an instruction set, and the RISC-V general processor refers to a general processor based on RISC-V instructions and runs programs with more control logics. RISC-V fast response processors refer to general purpose processors based on RISC-V instructions, running a specified program. The RISC-V special processor is based on RISC-V instruction, adds general calculating unit in parallel, modifies processor instruction scheduling and transmitting module, is compatible with general processor instruction set, and runs program with more calculating logic.
Furthermore, the RISC-V chip also comprises a RISC-V general processor;
the dispatcher module is also used for detecting the configuration information of the program and distributing the program to the RISC-V general-purpose processor for execution when the quick response configuration information is not detected.
Furthermore, the RISC-V chip also comprises a RISC-V special processor which is based on RISC-V instructions, adds an arithmetic operation module in parallel, modifies the instruction scheduling of the processor and is compatible with a general processor instruction set.
Further, the arithmetic operation module comprises: a multiplication module, a division module and all modules for completing arithmetic operation in a general processor.
Further, the number of the RISC-V special processors in the system is several.
Furthermore, the dispatcher module is also used for analyzing the characteristics of the program and detecting the ratio of logic operation to arithmetic operation in the statistical program;
if the ratio of the logic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V general processor for execution;
and if the ratio of the arithmetic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V special processor for execution. If there is no other quick response program, the processor always executes the program; if other quick response programs need to be executed, the execution is carried out according to the time slice principle.
On the other hand, the technical scheme of the invention provides a multi-core program scheduling method based on RISC-V, which is applied to a multi-core program scheduling system based on RISC-V and comprises the following steps:
carrying out quick response configuration on the program according to the requirement;
detecting configuration information of a program;
if the quick response configuration information is detected, the program is distributed to a quick response processor for execution;
if no quick response configuration information is detected, the program is allocated to a RISC-V general purpose processor for execution or is dispatched to a RISC-V special purpose processor for execution according to the program characteristics.
Further, the step of distributing the program to the RISC-V general-purpose processor for execution or scheduling the program to the RISC-V specific-purpose processor for execution according to the program characteristic if the quick response configuration information is not detected includes the steps of:
analyzing the characteristics of the program and detecting the ratio of logic operation to arithmetic operation in the statistical program;
judging the ratio of the logic operation to the arithmetic operation;
if the ratio of the logic operation is larger than the set threshold value, the scheduling program module distributes the program to the RISC-V general processor for execution;
if the ratio of the arithmetic operation is larger than the set threshold value, the scheduling program module distributes the program to the RISC-V special processor for execution.
According to the technical scheme, the invention has the following advantages: the scheduling system of the invention effectively solves the following two problems: 1. the interruption caused by task scheduling can not ensure continuous execution, and for the tasks with extremely high real-time requirements, the existing task scheduling mechanism can not meet the requirements; 2. the general processor core can not effectively adapt to the tasks and the processor core, so that the overall performance of the system can not be effectively improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a system provided by an embodiment of the invention.
FIG. 2 is a schematic block diagram of a RISC-V chip according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a software system provided by an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is first necessary for those skilled in the art to know the manner of task scheduling includes: non-deprivation mode: the dispatcher, once assigned to a process, allows the handler to run until the process is completed or blocked by an event, assigning the handler to another process.
Deprivation mode: when a process is running, the system may deprive the processor that has been allocated to it of allocation to other processes based on some principle. The principle of deprivation is: priority principle, short process priority principle, time slice principle.
Example one
The technical scheme of the invention provides a multi-core program scheduling system based on RISC-V, which comprises a RISC-V chip and a software system, wherein the software system comprises an operating system running on the RISC-V chip and an application program running on the operating system;
the RISC-V chip comprises a RISC-V quick response processor;
the system also comprises a scheduler module for scheduling the system kernel and a configuration program module for performing quick response configuration on the program;
the scheduling program module is used for detecting the configuration information of the program and distributing the program to the quick response processor for execution when the quick response configuration information is detected. The RISC-V chip also comprises a RISC-V general processor; the dispatcher module is also used for detecting the configuration information of the program and distributing the program to the RISC-V general-purpose processor for execution when the quick response configuration information is not detected. The RISC-V chip also comprises a RISC-V special processor which is based on RISC-V instructions, adds an arithmetic operation module in parallel, modifies the instruction scheduling of the processor and is compatible with a general processor instruction set. The arithmetic operation module comprises: a multiplication module, a division module and all modules for completing arithmetic operation in a general processor.
Task processing with extremely high real-time requirements: before the program is formally executed, in this embodiment, the configuration program module is a fast response program, the scheduler program module refers to a scheduling patch of the operating system in this embodiment, and the scheduler program module determines the configured related information, and if the program is configured as a fast response program, the program is allocated to a fast response processor for execution, and if the program is not configured as a fast response program, the program is allocated to a general-purpose processor for execution or is scheduled to a special-purpose processor for execution according to a program characteristic. If there is no other quick response program, the processor always executes the program; if other quick response programs need to be executed, the execution is carried out according to the time slice principle.
Example two
As shown in fig. 1-3, the technical solution of the present invention provides a RISC-V based multi-core program scheduling system, and the present embodiment takes Linux operating system as an example, and the differences from the first embodiment include:
the number of the RISC-V special processors in the system is several.
The scheduling program module is also used for analyzing the characteristics of the program and detecting the ratio of logic operation to arithmetic operation in the statistical program;
if the ratio of the logic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V general processor for execution;
and if the ratio of the arithmetic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V special processor for execution. If there is no other quick response program, the processor always executes the program; if other quick response programs need to be executed, the execution is carried out according to the time slice principle. Before the program is executed formally, the scheduler module analyzes the characteristics of the program, including the program 1-program n, and detects the ratio of logical operations to arithmetic operations in the statistical program, and also calculates the ratio of various operations in the arithmetic operations. The arithmetic operation module added in the RISC-V special processor of the invention comprises: multiplication (integer, floating point), division (integer, floating point) and all the module parts in the general-purpose processor which complete arithmetic operation.
EXAMPLE III
The technical scheme of the invention provides a multi-core program scheduling method based on RISC-V, which is applied to a multi-core program scheduling system based on RISC-V and comprises the following steps:
SS 1: carrying out quick response configuration on the program according to the requirement;
SS 2: detecting configuration information of a program; if the quick response configuration information is detected, go to step SS 3; if no quick response configuration information is detected, go to step SS 4;
SS 3: distributing the program to a quick response processor for execution;
SS 4: the program is distributed to a RISC-V general-purpose processor for execution or is scheduled to a RISC-V special-purpose processor for execution according to the program characteristics.
In step SS4, the steps of scheduling to the RISC-V dedicated processor for execution according to the program characteristics include:
SS 41: analyzing the characteristics of the program and detecting the ratio of logic operation to arithmetic operation in the statistical program;
SS 42: judging the ratio of the logic operation to the arithmetic operation; if the ratio of the logical operations is greater than the set threshold, go to step SS 43; if the ratio of the arithmetic operation is larger than the set threshold, executing step SS 44;
SS 43: the said dispatcher module distributes the program to RISC-V general processor to execute;
SS 44: the dispatcher module distributes the program to a RISC-V special processor for execution.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A multi-core program scheduling system based on RISC-V is characterized in that the system comprises a RISC-V chip and a software system, wherein the software system comprises an operating system running on the RISC-V chip and an application program running on the operating system;
the RISC-V chip comprises a RISC-V quick response processor;
the system also comprises a scheduler module for scheduling the system kernel and a configuration program module for performing quick response configuration on the program;
the scheduling program module is used for detecting the configuration information of the program and distributing the program to the quick response processor for execution when the quick response configuration information is detected.
2. A RISC-V based multi-core program scheduling system as claimed in claim 1, wherein said RISC-V chip further comprises a RISC-V general purpose processor;
the dispatcher module is also used for detecting the configuration information of the program and distributing the program to the RISC-V general-purpose processor for execution when the quick response configuration information is not detected.
3. A RISC-V based multi-core program scheduling system as claimed in claim 2, wherein said RISC-V chip further comprises a RISC-V dedicated processor, said RISC-V dedicated processor adds arithmetic operation modules in parallel based on RISC-V instructions, modifies processor instruction scheduling, and is compatible with general processor instruction set.
4. A RISC-V based multi-core program scheduling system as claimed in claim 3, wherein said arithmetic operation module comprises: a multiplication module, a division module and all modules for completing arithmetic operation in a general processor.
5. A RISC-V based multi-core program scheduling system as in claim 4, where the number of RISC-V specific processors in the system is several.
6. A RISC-V based multi-core program scheduling system as claimed in claim 4, wherein said scheduler module is further adapted to analyze the characteristics of the program and detect the ratio of logical operations to arithmetic operations in the statistical program;
if the ratio of the logic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V general processor for execution;
and if the ratio of the arithmetic operation is larger than the set threshold value, the scheduling program module is used for distributing the program to the RISC-V special processor for execution.
7. A multi-core program scheduling method based on RISC-V is applied to a multi-core program scheduling system based on RISC-V, and is characterized by comprising the following steps:
carrying out quick response configuration on the program according to the requirement;
detecting configuration information of a program;
if the quick response configuration information is detected, the program is distributed to a quick response processor for execution;
if no quick response configuration information is detected, the program is allocated to a RISC-V general purpose processor for execution or is dispatched to a RISC-V special purpose processor for execution according to the program characteristics.
8. A RISC-V based multi-core program scheduling method as claimed in claim 7, wherein said step of assigning the program to the RISC-V general purpose processor for execution or to the RISC-V specific processor for execution according to the program characteristics if the quick response configuration information is not detected, the step of scheduling to the RISC-V specific processor for execution according to the program characteristics comprises:
analyzing the characteristics of the program and detecting the ratio of logic operation to arithmetic operation in the statistical program;
judging the ratio of the logic operation to the arithmetic operation;
if the ratio of the logic operation is larger than the set threshold value, the scheduling program module distributes the program to the RISC-V general processor for execution;
if the ratio of the arithmetic operation is larger than the set threshold value, the scheduling program module distributes the program to the RISC-V special processor for execution.
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| CN106030538A (en) * | 2014-02-19 | 2016-10-12 | 华为技术有限公司 | System and method for isolating I/O execution via compiler and OS support |
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| CN110348249A (en) * | 2019-05-22 | 2019-10-18 | 上海埃络科技有限公司 | It is a kind of based on the processor structure calculated in memory |
| CN110443214A (en) * | 2019-08-12 | 2019-11-12 | 山东浪潮人工智能研究院有限公司 | A kind of recognition of face accelerating circuit system and accelerated method based on RISC-V |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106030538A (en) * | 2014-02-19 | 2016-10-12 | 华为技术有限公司 | System and method for isolating I/O execution via compiler and OS support |
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| CN110018848A (en) * | 2018-09-29 | 2019-07-16 | 安凯(广州)微电子技术有限公司 | A kind of mixing based on RISC-V is mixed to calculate system and method |
| CN110348249A (en) * | 2019-05-22 | 2019-10-18 | 上海埃络科技有限公司 | It is a kind of based on the processor structure calculated in memory |
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