CN111247646B

CN111247646B - Carrier with buffer layer and device and method for manufacturing device

Info

Publication number: CN111247646B
Application number: CN201880069371.1A
Authority: CN
Inventors: P.阿尔蒂里-韦马尔; I.诺伊德克; M.兹茨施佩格; S.格勒奇; H.科赫
Original assignee: Osram Oled GmbH
Current assignee: Osram Oled GmbH
Priority date: 2017-08-24
Filing date: 2018-07-23
Publication date: 2023-09-29
Anticipated expiration: 2038-07-23
Also published as: DE102017119344A1; US20200235271A1; US11450794B2; CN111247646A; WO2019037997A1

Abstract

A carrier (9) with a buffer layer (3) or a component (100), in particular with such a carrier, is described. The carrier is constructed of metal, wherein the buffer layer has a yield stress of at least 10MPa and at most 300MPa. In particular, the carrier has a base body (90) which is designed in terms of its material composition such that the yield stress of the base body is greater than the yield stress of the buffer layer. The component has, for example, a semiconductor chip (10) having a substrate (1) and a semiconductor body (2) arranged on the substrate, wherein the thermal expansion coefficient of the carrier is at least 1.5 times the thermal expansion coefficient of the substrate or of the semiconductor chip. The semiconductor chip is fixed on a mounting surface (94) of the carrier by means of a connection layer (4) such that the connection layer is arranged between the semiconductor chip and the buffer layer. A method for manufacturing such a device is also described.

Description

Carrier with buffer layer and device and method for manufacturing device

Technical Field

In particular, a carrier for an optoelectronic component is described. Furthermore, a device, in particular an optoelectronic device, having high mechanical stability is described. Furthermore, a method for manufacturing a device is described.

Background

In devices having a metal carrier (ein metallischer) fixed by means of a connecting layer) In the case of the above semiconductor chip, in the case of temperature fluctuations due to different thermal expansion coefficients, internal thermo-mechanical stresses often occur on the carrier side and the semiconductor chip side. Internal stresses may lead to damage, in particular to undesired deformations of the device or of the semiconductor chip or of the carrier, which deformations may lead to severe bending or mechanical breaks in the device and ultimately to peeling of the semiconductor chip from the carrier.

Disclosure of Invention

One task is to specify a temperature-stable carrier and a component with improved mechanical stability. Another object is to specify a simple and effective method for producing mechanically and thermally stable components.

According to at least one embodiment of the carrier, the carrier has a buffer layer and a matrix. The buffer layer is arranged in particular on the substrate. The carrier is in particular constructed as metal. A metal support is generally understood to be a support whose metal content is at least 50%, 60%, 70%, 80%, 90% or at least 95% of the total weight and/or volume of the support. The substrate is formed, for example, from or consists of a first metal. The buffer layer may be formed of or consist of a second metal. In particular, the first metal is different from the second metal, for example in terms of yield stress.

According to at least one embodiment of the carrier, the carrier is a printed circuit board. The matrix of the carrier may form a metal core, for example forming a lead frame or lead frames of a printed circuit board. In addition to the base body, the carrier may also have a molded body, in particular an electrically insulating molded body, which in particular shapes the base body (umformen). The carrier may have conductor tracks, which are arranged, for example, on a mounting surface. For example, the carrier is designed for mounting and/or electrically contacting one or more semiconductor chips.

According to at least one embodiment of the carrier, the carrier has a first major surface. The first major surface may be an exposed front side of the carrier. For example, the first major surface is a surface of the buffer layer, metallization layer, or connection layer. The carrier may have a second major surface, for example formed by an exposed backside of the carrier. The carrier has, in particular, a mounting surface which is designed to accommodate components, such as semiconductor chips. For example, the buffer layer is located between the mounting surface and the substrate. The mounting surface may be a partial area of the first main surface or the entire first main surface.

According to at least one embodiment of the carrier, the buffer layer has a yield stress of at least 10MPa and at most 300 MPa. The base body and the buffer layer may be designed in terms of their material selection such that the yield stress of the base body is greater than the yield stress of the buffer layer.

The yield stress of a layer is generally understood to be the normal stress required to achieve and sustain plastic flow under the uniaxial stress state of the layer involved. The yield stress of a layer is also generally understood to be the average yield stress of the layer. Yield stress is primarily dependent on the material, the magnitude of deformation, the strain rate or rate of deformation, and the shaping temperature. The yield stress values of known materials, determined under standard conditions common in the art, can be obtained from standard work. In case of doubt, the strain rate can be set at 10 including the end point value at a deformation 0.2% higher than the linear elastic deformation ^-6 /s and 10 ^-2 Between/s or in bagsIncluding end point value 10 ^-6 /s and 10 ^-4 Between/s (e.g. between 5 x 10 ^-4 /s or at 10 ^-5 At/s) and the shaping temperature is between-50 ℃ and 280 ℃ inclusive (e.g., at a shaping temperature of 20 ℃ or 75 ℃), and the yield stress value is determined.

In at least one embodiment of the carrier having a buffer layer and a base body, the carrier has a mounting surface for receiving a semiconductor chip, wherein the buffer layer is located between the mounting surface and the base body. The yield stress of the buffer layer is between 10MPa and 300MPa inclusive. The carrier is constructed of metal. The substrate is preferably formed of a first metal, wherein the buffer layer is formed of a second metal different from the first metal. The base body and the buffer layer are designed in terms of material composition such that the yield stress of the base body is greater than the yield stress of the buffer layer.

Due to the presence of the buffer layer, deformations of the carrier, in particular of the substrate, for example in the form of bends at fluctuating operating temperatures, can be minimized. The semiconductor chip can also be reliably fixed, for example soldered, to the carrier by using the buffer layer to form a stable component, since internal mechanical stresses occurring after the soldering and when the component cools can be largely absorbed by the buffer layer. The risk of cracks forming in the connection layer and/or the carrier is also reduced.

According to at least one embodiment of the carrier, the carrier has a metallization layer, in particular a galvanic metallization layer. The metallization layer adjoins in particular the buffer layer. For example, the metallization layer is arranged in a vertical direction between the body of the carrier and the buffer layer. The buffer layer may also be arranged between the body of the carrier and the metallization layer. The first main surface and/or the mounting surface of the carrier may be formed by a surface, in particular by an at least partially exposed surface of the metallization layer. Alternatively, the first main surface and/or the mounting surface of the carrier may be formed by a surface of the buffer layer or by a surface of a connection layer arranged on the substrate.

According to at least one embodiment of the device, the device has a semiconductor chip, a connection layer and a carrier. In particular, the semiconductor chip is fixed on the carrier by means of the connection layer, for example a solder layer. The carriers described herein are particularly suitable for forming the devices described herein. Thus, features described in connection with the carrier may be used in the device and vice versa.

According to at least one embodiment of the device, the semiconductor chip comprises a substrate and a semiconductor body arranged on the substrate. The semiconductor body has in particular a diode structure. For example, the semiconductor body comprises an optically active region, in particular a pn transition region. In particular, the optically active region is designed to emit or detect electromagnetic radiation in the visible, ultraviolet or infrared spectral range during operation of the semiconductor chip. The semiconductor chip is, for example, a Light Emitting Diode (LED) such as a light emitting high performance diode or a photodiode.

The substrate may be a growth substrate on which the semiconductor body is epitaxially grown. The substrate may also be different from the growth substrate. The semiconductor chip may have no growth substrate. The substrate on which the semiconductor body is arranged can have a base body which is designed to be electrically insulating. In general, the substrate may be electrically insulating.

In particular, the substrate, in particular the base of the substrate, is formed from a material other than metal. For example, the substrate or a matrix of the substrate is based on a semiconductor material, e.g. on Si or Ge, or on a ceramic material, e.g. on SiN or SiC. The substrate may additionally have a filler, for example made of plastic. In particular, the substrate may be formed of a mixture of ceramic and/or semiconductor materials with a plastic or plastics. At least 50%, 60%, 70%, 80% or at least 90% of the weight and/or volume of the semiconductor chip may be landed on the substrate. Alternatively or additionally, the substrate may have one metal through contact or a plurality of, for example two, metal through contacts. In this case, the substrate may have a base formed of a semiconductor material or an electrically insulating material. The through contact or contacts may extend through the base body, for example from the back side of the substrate up to the front side of the substrate.

According to at least one embodiment of the device, the device has a metal carrier. A semiconductor chip having the substrate is disposed on the metal carrier. The metal carrier may have a base body made of metal. For example, the metal carrier is a leadframe or a printed circuit board with a metal core, such as a metal core board. The device is in particular mechanically carried mainly by the metal carrier. The metal carrier is in particular different from a typical chip carrier which carries the semiconductor body and stabilizes the semiconductor chip. For example, the component can have a plurality of semiconductor chips, which each comprise a separate substrate and are arranged on a common metal carrier.

According to at least one embodiment of the device, the connection layer is arranged between the semiconductor chip and the metal carrier. The connection layer is preferably a solder layer, in particular an AuSn-based solder layer and/or an indium-containing solder layer. The semiconductor chip may be fixed on the metal carrier by the connection layer, for example, such that a substrate of the semiconductor chip faces the metal carrier. In the vertical direction, the substrate is located, for example, between the semiconductor body and the carrier of the device. Alternatively, the semiconductor chip may be fixed on the metal carrier such that the semiconductor body is located between the substrate and the carrier.

A vertical direction is generally understood to be a direction transverse, in particular perpendicular, to the main extension surface of the semiconductor body or the carrier. The vertical direction is for example the growth direction of the semiconductor body. Instead, a lateral direction is understood as a direction along, in particular parallel to, the main extension surface of the semiconductor body or the carrier. The vertical direction and the lateral direction are in particular perpendicular to each other. According to at least one embodiment of the device, the thermal expansion coefficient of the metal carrier is at least 1.5 times, at least twice, at least three times, at least four times, at least five times or at least ten times the thermal expansion coefficient of the substrate of the semiconductor chip or of the entire semiconductor chip. For the sake of doubt, the coefficient of thermal expansion of a layer is understood to be the average coefficient of thermal expansion of the layer, e.g. the average coefficient of thermal linear expansion of the layer, which is determined under standard conditions common in the art.

According to at least one embodiment of the device, the device has a buffer layer. The buffer layer may be disposed between the semiconductor chip and the carrier. The buffer layer may be an integral part of the carrier. For example, the buffer layer is integrated in the carrier. The buffer layer is preferably arranged between the base body of the carrier and the connection layer. The buffer layer may be contiguous with the substrate of the carrier and/or the connection layer. In general, two layers are adjacent to each other if they are in particular in direct contact with each other or only a single further layer (in particular a connection layer) or connection structure is present between the two layers.

In particular, the buffer layer is designed with regard to its material selection and/or geometry to compensate or reduce internal mechanical stresses in the component, for example thermo-mechanical stresses in the connection layer, in the substrate, in the semiconductor chip and/or in the metal carrier. According to one embodiment of the device and/or the carrier, the buffer layer is suitably formed of a ductile material. For example, the buffer layer is a ductile metal layer (metalischcicht) or a ductile pure metal layer (metalischcht), which may comprise metals such as gold, aluminum, copper, and the like.

According to at least one embodiment of the device and/or the carrier, the buffer layer has a yield stress of at most 300 MPa. The yield stress of the buffer layer is preferably between 10MPa and 300MPa inclusive, for example between 50MPa and 300MPa, between 100MPa and 300MPa, between 150MPa and 300MPa, between 200MPa and 300MPa or between 10MPa and 250MPa, between 10MPa and 200MPa, between 10MPa and 150MPa, between 10MPa and 100MPa or between 100MPa and 200MPa inclusive.

According to at least one embodiment of the device and/or the carrier, the buffer layer is structured to be coarse-grained. For example, the buffer layer has an average particle size greater than 100nm, such as between 100nm and 150nm inclusive, between 100nm and 200nm inclusive, between 100nm and 300nm inclusive, or between 100nm and 1 μ inclusive. The coarse-grained particles of the buffer layer may be a metal or metal alloy. In particular, the coarse-grained particles can be embedded in a matrix material, for example made of plastic. Depending on how large the coarse grain size the buffer layer is constructed, its liquid limit can be set. The larger the particle size of the buffer layer, the smaller the yield stress thereof.

In at least one embodiment of the device, the device has a semiconductor chip, a buffer layer, a connection layer, and a metal carrier. The semiconductor chip includes a substrate and a semiconductor body disposed on the substrate. The coefficient of thermal expansion of the metal carrier is at least 1.5 times the coefficient of thermal expansion of the substrate or the semiconductor chip. The buffer layer may be disposed between the metal carrier and the semiconductor chip. Particularly preferably, the semiconductor chip is fixed on the mounting surface of the metal carrier by means of the connection layer, so that the connection layer is arranged between the semiconductor chip and the buffer layer. In particular, the connection layer adjoins the back side of the semiconductor chip, for example, the substrate of the semiconductor chip. Furthermore, the buffer layer has a yield stress of at least 10MPa and at most 300 MPa.

By the presence of the buffer layer, internal stresses in the component, which occur as a result of different coefficients of thermal expansion on the carrier side and on the semiconductor chip side in the event of large temperature fluctuations, can be reduced. Thus, when the operating temperature of the device fluctuates, deformations of the semiconductor chip and/or the carrier, for example in the form of bends, can be minimized. The semiconductor chip can also be reliably fastened, for example soldered, to the carrier by using the buffer layer in order to form a stable component, since internal mechanical stresses occurring after the soldering and when the component cools can be absorbed for the most part by the buffer layer. The risk of cracks forming in the connection layer and/or the carrier is also reduced.

According to at least one embodiment of the device and/or the carrier, the substrate and/or the carrier and/or the base of the carrier has a larger vertical layer thickness than the buffer layer. In particular, the vertical layer thickness of the substrate and/or the carrier and/or the base of the carrier is at least three times, at least five times, at least ten times, at least twenty times or at least fifty times the vertical layer thickness of the buffer layer.

For example, the buffer layer has a vertical layer thickness between 250nm and 50 μm inclusive, for example between 1 μm and 10 μm inclusive, between 2 μm and 10 μm inclusive, between 3 μm and 10 μm inclusive or between 300nm and 5 μm inclusive, between 300nm and 3 μm inclusive or between 10 μm and 40 μm inclusive, between 1 μm and 5 μm inclusive or between 1 μm and 3 μm inclusive.

Conversely, the substrate, the matrix of the carrier and/or the entire metal carrier may have a vertical layer thickness of at least 50 μm, for example between 50 μm and 100 μm inclusive, between 50 μm and 150 μm, between 50 μm and 200 μm, between 50 μm and 300 μm inclusive or between 50 μm and 400 μm inclusive. The substrate and/or the matrix of the carrier and/or the entire metal carrier may also have a vertical layer thickness of more than 400 μm.

The metal carrier, in particular the substrate of the carrier, can serve as a heat sink for the semiconductor chip. The buffer layer having a relatively small vertical extension therefore has a low thermal resistance, so that heat generated during operation of the semiconductor chip can be effectively transferred into the metal carrier via the buffer layer.

According to at least one embodiment of the device and/or the carrier, the substrate and/or the matrix of the carrier and/or the entire metal carrier has a larger yield stress than the buffer layer. For example, the difference is at least 30MPa, at least 40MPa, at least 50MPa, at least 60MPa, or at least 100MPa. In this design of the component or the carrier, the realization and retention of the plastic flow (eisetzen) of the buffer layer can be achieved earlier than the base body of the substrate and/or the metal carrier, whereby fractures in the component, in particular in the region of the substrate or the connection layer, can be avoided. The substrate can be formed from a semiconductor material or a ceramic material and can therefore be configured to be more fragile than the buffer layer and the base body of the metal carrier, for example.

According to at least one embodiment of the device, the substrate has a greater vertical layer thickness and a greater yield stress than the buffer layer. The metal carrier, in particular the matrix of the metal carrier, may have a greater yield stress and/or a greater vertical layer thickness than the buffer layer.

According to at least one embodiment of the device, the buffer layer is at least partially covered by the semiconductor chip in a top view of the carrier. For example, in a top view, the semiconductor chip is completely overlapped with the buffer layer. In other words, the semiconductor chip in particular does not have a partial region which does not overlap the buffer layer in a top view of the carrier. The buffer layer may locally protrude laterally beyond the semiconductor chip in at least one lateral direction or in all lateral directions. The lateral cross section of the buffer layer and/or the carrier may be at least equal to or greater than the maximum lateral cross section of the semiconductor chip.

According to at least one embodiment of the device and/or the carrier, the carrier has a coefficient of thermal expansion of more than 8ppm/K, for example between 8ppm/K and 30ppm/K inclusive. The substrate or the semiconductor chip may have a coefficient of thermal expansion of less than 15ppm/K, for example less than 8ppm/K, i.e. less than 8 x 10 ^-6 K ^-1 For example between 2ppm/K and 15ppm/K inclusive. In particular, the thermal expansion coefficient of the metal carrier or of the matrix of the carrier differs from the thermal expansion coefficient of the substrate or of the semiconductor chip by at least 3ppm/K, at least 5ppm/K, at least 7ppm/K or at least 10ppm/K.

According to at least one embodiment of the device, the substrate of the semiconductor chip or a matrix of the substrate of the semiconductor chip is formed of a ceramic material, which may be based on SiN or Sic, or of a semiconductor material such as Si and Ge. Ceramic materials have high thermal conductivity and are particularly suitable for use as a material for the substrate of high performance diodes. Such a substrate may have plastic and/or metal through contacts.

According to at least one embodiment of the device and/or the carrier, the carrier has at least one material from the group consisting of Ag, al, au, cu, mg, mn, ni, pb, pt, sn, mo, W and Zn.

According to at least one embodiment of the device and/or the carrier, the buffer layer has or consists of at least one metal or metal alloy. In particular, the buffer layer may be formed of ductile metals such as Au, al, cu or on similar metals. Preferably, the buffer layer is designed in terms of its material selection and with respect to the carrier and/or the substrate such that it has a smaller yield stress than the carrier and/or the substrate.

According to at least one embodiment of the device and/or the carrier, the connection layer is a solder layer, for example an AuSn-based solder layer and/or an indium-containing solder layer. The connection of the semiconductor chip to the carrier is carried out at a temperature above the melting temperature of the solder used. In the case of AuSn, the melting temperature is about 280 ℃ or higher. When cooled, the device is reduced in size but is non-uniform in the area of the semiconductor chip and in the area of the carrier. It has been found that the buffer layer made of a metal or metal alloy having a yield stress between 10MPa and 300MPa inclusive, in particular between 100MPa and 300MPa inclusive, can compensate for strong stresses in the device over a large temperature interval, for example between-50 ℃ and 300 ℃ inclusive. In this way, possible bending of the semiconductor chip and/or the carrier or peeling of the semiconductor chip in the event of temperature fluctuations can be avoided.

According to at least one embodiment of the device, the device has a converter layer comprising a phosphor, i.e. a wavelength converting luminescent substance. The semiconductor chip is in particular a light emitting diode. The converter layer may be fastened to the semiconductor chip, for example, arranged on a surface of the semiconductor chip facing away from the carrier. For example, the converter layer is arranged on an upper side of the semiconductor body facing away from the substrate. The converter layer may be arranged on an upper side of the substrate facing away from the semiconductor body if the semiconductor body is arranged between the substrate and the carrier. In particular, the converter layer is designed in the operation of the device to convert the short-wave component, in particular the blue or ultraviolet component, of the electromagnetic radiation emitted by the semiconductor chip into a long-wave component, for example the yellow, green or red component, of the electromagnetic radiation.

The converter layer is preferably a prefabricated converter plate, which may have a vertical layer thickness that is constant within manufacturing tolerances. The converter plate may be configured to be self-supporting and in particular flat. The converter plate can be fastened to the semiconductor chip via further connection layers, for example on the upper side of the semiconductor chip, in particular on the upper side of the semiconductor body. The further connection layer may be an adhesive layer or an adhesive layer and in particular is different from the solder layer. By using the buffer layer, deformations of the semiconductor chip are prevented or at least reduced, whereby in particular mechanical stresses in the adhesive connection of the converter plate to the semiconductor chip are reduced, and thus the risk of a shift in chromaticity coordinates can also be reduced. In other words, chromaticity coordinate fluctuations due to deformation or bending of the converter layer or the converter plate can be avoided or minimized in the operation of the device.

By means of the buffer layer, a possible bending or deformation of the component, the carrier or the semiconductor chip is prevented or reduced, so that a stable connection between the converter plate and the semiconductor chip can be ensured. Such bending or deformation will generally occur without the buffer layer, in particular if the vertical layer thickness of the substrate and/or the carrier is less than 400 μm, in particular less than 300 μm or less than 200 μm.

According to at least one embodiment of the device, the buffer layer covers at least 90% of the back side of the semiconductor chip or the substrate facing the carrier. For example, the buffer layer completely covers the back side of the semiconductor chip. In a top view, the carrier and/or the buffer layer has a larger surface than the semiconductor chip, for example. The buffer layer can in particular protrude beyond the semiconductor chip not only in the region below the semiconductor chip, but also laterally on the mounting surface of the carrier. The component may have a plurality of semiconductor chips on a common metal carrier, wherein each partial region of the buffer layer is assigned exclusively to one of the semiconductor chips or to a plurality of semiconductor chips.

According to at least one embodiment of the device, the substrate is arranged between the carrier and the semiconductor body. Alternatively, the semiconductor body may be arranged between the carrier and the substrate.

According to at least one embodiment of the component and/or the carrier, the buffer layer is structured. For example, the mounting surface is a partial region of the first main surface of the carrier, wherein the buffer layer is structured such that it completely covers the mounting surface and only partially covers the first main surface. Thus, the size of the mounting surface is defined by the structuring of the buffer layer. Alternatively, the buffer layer may be constructed to be coherent and/or free of holes. In particular, in a top view of the carrier, the buffer layer completely covers the base body of the carrier. In other words, the buffer layer may completely cover the surface of the substrate of the carrier facing the buffer layer and/or the first main surface of the carrier.

According to at least one embodiment of the device and/or the carrier, the buffer layer is structured such that the buffer layer has one or more openings. The openings may extend through or into the buffer layer in a vertical direction. In particular, the opening is arranged in a lateral direction of the mounting surface. For example, the opening has the form of a channel or frame which laterally partially or completely surrounds the mounting surface. The buffer layer may be divided into a plurality of partial regions by the opening. These partial regions may form a plurality of laterally spaced mounting surfaces for the semiconductor chip.

According to at least one embodiment of a method for manufacturing a device, the device is annealed after fixing one or more semiconductor chips on a carrier. In order to adapt the flow characteristics of the connection layer and/or the buffer layer, the device may be annealed at a temperature between 125 ℃ and 200 ℃ inclusive. The heat treatment may be performed during a period of several minutes (e.g., between 10 minutes and 50 minutes) or several hours (e.g., between 1 hour and 10 hours). The connection layer is, for example, an AuSn-based solder layer, the melting temperature of which is higher than the temperature applied during the heat treatment.

By means of the heat treatment, on the one hand, internal stresses in the component and, on the other hand, possible bending of the component can be reduced. It has been found that by means of the heat treatment the curvature of the device can be reduced additionally by at least 5% up to 40%.

The above-described method is particularly suitable for fabricating the devices described herein. Thus, features described in connection with the device or the carrier may be used in the method and vice versa.

Drawings

Further advantages, preferred embodiments and extensions of the device, the carrier or the method result from the examples explained below in connection with fig. 1 to 6B.

Figure 1A shows a comparative example of a device without a buffer layer in a schematic cross-sectional view,

figure 1B shows a comparative example of a device with a buffer layer in a schematic cross-sectional view,

fig. 2A, 2B, 2C, 2D, 2E and 2F show schematic views of different embodiments of a carrier with a buffer layer in cross-section,

fig. 3A, 3B, 3C, 3D, 4A, 4B and 4C show schematic diagrams of different embodiments of a device with a buffer layer in cross-section, respectively, and

fig. 5A, 5B, 5C, 5D, 6A and 6B show graphical or tabular illustrations of the results of some experimental measurements and simulations of different devices with or without buffer layers before or after heat treatment,

Fig. 7A and 7B show schematic diagrams of other embodiments of devices with buffer layers in cross-section, respectively, and

fig. 8 shows a schematic diagram of a further embodiment of a carrier with a buffer layer.

In the drawings, identical, similar or functionally identical elements have the same reference numerals. Each of the figures is schematic and, therefore, is not necessarily to scale. On the contrary, relatively small elements, particularly layer thicknesses, may be exaggerated for clarity.

Detailed Description

Fig. 1A schematically shows a comparative example of a component 100 having a semiconductor chip 10 on a carrier 9, the semiconductor chip 10 being fastened via a connection layer 4 to a first main surface 91 of the carrier 9 or to a mounting surface 94 of the carrier 9.

The semiconductor chip 10 has a front side 101 and a back side 102 facing away from the front side 101. The front side of the device 100 may be formed by the front side 101 of the semiconductor chip 10. For example, the front side 101 is a radiation entrance surface or a radiation exit surface of the semiconductor chip 10 or the device 100. In particular, the connection layer 4 adjoins both the mounting surface 94 of the carrier 9 and the rear side 102 of the semiconductor chip 10.

Fig. 4A to 4C schematically show, for example, a semiconductor chip 10 with a substrate 1, a semiconductor body 2 and optionally a converter layer 6.

In general, the carrier 9 and the semiconductor chip 10, in particular the carrier 9 and the substrate 1 of the semiconductor chip 10, have different coefficients of thermal expansion. In the case of severe temperature fluctuations, internal stresses may occur in the component 100, which lead to a bending of the component 100, in particular of the semiconductor chip 10, or to a fracture of the component 100, for example at the connection layer 4. Bending of the semiconductor chip 10, in particular of the LED with the converter layer 6, can also lead to undesired changes in the chromaticity coordinates in the event of temperature fluctuations. Due to possible deformations of the component 100, the converter layer 6, which is embodied, for example, in the form of a converter plate and is fastened to the semiconductor chip 10 by means of the further connection layer 5, can be peeled off from the semiconductor chip 10.

In order to avoid possible cracks in the connection layer 4 or the semiconductor chip 10 due to the different coefficients of thermal expansion between the substrate 1, which is formed for example of Si, ge, siN or SiC, and the carrier 9, which is formed in particular of a metal such as Cu, a sufficient fracture strength of the device 100 should be ensured. This can be achieved, for example, by using a solder connection with high mechanical strength between the semiconductor chip 10 and the carrier 9. In order to prevent strong chromaticity coordinate changes of the semiconductor chip 10 or peeling of the converter layer 6, an adhesive having particularly strong adhesion should be used to bond the converter layer 6, and additionally a minimum thickness of the other connection layer 5 to fix the converter layer 6 to the semiconductor chip 10 should be ensured. Despite the measures described above, there may still be a non-negligible quality risk due to the high stresses in the device 100 with the semiconductor chip 10 on the metal carrier 9.

In order to minimize this quality risk, the device 100 may be designed such that the buffer layer 3 is arranged between the semiconductor chip 10 and the metal carrier 9, in particular between the semiconductor chip 10 and the body 90 of the carrier 9. In particular, the buffer layer 3 may be formed as an integral part of the carrier 9.

According to the comparative example shown in fig. 1B, the device 100 has such a buffer layer 3. The buffer layer 3 is arranged between the semiconductor chip 10 and the connection layer 4 in the vertical direction. The buffer layer 3 adjoins in particular both the connection layer 4 and the semiconductor chip 10, in particular the substrate 1 of the semiconductor chip 10. Preferably, only the buffer layer 3 and the connection layer 4 are arranged between the mounting surface 94 of the carrier 9 and the backside 102 of the semiconductor chip 10.

The buffer layer 3 may be configured as a part of the semiconductor chip 10. In this case, the semiconductor chip 10 already has the buffer layer 3 before the semiconductor chip 10 is applied to the carrier 9. The buffer layer 3 may be formed directly or indirectly on the semiconductor chip 10, in particular on the back side 102 of the semiconductor chip 10, for example on the substrate 1 of the semiconductor chip 10. For this purpose, a starting layer of the rear side 102 can be formed first, in particular on the substrate 1, and subsequently the buffer layer 3 can be formed on the starting layer, for example by means of an electroplating method. Alternatively, the buffer layer 3 may be formed by a different coating method, for example by an evaporation method or a deposition method such as vapor deposition or by sputtering. In this case, the starting layer may be discarded.

In top view, the buffer layer 3 may be completely covered by the substrate 1 and/or the semiconductor body 2. The buffer layer 3 may cover at least 60%, at least 70%, at least 90% or at least 95% of the surface of the back side 102 of the semiconductor chip 10. The buffer layer 3 may be flush with the substrate 1 or with the semiconductor chip 10 in at least one lateral direction or in all lateral directions. If the buffer layer 3 is an integral part of the semiconductor chip 10, the buffer layer 3 cannot protrude beyond the semiconductor chip 10 in the lateral direction. Therefore, the extension of the buffer layer 3 is limited by the size of the semiconductor chip 10, for example.

Fig. 2A shows an embodiment of the carrier 9. The carrier 9 has a base body 90 and a buffer layer 3 arranged on the base body 90. A metallization layer 93, in particular a plated metallization layer 93, is arranged between the buffer layer 3 and the substrate 90. In top view, the buffer layer 3 partially covers the substrate 90 and/or the metallization layer 93. In particular, the buffer layer 3 forms a seat for accommodating one or more semiconductor chips 10. The buffer layer 3 may be formed on the body 90 or on the metallization layer 93 by means of a mask or by subsequent structuring.

The carrier 9 has a first main surface 91, which is for example the exposed front side of the carrier 9. The main surface 91 is composed of, for example, a buffer layer 3 and a metallization layer 93. In particular, a partial region of the main surface 91 is configured as a mounting surface 94 of the carrier 9. For example, the mounting surface 94 is formed by the surface of the buffer layer 3. The mounting surface 94 in fig. 2A is in particular locally vertically raised on the main surface 91 of the carrier 9. The carrier 9 has a second main surface 92, which is for example the exposed back side of the carrier 9. In particular, the second major surface 92 is formed by a surface of the substrate 90.

Unlike fig. 2A, the buffer layer 3 may be disposed between the metallization layer 93 and the substrate 90. In particular, the buffer layer 3 is laterally shaped by a metallization layer 93 (fig. 8).

The embodiment shown in fig. 2B corresponds substantially to the embodiment of the carrier 9 shown in fig. 2A. Unlike fig. 2A, a buffer layer 3 having a vertical layer thickness D3 is arranged between the base body 90 and the metallization layer 93. The buffer layer 3 is constructed to be coherent and to cover the substrate completely. In top view, the metallization layer 93 may completely cover the buffer layer 3. The first main surface 91 and/or the mounting surface 94 are formed in particular by the surface of the metallization layer 93 only.

The embodiment shown in fig. 2C corresponds substantially to the embodiment of the carrier 9 shown in fig. 2B. Unlike fig. 2B, the carrier 9 has at least one opening 95 or a plurality of openings 95. In particular, the mounting surface 94 or a partial region of the mounting surface 94 is delimited in the transverse direction by one opening 95 or by a plurality of openings 95.

The opening 95 or openings 95 can extend through the buffer layer 3, for example, into the base body 90. The buffer layer 3 is thus structured. The buffer layer 3 can also be covered, in particular completely covered, by the metallization layer 93 in a top view. The inner walls of the openings 95 may be covered, in particular completely covered, by the metallization layer 93. Furthermore, the metallization layer 93 may be configured to be coherent and free of holes.

For example, the metallization layer 93 is applied to the buffer layer 3 after the openings 95 are formed. The buffer layer 3 can be applied to the body 90 in a structured manner, for example by means of a mask. Alternatively, the buffer layer 3 may be formed first as a continuous layer and subsequently structured, for example by means of an etching method.

The embodiment shown in fig. 2D corresponds in top view, for example, to the embodiment of the carrier 9 shown in fig. 2C. The opening 95 may be designed in the form of a channel or a frame. In particular, a first partial region 96 of the main surface 91 is surrounded, in particular completely surrounded, in the transverse direction by the opening 95. For example, a first partial region 96 configured as a coherent formation forms the mounting surface 94. The second partial region 97 of the main surface 91 is laterally spaced from the first partial region 96 by an opening 95. It has been found that an interruption of the buffer layer 3 results in an improved buffering effect. Unlike fig. 2D, the carrier 9 may have a plurality of such laterally spaced partial areas 96 or mounting surfaces 94. Furthermore, unlike fig. 2D, the carrier may have electrical conductor tracks and/or electrical connection surfaces on the first main surface for electrically contacting components arranged on the first main surface.

The embodiment shown in fig. 2E essentially corresponds to the embodiment of the carrier 9 shown in fig. 2C or 2D. Unlike fig. 2C or 2D, an opening 95 or openings 95 extend through the metallization layer 93, in particular into the buffer layer 3. The embodiment shown in fig. 2F corresponds substantially to the embodiment of the carrier 9 shown in fig. 2E. Unlike fig. 2E, the carrier 9 has a connection layer 4. In particular, the mounting surface 94 is at least partially formed by a surface of the connection layer 94. The embodiments shown in fig. 2A to 2E can likewise have such a connection layer 4.

In fig. 2F, the mounting surface 94 is a local vertical elevation on the main surface 91, wherein the mounting surface 94 is delimited in the lateral direction, in particular by one opening 95 or by a plurality of openings 95. The connection layer 4 may have a connection material, such as a solder material. The opening 95 or openings 95 may serve as a peristaltic stop for the liquid connection material and are specifically designed to capture molten or excess connection material, for example, when mounting one or more semiconductor chips.

In all embodiments, the buffer layer 3 may have a material composition which is suitably different from the material composition of the carrier 9 and/or the substrate 1. The buffer layer 3 is preferably constructed of metal and has a yield stress between 10MPa and 300MPa inclusive. The buffer layer 3 suitably has or consists of a ductile metal such as Au, al or Cu, or an alloy thereof. To reduce the yield stress, the buffer layer 3 may be coarse grained, e.g. with a metal grain size of more than 100 nm. The buffer layer 3 is in particular different from the connection layer 4, for example from a solder layer.

An embodiment of a device 100 with a semiconductor chip 10 on a carrier 9 with a body 90 is schematically shown in fig. 3A, 3B, 3C and 3D. A connection layer 4, a buffer layer 3 and a metallization layer 93 are arranged between the semiconductor chip and the body 90. However, the metallization layer 93 may be optional. The connection layer 4 adjoins in particular both the mounting surface 94 and the rear face 102 of the semiconductor chip 10, for example the substrate 1.

The embodiment of the device 100 shown in fig. 3A corresponds to the embodiment of the carrier 9 shown in fig. 2A, wherein a semiconductor chip 10 is arranged on the carrier 9. The buffer layer 3 is designed in particular as a mount under the semiconductor chip 10. In a top view of the carrier 9, the semiconductor chip 10 can completely cover the buffer layer 3. In this case, the buffer layer 3 is structured only in the area covered by the semiconductor chip 10. Alternatively, the buffer layer 3 configured as a mount may protrude laterally beyond the semiconductor chip 10 in the lateral direction. In particular, the buffer layer 3 only partially covers the first main surface 91, the metallization layer 93 and/or the substrate 90.

The embodiment of the different device 100 shown in fig. 3B, 3C and 3D corresponds to the embodiment of the carrier 9 shown in fig. 2B, 2C and 2E, respectively, wherein the semiconductor chip 10 is arranged on the carrier 9. The buffer layer 3 may protrude laterally beyond the semiconductor chip 10 and may partially or completely cover the first main surface 91, the metallization layer 93 and/or the substrate 90.

The embodiment shown in fig. 4A substantially corresponds to the embodiment of the device 100 shown in fig. 3A. Unlike fig. 3A, the semiconductor chip 10 is shown in more detail in fig. 4A.

The semiconductor body 2 has a first semiconductor layer 21 facing away from the substrate 1, a second semiconductor layer 22 facing the substrate 1 and an optically active region 23 arranged between the first and second semiconductor layers. The semiconductor body 2 is based in particular on a III-V or II-VI semiconductor composite. The first semiconductor layer 21 and the second semiconductor layer 22 may be configured to be n-conductive or p-conductive and/or n-doped or p-doped, or vice versa.

The semiconductor body 2 has a first main surface 201 facing away from the substrate 1 and a second main surface 202 facing the substrate 1. The first main surface 201 and the second main surface 202 each delimit the semiconductor body 2 in the vertical direction. The converter layer 6 is fixed at the first main surface 201 of the semiconductor body 2 by means of the further connection layer 5. The particularly exposed surface of the transducer layer 6 forms the front side 101 of the semiconductor chip 10 and/or the device 100.

The semiconductor chip 10 has a first contact layer 71 for electrically contacting the first semiconductor layer 21 and a second contact layer 72 for electrically contacting the second semiconductor layer 22. As shown in fig. 4A, the first contact layer 71 is arranged on the first main surface 201 side of the semiconductor body 2, while the second contact layer 72 is arranged on the second main surface 202 side of the semiconductor body 2. In particular, the second contact layer 72 is located locally between the semiconductor body 2 and the substrate 1. The semiconductor chip 10 may be electrically contacted from the outside via the contact layers 71 and 72, and the contact layers 71 and 72 may be accessed at least partly via the front side 101 of the device 100.

The carrier 9 may have conductor tracks (not shown in the figures) which are arranged, for example, on a mounting surface 94 on the main surface 91 of the carrier 9 and/or laterally of the mounting surface 94. For example, the contact layers 71 and 72 can be electrically conductively connected to the conductor tracks of the carrier 9 via bonding wires. The carrier 9 may have a metallic lead frame. In particular, the body 90 forms the leadframe, which is shaped, for example, by a molded body. The molded body may be configured to be electrically insulating.

The embodiment shown in fig. 4B substantially corresponds to the embodiment of the device 100 shown in fig. 4A. Unlike fig. 4A, the second contact layer 72, which is formed in the form of a through contact, extends from the second main surface 202, for example, through the substrate 1, for example, up to the back side 102 of the semiconductor chip 10. In particular, the buffer layer 3 and the connection layer 4 are configured to be electrically conductive. The semiconductor chip 10 can be in electrical contact with the carrier 1 and can be electrically contacted via the carrier 1.

Unlike fig. 4B, the substrate 1 may be designed to be conductive. In this case, the second contact layer 72 configured as a through contact may be omitted.

The embodiment shown in fig. 4C substantially corresponds to the embodiment of the device 100 shown in fig. 4B. Unlike fig. 4B, the semiconductor chip 10 has a through contact 70, which extends, for example, from the second main surface 202 or from the first contact layer 71 into the first semiconductor layer 21 through the second semiconductor layer 22 and the active region 23. For lateral electrical insulation, for example, the through contact 70 is completely surrounded in the transverse direction, for example, by the insulating layer 8.

According to fig. 4C, both the first contact layer 71 and the second contact layer 72 are locally located on the second main surface 202. The first contact layer 71 is arranged at least partially between the substrate 1 and the semiconductor body 2. Unlike fig. 4C, both the first contact layer 71 and the second contact layer 72 may extend through the substrate 1. In such a case, the semiconductor chip 10 is a surface-mountable semiconductor chip which can only be contacted electrically on its back side 102.

The results of some experimental measurements (fig. 5A) and some simulations (fig. 5B,5C and 5D) for the device 100 are graphically shown in fig. 5A, 5B,5C and 5D. Reference numerals K, N and S represent the curvature of the semiconductor chip 10, the maximum normal stress determined on the semiconductor chip 10, and the maximum shear stress determined on the semiconductor chip at room temperature after the connection process, respectively. The parameters O3, M3, T1 and T2 represent "no buffer layer 3", "with buffer layer 3", "before annealing" and "after annealing", respectively, in the illustrated order.

A device 100 with a semiconductor chip 10 and a carrier 9, for example according to fig. 1B or 3A, is used as a sample, wherein the carrier 9 has a lead frame made of copper, and wherein the semiconductor chip 10 comprises a silicon substrate 1 and is fixed on the carrier 9 by means of a solder layer 4. The carrier 9 or the matrix 90 of the carrier 9 has a layer thickness of about 150 μm. The buffer layer 3 is formed of gold and has a layer thickness D3 of about 2 μm.

As can be seen from fig. 5A, the curvature K is reduced by using the buffer layer 3. The curvature K of the semiconductor chip 10 and/or the device 100 can also be reduced by an annealing process, wherein the curvature K can be reduced more severely in the presence of the buffer layer 3. This effect with respect to the reduction of the curvature K can also be seen in fig. 5B. According to the results shown in fig. 5A and 5B, if the device 100 has the buffer layer 3 and the device 100 is subjected to a heat treatment, in particular after the semiconductor chip 10 is fixed on the carrier 9, the semiconductor chip 10 has the smallest curvature K.

Simulation results of normalized normal stress N and shear stress S compared to curvature K are shown in fig. 5C and 5D. Here, the maximum normal stress N and the maximum shear stress S of the device without the buffer layer 3 are normalized to 1 at time T1. It has been found that the device 100 is most stable if the device 100 has a buffer layer 3 and is heat treated. Here, the maximum normal stress N or the maximum shear stress S will be reduced by more than 20% or more than 40%.

It was furthermore determined that the maximum normal stress N decreases with increasing layer thickness of the buffer layer 3. With layer thicknesses of 0.5 μm, 1 μm and 2 μm, the maximum normal stresses were determined to be 127MPa, 125MPa and 124MPa in the order illustrated.

It was furthermore determined that the curvature K, the normal stress N and the shear stress S can be reduced more severely in the case of the device 100 according to fig. 3A, 3B, 3C and 3D than in the case of the device 100 according to fig. 1B. The reason for this is that, in comparison with the device according to fig. 1B, the buffer layer 3 is not only located directly below the semiconductor chip 10, but can also protrude laterally beyond the semiconductor chip edge. In this case, a larger part of the first main surface 91 of the carrier 9 or the entire first main surface 91 can be covered by the buffer layer 3, whereby the internal thermo-mechanical stresses occurring can be better compensated.

These simulations also show that the cushioning effect is additionally increased if the cushioning layer 3 is not continuously structured, but is structured as shown, for example, in fig. 2C, 2D, 2E, 2F, 3C and 3D. In this case, the opening 95 or openings 95 can serve as compensation areas, which prevent severe deformations or bending of the carrier 1. Fig. 6A and 6B show some other results for the determined normal stress N and the determined curvature K at the time T1 before the heat treatment or at the time T2 after the heat treatment. The device 100 is examined here with different designs, i.e. with different layer thicknesses D3 of the buffer layer 3 according to fig. 1A, 3B or 3C. It has been found that the cushioning effect of the cushioning layer 3 increases with increasing layer thickness D3. The lateral structuring of the buffer layer 3 (fig. 3C) may further increase the buffering effect. Furthermore, the heat treatment results in a significant reduction of the curvature K of the semiconductor chip 10 and of the maximum normal stress N determined on the semiconductor chip 10.

The embodiment shown in fig. 7A corresponds substantially to the embodiment of the device 100 shown in fig. 4C. Unlike fig. 4C, the semiconductor body 2 is arranged between the substrate 1 and the carrier 9 or the buffer layer 3. The substrate 1 is located between the semiconductor body 2 and the transducer layer 6. In particular, the semiconductor chip 10 is a flip chip. The substrate 1 may be constructed to be transparent to radiation.

Another difference from the device 100 shown in fig. 4C is that the buffer layer 3 and/or the connection layer 4 have partial regions which are laterally spaced apart by the intermediate region 80. The intermediate region 80 may be filled with an electrically insulating material. The first partial region 41 of the connection layer 4 is electrically connected, for example, to the first contact layer 71. The second partial region 42 of the connection layer 4 is electrically connected, for example, to the second contact layer 72. The first partial region 31 of the buffer layer 3 is laterally spaced apart from the second partial region 32 of the buffer layer 3 by the intermediate region 80 and is in particular electrically insulated from said second partial region 32. The intermediate region 80 extends in particular in the vertical direction through the buffer layer 3 and/or through the connection layer 4.

The first contact layer 71 can be in electrical contact via the first partial regions 31 and 41, for example, with a first connection surface on the carrier 9 or with a first conductor track (not shown in fig. 7A) on the carrier 9. The second contact layer 72 can be in electrical contact with, for example, a second connection surface on the carrier 9 or with a second conductor track (not shown in fig. 7A) on the carrier 9 via the second subregions 32 and 42.

Unlike fig. 7A, the contact layers 71 and 72 may extend through the buffer layer 3 and be electrically insulated from the buffer layer 3, for example, by an insulating layer. In this case, the buffer layer 3 can continue to be designed to be coherent. The intermediate region 80 may also extend through the carrier 9 and divide the carrier 9 into two partial regions which are spaced apart from one another in the transverse direction.

The embodiment shown in fig. 7B corresponds substantially to the exemplary embodiment of the device 100 shown in fig. 4C. Unlike fig. 4C, the first contact layer 71 and the second contact layer 72 are each formed as a through contact portion penetrating through the substrate 1. The electrical contact between the semiconductor chip 10 and the carrier 9 shown in fig. 7B corresponds to the contact shown in fig. 7A.

By means of a buffer layer, in particular made of ductile material, arranged between the metal carrier and the semiconductor chip fastened to the carrier, the component with the carrier and the semiconductor chip can be designed to be particularly mechanically stable. Furthermore, such devices are also particularly insensitive to large temperature fluctuations in terms of their mechanical stability and/or chromaticity coordinate stability.

This patent application claims priority from german patent application DE102017119344.8, the disclosure of which is incorporated herein by reference.

The present invention is not limited to these embodiments because of the description of the present invention based on the embodiments. Rather, the invention comprises each new feature and each combination of features, especially including each combination of features in the claims, even if the feature or the combination itself is not explicitly indicated in the claims or the embodiments.

List of reference numerals

100 devices

10 semiconductor chip

Front side of 101 semiconductor chip/device

102 backside of semiconductor chip

1 substrate for semiconductor chip

2 semiconductor body

21 first semiconductor layer

22 second semiconductor layer

23 optically active region

201 upper side of semiconductor body

202 underside of semiconductor body

3 buffer layer

31 first partial region of buffer layer

Second partial region of 32 buffer layer

4 tie layer

First partial region of 41 connection layer

42 second partial region of the connection layer

5 other connection layers

6 converter layer

71 first contact layer

72 second contact layer

70 through contact

8 insulating layer

80 middle region

9 device carrier

90 carrier matrix

First major surface/front side of 91 carrier

Second major surface/backside of 92 carrier

93 metallization layer

94 mounting surface of carrier

Openings of 95 buffer layer

First partial region of 96 main surface

Second partial region of 97 main surface

Vertical layer thickness of D3 buffer layer

K curvature

N normal stress

S shear stress

O3 no buffer layer 3

M3 has a buffer layer 3

Before Tl annealing

And (5) after T2 annealing.

Claims

1. A component (100) has a semiconductor chip (10), a buffer layer (3), a connection layer (4) and a metal carrier (9), wherein

The semiconductor chip comprises a substrate (1) and a semiconductor body (2) arranged on the substrate,

the coefficient of thermal expansion of the metal carrier is at least 1.5 times the coefficient of thermal expansion of the substrate or the semiconductor chip,

fixing the semiconductor chip on a mounting surface (94) of the metal carrier by means of the connection layer such that the connection layer is arranged between the semiconductor chip and the buffer layer and adjoins a rear side (102) of the semiconductor chip,

the yield stress of the buffer layer is at least 10MPa and at most 300MPa,

-the buffer layer (3) is structured in such a way that it has openings (95) which extend in the vertical direction into the buffer layer or through the buffer layer into the base body (90) of the carrier (9) and are arranged in the lateral direction laterally of the mounting surface (94), and

-the substrate (1) of the semiconductor chip and the metal carrier (9) of the device have a yield stress greater than that of the buffer layer (3), wherein

-the substrate is a growth substrate on which the semiconductor body (2) is epitaxially grown, or

-the substrate has a metallic through contact (72) and a matrix made of a semiconductor material or an electrically insulating material, wherein the through contact extends through the matrix of the substrate.

2. The device according to claim 1, wherein, in a top view of the carrier (9), the buffer layer (3) is partially covered by the semiconductor chip (10) and partially protrudes laterally beyond the semiconductor chip.

3. The device according to any one of claims 1 to 2, wherein,

-the carrier (9) has at least one material from the group of Ag, al, au, cu, mg, mn, ni, pb, pt, sn, mo, W and Zn, and

-the buffer layer (3) has at least one metal, wherein the buffer layer is configured in terms of its material selection and in terms of the carrier (9) and/or the substrate (1) such that the buffer layer has a lower yield stress than the carrier and/or the substrate.

4. The device according to any one of claims 1 to 2, wherein the connection layer (4) arranged on the mounting surface (94) is a solder layer.

5. The device according to any one of claims 1 to 2, wherein the opening (95) has the form of a groove or a frame which laterally partly or completely surrounds the mounting surface (94), such that the mounting surface (94) is configured as a local vertical elevation on the main surface (91) of the carrier (9) and is delimited by the opening (95) in the lateral direction.

6. Device according to any one of claims 1 to 2, having a converter layer (6) arranged on a surface of the semiconductor chip (10) facing away from the carrier (9), wherein the semiconductor chip (10) is a light emitting diode and the converter layer has a wavelength converting luminescent substance.

7. Device according to claim 6, wherein the substrate (1) and/or the carrier (9) have a vertical layer thickness of less than 400 μm and the converter layer (6) is a prefabricated converter plate which is fixed with the semiconductor chip (10) by means of a further connection layer (5).

8. A carrier (9) has a buffer layer (3) and a base body (90), wherein

-the carrier has a mounting surface (94) for accommodating a semiconductor chip (10), wherein the buffer layer is located between the mounting surface and the base body;

The yield stress of the buffer layer is at least 10MPa and at most 300MPa,

the support is constructed of metal,

the base body and the buffer layer are designed in terms of material composition such that the yield stress of the base body is greater than the yield stress of the buffer layer, and

-the buffer layer (3) is structured such that it has openings (95) extending into or through the buffer layer in a vertical direction into the base body (90) and arranged laterally to the mounting surface (94), wherein the openings (95) act as peristaltic stops for the liquid connecting material.

9. The support according to claim 8, wherein the buffer layer (3) is configured to be coarse-grained, having an average grain size of more than 100 nm.

10. The carrier according to claim 8, wherein the buffer layer (3) is a ductile metal layer.

11. The carrier according to claim 8, wherein the buffer layer (3) is a ductile pure metal layer.

12. The carrier according to any one of claims 8 to 11, wherein,

-the buffer layer (3) has a vertical layer thickness from 250nm to 10 μm, and

-the vertical layer thickness of the substrate (90) or of the entire carrier (9) is at least 50 μm.

13. The carrier according to any one of claims 8 to 11, wherein the carrier (9) is a printed circuit board designed for mounting one or more semiconductor chips (10) and for electrically contacting one or more semiconductor chips (10).

14. The carrier according to any one of claims 8 to 11, wherein the carrier (9) has a metallization layer (93) adjoining the buffer layer (3).

15. The carrier of claim 14, wherein the metallization layer (93) is a plated metal layer.

16. The carrier according to any one of claims 8 to 11, wherein the mounting surface (94) is a partial region of the first main surface (91) of the carrier (9), and the buffer layer is structured such that it completely covers the mounting surface (94) and only partially covers the first main surface (91).

17. The carrier according to any one of claims 8 to 11, wherein the opening (95) has the form of a groove or a frame which laterally partly or completely surrounds the mounting surface (94), such that the mounting surface (94) is configured as a local vertical elevation on the main surface (91) of the carrier (9) and is delimited by the opening (95) in the lateral direction.

18. Carrier according to any one of claims 8 to 11, wherein the openings (95) extend in a vertical direction only into the buffer layer, the buffer layer (3) being constructed to be coherent and completely cover the carrier's base body (90) in a top view of the carrier (9).

19. A method for manufacturing a device (100) according to any of claims 1 to 7, wherein the device is annealed after the semiconductor chip (10) is fixed on the carrier (9).

20. The method according to claim 19, wherein the connection layer (4) is an AuSn-based solder layer and the device (100) is annealed at a temperature from 125 ℃ to 200 ℃ in order to adapt the flow characteristics of the connection layer and the buffer layer (3).