CN111246208A

CN111246208A - Video processing method and device and electronic equipment

Info

Publication number: CN111246208A
Application number: CN202010074802.2A
Authority: CN
Inventors: 黎凌宇; 尹海斌; 王悦
Original assignee: Beijing ByteDance Network Technology Co Ltd
Current assignee: Beijing ByteDance Network Technology Co Ltd
Priority date: 2020-01-22
Filing date: 2020-01-22
Publication date: 2020-06-05
Anticipated expiration: 2040-01-22
Also published as: WO2021147463A1; CN111246208B

Abstract

The disclosed embodiments provide a video processing method, apparatus and electronic device, the method searches a reference pixel block from a preset pixel block information table according to 32-bit crc values of a target pixel block in a preset coding mode when coding the target pixel block, and obtains coordinates thereof, and further performs conversion between bit representations of the target pixel block and the target pixel block according to the coordinates, wherein for two blocks with difference pixel values, the 32-bit crc values are completely different, thereby solving the problem that a large number of similar image blocks have the same hash value due to IBC coding, thereby reducing coding speed, in addition, the disclosed embodiments perform a segment search in the preset pixel block information table according to values of a first preset bit and a second preset bit in the 32-bit crc values of the target pixel block when searching the reference pixel block, thereby enabling the preset pixel block information table to store information in segments, saving storage space and being suitable for practical application.

Description

Video processing method and device and electronic equipment

Technical Field

The embodiment of the disclosure relates to the technical field of coding, and in particular, to a video processing method and apparatus, and an electronic device.

Background

With the development of information technology, video image services such as high-definition televisions, web conferences, interactive Internet Protocol Televisions (IPTV), three-dimensional (3D) televisions and the like are rapidly developed, and video image signals become the most important way for people to acquire information in daily life due to the advantages of intuitiveness, high efficiency and the like. Taking a screen video as an example, the screen video content is video content directly captured in an image display of a terminal such as a computer, a mobile phone and the like, and mainly comprises computer graphics, text documents, mixed images of natural video and graphics and text, computer generated images and the like. The screen video coding has wide application prospect in the fields of desktop sharing, video conferences, online education, cloud games and the like.

In the related art, the hevc scc proposes an expansion proposal for screen video content on the hevc/h.265. The hevcscc encoding tool has Intra Block Copy (IBC). There is a large amount of repeated content in the on-screen video content, such as text icons and the like. When encoding a current block, performing a conventional motion search method cannot accurately find a perfectly matched reference block. If the IBC is adopted to search the matched blocks in the screen content, if the matched reference blocks can be searched, the residual error is almost zero, and the compression efficiency is greatly improved.

However, in the IBC, based on the gradient calculation of the image block, a large number of similar image blocks have the same hash value, and thus, when the reference block is searched according to the hash value, a large number of searched reference blocks are caused, and the searched reference block needs to be further processed to determine a final reference block, thereby reducing the encoding speed.

Disclosure of Invention

The embodiment of the disclosure provides a video processing method, a video processing device and electronic equipment, so as to solve the problem that a large number of similar image blocks have the same hash value due to IBC coding, thereby reducing the coding speed.

In a first aspect, an embodiment of the present disclosure provides a video processing method, including:

in a preset coding mode, searching a second preset bit value corresponding to a first preset bit value in a preset pixel block information table according to the first preset bit value in a 32-bit cyclic redundancy check (crc) value of a target pixel block;

if the value of the searched second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block from the preset pixel block information table according to the value of the searched second preset bit;

performing a conversion between the target pixel block and a bit representation of the target pixel block according to coordinates of the reference pixel block.

In a second aspect, an embodiment of the present disclosure provides a video processing apparatus, including:

the searching module is used for searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table according to the first preset bit value in the 32-bit crc value of the target pixel block in a preset coding mode;

an obtaining module, configured to obtain, if the searched value of the second preset bit is the same as the second preset bit in the 32-bit crc value of the target pixel block, a coordinate of a reference pixel block from the preset pixel block information table according to the searched value of the second preset bit;

an encoding module to perform a conversion between the target pixel block and a bit representation of the target pixel block according to coordinates of the reference pixel block.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor and memory;

the memory stores computer-executable instructions;

the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the video processing method as set forth in the first aspect above and in various possible designs of the first aspect.

In a fourth aspect, the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the video processing method according to the first aspect and various possible designs of the first aspect are implemented.

The video processing method, the video processing device and the electronic equipment provided by the embodiment of the disclosure search the reference pixel block from the preset pixel block information table according to the 32-bit crc value of the target pixel block in the preset coding mode when the target pixel block is coded, acquire the coordinates of the reference pixel block, and further perform the conversion between the bit representations of the target pixel block and the target pixel block according to the coordinates of the reference pixel block, wherein for two blocks with different pixel values, the 32-bit crc value is completely different, so as to solve the problem that a large number of similar image blocks have the same hash value due to IBC coding, thereby reducing the coding speed, in addition, when the reference pixel block is searched, segment search is performed in the preset pixel block information table according to the value of the first preset bit and the value of the second preset bit in the 32-bit crc value of the target pixel block, therefore, the preset pixel block information table can store the information in a segmented mode, the storage space is saved, and the method is suitable for practical application.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic diagram of a video processing system according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a video processing method according to an embodiment of the disclosure;

fig. 3 is a schematic flow chart of another video processing method according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart of another video processing method according to an embodiment of the disclosure;

fig. 5 is a schematic flowchart of another video processing method according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart of another video processing method according to an embodiment of the present disclosure;

fig. 7 is a schematic flowchart of another video processing method according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another video processing apparatus according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The nouns to which this disclosure relates will be explained first:

video coding: generally refers to processing a sequence of pictures forming a video or video sequence. In the field of video coding, the terms "piCTUre", "frame" or "image" may be used as synonyms. Video encoding in the present disclosure is performed on the source side, typically including processing (e.g., by compressing) the original video picture to reduce the amount of data needed to represent the video picture (and thus more efficiently store and/or transmit). Video decoding is performed at the destination side, typically involving inverse processing with respect to the encoder, to reconstruct the video pictures.

As used in this disclosure, the term "block" may be a portion of a picture or frame. For ease of description, embodiments of the present disclosure are described with reference to multipurpose Video Coding (VVC) or High-Efficiency Video Coding (HEVC) developed by the Joint working Group of Video Coding Experts Group (VCEG) and the MPEG Video Coding of the ISO/IEC Moving PiCTUre Experts Group (MPEG) for High Efficiency Video Coding (HEVC). In HEVC, a Coding tree Unit is split into multiple Coding units (Coding units, abbreviated CUs) by using a quadtree structure represented as a Coding tree. The CU, i.e. the coding unit, usually corresponds to an a × B rectangular region, and includes a × B luminance pixels and its corresponding chrominance pixels, where a is the width of the rectangle, B is the height of the rectangle, a and B may be the same or different, and a and B usually take a value to an integer power of 2, e.g. 128, 64, 32, 16, 8, 4. An encoding unit can decode to obtain a reconstructed image of an A × B rectangular region through decoding processing, wherein the decoding processing generally comprises prediction, inverse quantization, inverse transformation and the like, predicted images and residual errors are generated, and the predicted images and the residual errors are superposed to obtain the reconstructed image. CTUs, i.e. coding tree units, an image is composed of a plurality of CTUs, one CTU generally corresponds to a square image area, and contains luminance pixels and chrominance pixels (or may contain only luminance pixels, or may contain only chrominance pixels) in the image area; syntax elements are also included in the CTU that indicate how to divide the CTU into at least one CU and the method of decoding each coding unit resulting in a reconstructed picture.

The existing screen video content is the video content directly captured in the image display of the terminal such as computer, mobile phone, etc., and mainly comprises computer graphics, text documents, mixed images of natural video and graphics and text, computer generated images, etc. In the related art, the hevc scc proposes an expansion proposal for screen video content on the hevc/h.265. The hevc scc coders have IBCs. There is a large amount of repeated content in the on-screen video content, such as text icons and the like. When encoding a current block, performing a conventional motion search method cannot accurately find a perfectly matched reference block. If the IBC is adopted to search the matched blocks in the screen content, if the matched reference blocks can be searched, the residual error is almost zero, and the compression efficiency is greatly improved.

However, IBC is based on gradient calculation of image blocks, and a large number of similar image blocks have the same hash value, so that when a reference block is subsequently searched according to the hash value, more reference blocks are searched, and the searched reference block needs to be further processed to determine a final reference block, thereby reducing the encoding speed. Exemplary, IBC: for an 8x8 coded block:

H＝MSB(dc0,3)<<13+MSB(dc1,3)<<10+MSB(dc2,3)<<7+MSB(dc3,3)<<4+MSB(Grad,4)

where H is the resulting hash value to be calculated, for a total of 16 bits. MSB (val, n) refers to the highest n bits of val. < < denotes a left shift. DC 0-3 represents the DC value, or pixel mean, of four 4x4 subblocks. And Grad represents the average of the gradient values in the horizontal and vertical directions.

Therefore, in view of the above problems, the present disclosure provides a video processing method, by searching a reference pixel block from a preset pixel block information table according to a 32-bit crc value of a target pixel block in a preset coding mode when coding the target pixel block, and acquiring coordinates of the reference pixel block, and further performing conversion between bit representations of the target pixel block and the target pixel block according to the coordinates of the reference pixel block, wherein 32-bit crc values are completely different for two blocks having a difference in pixel value, thereby solving a problem that IBC coding causes a large number of similar image blocks to have the same hash value, thereby reducing coding speed, and further, when searching the reference pixel block, performing a segment search in the preset pixel block information table according to a value of a first preset bit and a value of a second preset bit among the 32-bit crc values of the target pixel block, therefore, the preset pixel block information table can store the information in a segmented mode, the storage space is saved, and the method is suitable for practical application.

A video processing method provided by the present disclosure may be applied to the video processing system architecture diagram shown in fig. 1, as shown in fig. 1, a video processing system 10 includes a source device 12 and a target device 14, where the source device 12 includes: picture taking means 121, a pre-processor 122, an encoder 123 and a communication interface 124. The target device 14 includes: display device 141, processor 142, decoder 143, and communication interface 144. The source device 12 transmits the encoded data 13 obtained by the encoding to the target device 14. The method of the present disclosure is applied to the encoder 123.

Source device 12 may be referred to herein as a video encoding device or a video encoding apparatus. The target device 14 may be referred to as a video decoding device or video decoding apparatus. Source device 12 and destination device 14 may be examples of video encoding devices or video encoding apparatus.

Source device 12 and target device 14 may comprise any of a variety of devices, including any type of handheld or stationary device, such as a notebook or laptop computer, a mobile phone, a smart phone, a tablet or tablet computer, a camcorder, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiver device, a broadcast transmitter device, etc., and may not use or use any type of operating system.

In some cases, source device 12 and target device 14 may be equipped for wireless communication. Thus, source device 12 and target device 14 may be wireless communication devices.

In some cases, the video processing system 10 shown in fig. 1 is merely an example, and the techniques of this disclosure may be applied to video encoding settings (e.g., video encoding or video decoding) that do not necessarily involve any data communication between the encoding and decoding devices. In other examples, the data may be retrieved from local storage, streamed over a network, and so on. A video encoding device may encode and store data to a memory, and/or a video decoding device may retrieve and decode data from a memory. In some examples, the encoding and decoding are performed by devices that do not communicate with each other, but merely encode data to and/or retrieve data from memory and decode data.

In some cases, encoder 123 of video processing system 10 may also be referred to as a video encoder and decoder 143 may also be referred to as a video decoder.

In some cases, picture taking apparatus 121 may include or may be any type of picture capturing device, for example, a device for capturing a real-world picture, and/or any type of picture or comment generation device (for screen content encoding, some text on the screen is also considered part of the picture or image to be encoded), such as a computer graphics processor for generating a computer animation picture, or any type of device for obtaining and/or providing a real-world picture, a computer animation picture (e.g., screen content, a Virtual Reality (VR) picture), and/or any combination thereof (e.g., an Augmented Reality (AR) picture). Wherein a picture is or can be seen as a two-dimensional array or matrix of sample points having intensity values. Taking an array as an example, a sampling point in the array may also be called a pixel (pel) or a pixel (pel). The number of sampling points of the array in the horizontal and vertical directions (or axes) defines the size and/or resolution of the picture. To represent color, three color components are typically employed, i.e., a picture may be represented as or contain three sample arrays. In the RBG format or color space, a picture includes corresponding red, green, and blue sampling arrays. However, in video coding, each pixel is typically represented in a luminance/chrominance format or color space, e.g., YCbCr, comprising a luminance (briefly luma) component, indicated by Y (sometimes also indicated by L), and two chrominance (briefly chroma) components, indicated by Cb and Cr. The luminance component Y represents luminance or gray level intensity (e.g., both are the same in a gray scale picture), while the two chrominance components Cb and Cr represent chrominance or color information components. Accordingly, a picture in YCbCr format includes a luminance sample array for the luminance component (Y), and two chrominance sample arrays for the chrominance components (Cb and Cr). Pictures in RGB format may be converted or transformed into YCbCr format and vice versa, a process also known as color transformation or conversion.

Further, the picture taking means 121 may be, for example, a camera for capturing pictures, a memory, such as a picture memory, comprising or storing previously captured or generated pictures, and/or any kind of (internal or external) interface for taking or receiving pictures. Where the camera may be, for example, an integrated camera local or integrated in the source device, the memory may be an integrated memory local or integrated in the source device, for example. The interface may be, for example, an external interface that receives pictures from an external video source, where the external video source is, for example, an external picture capturing device such as a camera, an external memory, or an external picture generating device, for example, an external computer graphics processor, computer, or server. Further, the interface may be any kind of interface according to any proprietary or standardized interface protocol, e.g. a wired or wireless interface, an optical interface. The interface for obtaining the picture data 125 in fig. 1 may be the same interface as the communication interface 124 or may be part of the communication interface 124. Picture data 125 (e.g., video data) may be referred to as raw pictures or raw picture data, among others.

In some cases, pre-processor 122 is to receive picture data 125 and perform pre-processing on picture data 125 to obtain a pre-processed picture (or pre-processed picture data) 126. Among other things, the pre-processing performed by the pre-processor 122 may include trimming, color format conversion (e.g., from RGB to YCbCr), toning, or denoising. It is to be appreciated that the preprocessor 122 can be an optional component.

In some cases, encoder 123 (e.g., a video encoder) is used to receive a preprocessed picture (or preprocessed picture data) 126 and provide encoded picture data 127.

In some cases, communication interface 124 of source device 12 may be used to receive encoded picture data 127 and transmit to other devices, e.g., target device 14 or any other device for storage or direct reconstruction, or to process encoded picture data 127 prior to correspondingly storing encoded data 13 and/or transmitting encoded data 13 to other devices, e.g., target device 14 or any other device for decoding or storage. Communication interface 144 of target device 14 is used, for example, to receive encoded picture data 127 or encoded data 13 directly from source device 12 or any other source, such as a storage device, such as an encoded picture data storage device.

Communication interface 124 and communication interface 144 may be used, among other things, to transmit or receive encoded picture data 127 or encoded data 13 via a direct communication link between source device 12 and target device 14, such as a direct wired or wireless connection, or via any type of network, such as a wired or wireless network or any combination thereof, or any type of private and public networks, or any combination thereof. The communication interface 124 may, for example, be used to encapsulate the encoded picture data 127 into a suitable format, such as a packet, for transmission over a communication link or communication network. Communication interface 144, which forms a corresponding part of communication interface 124, may be used, for example, to decapsulate encoded data 13 to obtain encoded picture data 127. Both communication interface 124 and communication interface 144 may be configured as a one-way communication interface, as indicated by the arrow pointing from source device 12 to destination device 14 for encoded picture data 127 in fig. 1, or as a two-way communication interface, and may be used, for example, to send and receive messages to establish a connection, acknowledge, and exchange any other information related to a communication link and/or data transmission, such as an encoded picture data transmission.

In some cases, decoder 143 is used to receive encoded picture data 127 and provide decoded picture data (or decoded picture) 145.

In some cases, processor 142 of target device 14 is used to post-process decoded picture data (or decoded picture) 145, e.g., a decoded picture, to obtain post-processed picture data 146, e.g., a post-processed picture. Post-processing performed by processor 142 may include, for example, color format conversion (e.g., from YCbCr to RGB), toning, cropping, or resampling, or any other processing, for example, to prepare decoded picture data (or decoded pictures) 145 for display by display device 141.

In some cases, display device 141 of target device 14 is used to receive post-processed picture data 145 to display a picture to, for example, a user or viewer. Display device 141 may be or may include any type of display for presenting the reconstructed picture, such as an integrated or external display or monitor. For example, the display may include a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), a Digital Light Processor (DLP), or any other type of display.

Additionally, although fig. 1 depicts source device 12 and target device 14 as separate devices, device embodiments may also include the functionality of both source device 12 and target device 14 or both, i.e., source device 12 or corresponding functionality and target device 14 or corresponding functionality. In such embodiments, the source device 12 or corresponding functionality and the target device 14 or corresponding functionality may be implemented using the same hardware and/or software, or using separate hardware and/or software, or any combination thereof. The existence and (exact) division of functionality of different elements or of source device 12 and/or target device 14 shown in fig. 1 may vary depending on the actual device and application.

In some cases, encoder 123 (e.g., a video encoder) and decoder 143 (e.g., a video decoder) may each be implemented as any of a variety of suitable circuitry, such as one or more microprocessors, Digital Signal Processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, or any combination thereof. If the techniques are implemented in part in software, an apparatus may store instructions of the software in a suitable non-transitory computer-readable storage medium and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered one or more processors. Each of the encoder 123 and decoder 143 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (codec) in the corresponding device.

It will be appreciated that for each of the examples described above with reference to the encoder 123, the decoder 143 may be used to perform the reverse process. With respect to signaling syntax elements, decoder 143 may be configured to receive and parse such syntax elements and decode the associated video data accordingly. In some examples, the encoder 123 may entropy encode the one or more defined syntax elements into an encoded video bitstream. In such instances, decoder 143 may parse such syntax elements and decode the relevant video data accordingly.

The following describes the technical solutions of the present disclosure and how to solve the above technical problems in specific embodiments. The following specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

Fig. 2 is a flowchart illustrating a video processing method according to an embodiment of the present disclosure, where an execution subject of the embodiment of the present disclosure may be an encoder in the foregoing embodiment. As shown in fig. 2, the method may include:

s201: in the preset coding mode, according to the value of a first preset bit in the 32-bit crc value of the target pixel block, searching a second preset bit value corresponding to the value of the first preset bit in a preset pixel block information table.

The target pixel blocks may be determined according to actual conditions, and the comparison in the embodiments of the present disclosure is not particularly limited.

Here, the preset encoding mode may be an IBC encoding mode, a hashme encoding mode, or the like. The first preset bit and the second preset bit may be set according to actual conditions, for example, the upper 16 bits of the 32-bit crc value are used as the first preset bit, and the lower 16 bits of the 32-bit crc value are used as the second preset bit.

The preset pixel block information table may pre-store a corresponding relationship between a value of a first preset bit and a value of a second preset bit among 32-bit crc values of the plurality of pixel blocks, and a coordinate of the pixel block.

Taking IBC encoding mode as an example, the value of a first predetermined bit in the 32-bit crc value of the target pixel block is searched for a value of a second predetermined bit corresponding to the value of the first predetermined bit in the correspondence relationship of the predetermined pixel block information table.

In addition, the above-mentioned 32-bit crc value may be a fastcrc32 value.

S202: and if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit.

Here, if a value of a second preset bit corresponding to the value of the first preset bit is searched in the preset pixel block information table, and the searched value of the second preset bit is the same as the value of the second preset bit among the 32-bit crc values of the target pixel block, the coordinates of the reference pixel block are further obtained from the preset pixel block information table according to the searched value of the second preset bit.

If the value of the second preset bit corresponding to the value of the first preset bit is not searched in the preset pixel block information table, or the value of the searched second preset bit is different from the value of the second preset bit in the 32-bit crc value of the target pixel block, corresponding prompting is carried out, and the steps can be executed in other preset coding modes until the coordinates of the reference pixel block are obtained.

S203: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

Wherein the target pixel block is encoded by converting the bit representation of the target pixel block into a target pixel block, and the target pixel block is decoded by converting the bit representation of the target pixel block into a target pixel block.

Illustratively, if the encoding mode is an IBC encoding mode, the conversion between the bit representations of the target pixel block and the target pixel block is performed according to the coordinates of the reference pixel block. If the coding mode cannot be the IBC mode, a hash coding mode can be tried, in the hash coding mode, according to the value of a first preset bit in the 32-bit crc value of the target pixel block, searching a value of a second preset bit corresponding to the value of the first preset bit in a preset pixel block information table, if the value of the searched second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, according to the value of the searched second preset bit, obtaining the coordinate of a reference pixel block from the preset pixel block information table, and according to the coordinate of the reference pixel block, performing conversion between bit representations of the target pixel block and the target pixel block, and the like.

As can be seen from the above description, in the present disclosure, when encoding a target pixel block, in a preset encoding mode, according to a 32-bit crc value of the target pixel block, a reference pixel block is searched from a preset pixel block information table, and coordinates of the reference pixel block are obtained, and further, conversion between bit representations of the target pixel block and the target pixel block is performed according to the coordinates of the reference pixel block, where, for two blocks having a difference in pixel value, the 32-bit crc value is completely different, so as to solve a problem that IBC encoding causes a large number of similar image blocks to have the same hash value, thereby reducing an encoding speed, and in addition, in searching the reference pixel block, a segment search is performed in the preset pixel block information table according to a value of a first preset bit and a value of a second preset bit in the 32-bit crc value of the target pixel block, thereby enabling the preset pixel block information table to store information in segments, saving storage space and being suitable for practical application.

In addition, before searching the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit, the embodiment of the present disclosure may further determine the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, and obtain the 32-bit crc value of the target pixel block therefrom. Fig. 3 is a flowchart illustrating another video processing method according to an embodiment of the disclosure, where an execution subject of the embodiment may be an encoder in the embodiment shown in fig. 1. As shown in fig. 3, the method includes:

s301: a 32-bit crc value for the pixel block of each pixel position of the luminance component of the coding tree unit to be processed is determined.

The coding tree unit to be processed may be determined according to actual conditions, and the comparison in the embodiments of the present disclosure is not particularly limited.

Illustratively, the 32-bit crc value for each pixel block, e.g., an 8 × 8 pixel block, at each pixel position of the current CTU luma component is computed prior to encoding the CTU, thereby obtaining the 32-bit crc value for the target pixel block from the computed 32-bit crc values for the pixel blocks.

Optionally, the determining the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed may include:

and carrying out parallel processing on the pixel values of the pixel blocks at each pixel position of the brightness components of the coding tree unit to be processed to obtain 32-bit crc values of the pixel blocks at each pixel position of the brightness components of the coding tree unit to be processed.

In addition, the determining the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed may further include:

merging the pixel values of the pixel blocks at each pixel position of the brightness components of the coding tree unit to be processed to obtain 32-bit pixel values;

and obtaining the 32-bit crc value of the pixel block of each pixel position of the brightness component of the coding tree unit to be processed by adopting a calculation function of the 32-bit crc value according to the 32-bit pixel value.

Here, the 32-bit crc value of the coding tree unit to be processed may be calculated in parallel, and/or the pixel values may be combined during the calculation process, so as to increase the calculation speed and, therefore, the coding speed.

The calculation function of the 32-bit crc value may be determined according to actual conditions, and the comparison in the embodiments of the present disclosure is not particularly limited. For example, in some cases, the above-described calculation function for the 32-bit crc value may be x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+¹。

Here, the obtaining of the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed may include:

obtaining a 32-bit crc value to be processed by adopting a calculation function of the 32-bit crc value according to the 32-bit pixel value;

and obtaining the 32-bit crc value of the pixel block of each pixel position of the brightness component of the coding tree unit to be processed by adopting a random calculation function according to the 32-bit crc value to be processed.

The random calculation function may also be determined according to actual conditions, and the comparison in the embodiments of the present disclosure is not particularly limited.

Here, for two blocks having different pixel values, different 32-bit crc values to be processed can be obtained by using the above calculation function of the 32-bit crc value. However, considering that the 32-bit crc value is segmented in the subsequent processing, for example, when the reference pixel block is searched subsequently, a segmentation search is performed in the preset pixel block information table according to the value of the first preset bit and the value of the second preset bit in the 32-bit crc value of the target pixel block, and the segmented crc values may be the same. In order to solve the problem, the embodiment of the present disclosure further uses a random calculation function to obtain the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed based on the 32-bit crc value to be processed, and after subsequent segmentation processing, the 32-bit crc values of the two blocks with different pixel values are different, and further, normal subsequent processing is ensured.

Illustratively, taking the calculation of a 32-bit crc value for an 8 × 8 pixel block as an example, the following operations may be included:

(1) for an 8 × 8 pixel block, 64 pixels are provided, each pixel value is 8 bits, and each 4 pixels are combined in a group, that is, 4 8-bit pixel values are combined to obtain a 32-bit value, and finally a 16-bit value buf [ i ] (i is 0,1 … 15). In the subsequent steps, the final 32-bit crc value is represented by p, with 32 bits, and the initial value is set to 0.

(2) For each buf [ i ], p ═ f (p, buf [ i ]) is performed until 16 iterative computations are completed, where f is a computation function of the 32-bit crc value.

(3) A random computation, p ═ rand (p), is performed, where rand is a random computation function.

Here, the pixel values of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed may be processed in parallel to obtain a 32-bit crc value of the pixel block at each pixel position, wherein the specific steps of each process may be as described in (1) to (3) above, thereby increasing the calculation speed and, in turn, the coding speed. The parallel processing can be realized by Single Instruction Multiple Data (SIMD for short) vector parallel computation, the embodiment of the present disclosure is realized by performing SIMD of armv7 armv8 sse avx2, and taking avx2 of 256 bits as an example, for a row of pixel points a [ i ] (i ═ 0 … 31), a avx2 register performs steps (1) - (3), and 32-bit crc values at four positions of a [0] a [8] a [16] a [24] can be completed in parallel.

S302: and acquiring the 32-bit crc value of the target pixel block from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed.

S303: in the preset coding mode, according to the value of a first preset bit in the 32-bit crc value of the target pixel block, searching a second preset bit value corresponding to the value of the first preset bit in a preset pixel block information table.

S304: and if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit.

S305: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

The steps S303 to S305 are the same as the steps S201 to S203, and are not described herein again.

The video processing method provided by the embodiment of the disclosure increases the speed of calculating the 32-bit crc value of the coding tree unit to be processed by parallel calculation and/or combining the pixel values in the calculation process, further increases the coding speed, and, when coding a target pixel block, searches a reference pixel block from a preset pixel block information table according to the 32-bit crc value of the target pixel block in a preset coding mode, and obtains the coordinates of the reference pixel block, and further performs conversion between bit representations of the target pixel block and the target pixel block according to the coordinates of the reference pixel block, wherein, for two blocks with difference pixel values, the 32-bit crc value is completely different, thereby solving the problem that a large number of similar image blocks have the same hash value due to IBC coding, thereby reducing the coding speed, and in addition, when searching the reference pixel block, and carrying out segmentation search in the preset pixel block information table according to the value of the first preset bit and the value of the second preset bit in the 32-bit crc value of the target pixel block, so that the preset pixel block information table can store information in a segmentation manner, the storage space is saved, and the method is suitable for practical application.

In addition, before searching the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit, the embodiment of the present disclosure may also store the value of the first preset bit and the value of the second preset bit in the 32-bit crc values of the pixel block, and the coordinates of the pixel block in the preset pixel block information table. Fig. 4 is a flowchart illustrating another video processing method according to an embodiment of the disclosure, where an execution subject of the embodiment may be an encoder in the embodiment shown in fig. 1. As shown in fig. 4, the method includes:

s401: a 32-bit crc value for the pixel block of each pixel position of the luminance component of the coding tree unit to be processed is determined.

Step S401 is the same as the implementation of step S301, and is not described herein again.

S402: and respectively acquiring a value of a first preset bit and a value of a second preset bit from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed, and determining the coordinate of the corresponding pixel block.

Here, the value of the first preset bit and the value of the second preset bit obtained as described above are represented correspondingly, and the determined coordinates of the pixel block are information of the same pixel block.

S403: and storing the obtained value of the first preset bit, the obtained value of the second preset bit and the determined coordinates of the corresponding pixel block in a preset pixel block information table.

Here, the above-mentioned pixel block information table may be pre-established, and a correspondence relationship of a value of a first preset bit, a value of a second preset bit, and coordinates of pixel blocks among 32-bit crc values of a plurality of pixel blocks may be pre-stored in the pixel block information table.

After the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed is determined, the value of the first preset bit and the value of the second preset bit are respectively obtained from the 32-bit crc value, the coordinate of the corresponding pixel block is determined, the hash table is updated, and then corresponding information can be directly obtained from the preset pixel block information table in subsequent video processing, so that repeated calculation is reduced.

S404: and acquiring the 32-bit crc value of the target pixel block from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed.

S405: in a preset coding mode, according to the value of a first preset bit in the 32-bit crc value of the target pixel block, searching a preset pixel block information table for the value of a second preset bit corresponding to the value of the first preset bit.

S406: and if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit.

S407: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

The steps S405 to S407 are the same as the steps S303 to S305, and are not described herein again.

The video processing method provided by the embodiment of the disclosure can directly acquire corresponding information from the information table by establishing the preset pixel block information table, reduce repeated calculation, and, when encoding the target pixel block, search the reference pixel block from the preset pixel block information table according to the 32-bit crc value of the target pixel block in the preset encoding mode, and acquire the coordinates of the reference pixel block, and further perform conversion between bit representations of the target pixel block and the target pixel block according to the coordinates of the reference pixel block, wherein, for two blocks with different pixel values, the 32-bit crc value is completely different, thereby solving the problem that a large number of similar image blocks have the same hash value due to IBC encoding, and thus reducing the encoding speed, in addition, when searching the reference pixel block, according to the value of the first preset bit and the value of the second preset bit in the 32-bit crc value of the target pixel block, and the preset pixel block information table is subjected to segmented search, so that the preset pixel block information table can store information in a segmented manner, the storage space is saved, and the method is suitable for practical application.

In addition, the embodiment of the present disclosure can also determine the number of searches before searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table. Fig. 5 is a flowchart illustrating another video processing method according to an embodiment of the disclosure, where an execution subject of the embodiment may be an encoder in the embodiment shown in fig. 1. As shown in fig. 5, the method includes:

s501: and judging whether the number of times of searching the second preset bit value corresponding to the first preset bit value in the preset pixel block information table reaches a preset searching number upper limit or not.

S502: if the number of times does not reach the upper limit of the preset search number of times, searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table according to the value of the first preset bit in the 32-bit crc value of the target pixel block in a preset coding mode.

The preset upper limit of the search times may be set according to an actual situation, and is not particularly limited in the embodiment of the present disclosure.

Before searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table, judging whether the searching frequency reaches a preset searching frequency upper limit, if so, stopping searching, and otherwise, performing corresponding searching.

The problems of excessive search times and low coding speed in the prior art are solved by setting the upper limit of the preset search times.

S503: and if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit.

S504: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

The implementation of steps S502 to S504 is the same as that of steps S201 to S203, and is not described herein again.

The video processing method provided by the embodiment of the disclosure solves the problems of excessive searching times and low coding speed by setting a preset upper limit of searching times, and when a target pixel block is coded, a reference pixel block is searched from a preset pixel block information table according to 32-bit crc values of the target pixel block in a preset coding mode, coordinates of the reference pixel block are obtained, and further, conversion between bit representations of the target pixel block and the target pixel block is performed according to the coordinates of the reference pixel block, wherein for two blocks with different pixel values, the 32-bit crc values are completely different, and further the problem that a large number of similar image blocks have the same hash value due to IBC coding is solved, so that the coding speed is reduced, in addition, when the reference pixel block is searched, according to the value of a first preset bit and the value of a second preset bit in the 32-bit crc values of the target pixel block, and the preset pixel block information table is subjected to segmented search, so that the preset pixel block information table can store information in a segmented manner, the storage space is saved, and the method is suitable for practical application.

In addition, the embodiment of the present disclosure can also acquire the coordinates of the reference pixel block from the preset pixel block information table according to the corresponding cost. Fig. 6 is a flowchart illustrating another video processing method according to an embodiment of the disclosure, where an execution subject of the embodiment may be an encoder in the embodiment shown in fig. 1. As shown in fig. 6, the method includes:

s601: in the preset coding mode, according to the value of a first preset bit in the 32-bit crc value of the target pixel block, searching a second preset bit value corresponding to the value of the first preset bit in a preset pixel block information table.

Step S601 is the same as the implementation of step S201, and is not described herein again.

S602: and if the value of the searched second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, respectively determining the cost value between the target pixel block and the pixel block to be processed which is corresponding to the value of the searched second preset bit and belongs to the preset pixel block information table.

S603: and acquiring a pixel block corresponding to the minimum value of the cost value from the pixel blocks to be processed as a reference pixel block, and acquiring the coordinates of the reference pixel block from the preset pixel block information table.

Here, cost values between pixel blocks to be processed, which correspond to values of second preset bits searched by the target pixel block and belong to the preset pixel block information table, are respectively calculated, where the cost values may be rate distortion costs (rdcosts), and thus, a pixel block corresponding to a minimum value of the cost values obtained from the pixel blocks to be processed is used as a reference pixel block, and an optimal reference pixel block is found, so that a residual error is almost zero, and compression efficiency is greatly improved.

S604: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

Step S604 is the same as the step S203, and is not described herein again.

The video processing method provided by the embodiment of the disclosure can search a matched reference block to make a residual error almost zero, thereby greatly improving compression efficiency, and in addition, when a target pixel block is encoded, in a preset encoding mode, according to a 32-bit crc value of the target pixel block, a reference pixel block is searched from a preset pixel block information table, and coordinates of the reference pixel block are obtained, and further, conversion between bit representations of the target pixel block and the target pixel block is performed according to the coordinates of the reference pixel block, wherein for two blocks with different pixel values, the 32-bit crc value is completely different, thereby solving the problem that a large number of similar image blocks have the same hash value due to IBC encoding, thereby reducing encoding speed, in addition, when the reference pixel block is searched, according to a first preset bit value and a second preset bit value in the 32-bit crc value of the target pixel block, and the preset pixel block information table is subjected to segmented search, so that the preset pixel block information table can store information in a segmented manner, the storage space is saved, and the method is suitable for practical application.

In addition, the preset pixel block information table is a hash table, and the hash table takes the value of the first preset bit in the 32-bit crc value of the pixel block as key, and takes the value of the second preset bit in the 32-bit crc value of the pixel block and the coordinate of the pixel block as value. The embodiment of the present disclosure can also search the hash table for a value of a second preset bit corresponding to the value of the first preset bit. Fig. 7 is a flowchart illustrating another video processing method according to an embodiment of the disclosure, where an execution subject of the embodiment may be an encoder in the embodiment shown in fig. 1. As shown in fig. 7, the method includes:

s701: in the preset coding mode, the value corresponding to the search key is searched in the hash table by taking the value of the first preset bit in the 32-bit crc value of the target pixel block as the search key.

S702: and if the value of the second preset bit in the value corresponding to the searched search key is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block in the value corresponding to the search key.

Here, the above-described hash table, which is a data structure directly accessed according to a Key value (Key value), may be set every frame. The key is the value of the first preset bit in the 32-bit crc value of the pixel block, and the value is the value of the second preset bit in the 32-bit crc value of the pixel block and the pixel block. One key may correspond to multiple values, linked by a linked list.

In the above process of obtaining the coordinates of the reference pixel block, the value of the first preset bit in the 32-bit crc value of the target pixel block is first used as a search key, the search key is looked up in the hash table, if the search key can be found, the header of the value linked list is obtained, the value linked list is traversed, a value in which the value of the second preset bit in the value is equal to the second bit in the 32-bit crc value of the target pixel block is found, the coordinates of the reference pixel are obtained from the value, and then the conversion step between the bit representations of the target pixel block and the target pixel block can be executed. The hash table is established, so that corresponding information can be directly obtained from the hash table in subsequent video processing, and repeated calculation is reduced.

S703: the conversion between the bit representations of the target pixel block and the target pixel block is performed based on the coordinates of the reference pixel block.

Step S703 is the same as the implementation of step S203, and is not described herein again.

The video processing method provided by the embodiment of the disclosure can directly acquire corresponding information from the hash table by establishing the hash table, so as to reduce repeated calculation, and in addition, when a target pixel block is encoded, a reference pixel block is searched from a preset pixel block information table according to a 32-bit crc value of the target pixel block in a preset encoding mode, and coordinates of the reference pixel block are acquired, and further, conversion between bit representations of the target pixel block and the target pixel block is performed according to the coordinates of the reference pixel block, wherein for two blocks with different pixel values, the 32-bit crc value is completely different, so as to solve the problem that a large number of similar image blocks have the same hash value due to IBC encoding, so as to reduce encoding speed, and in addition, when the reference pixel block is searched, according to a first preset bit value and a second preset bit value in the 32-bit crc value of the target pixel block, and the preset pixel block information table is subjected to segmented search, so that the preset pixel block information table can store information in a segmented manner, the storage space is saved, and the method is suitable for practical application.

In addition, based on the IBC and hashme tools realized on the self-research project in the embodiment of the application, the bd-bitrate is about-30%, the coding time is + 30%, the coding efficiency is expected, and the complexity is far lower than that of the original scheme.

Fig. 8 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present disclosure, corresponding to the video processing method according to the foregoing embodiment. For ease of illustration, only portions that are relevant to embodiments of the present disclosure are shown. Fig. 8 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present disclosure. As shown in fig. 7, the video processing apparatus 80 includes: a search module 801, an obtaining module 802 and an encoding module 803.

The searching module 801 is configured to search, in a preset coding mode, a preset pixel block information table for a value of a second preset bit corresponding to a value of the first preset bit according to a value of the first preset bit in the 32-bit crc value of the target pixel block.

An obtaining module 802, configured to, if the searched value of the second preset bit is the same as the second preset bit in the 32-bit crc value of the target pixel block, obtain the coordinate of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit.

An encoding module 803 for performing a conversion between the target pixel block and the bit representation of the target pixel block according to the coordinates of the reference pixel block.

The apparatus provided in the embodiment of the present disclosure may be configured to implement the technical solution of the method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again in the embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of another video processing apparatus according to an embodiment of the present disclosure. As shown in fig. 9, the embodiment of the present disclosure further includes, on the basis of the embodiment of fig. 8: a determination module 804, an acquisition module 805, and a save module 806.

In a possible design, the determining module 804 is configured to determine a 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed before the searching module 801 searches the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit;

an obtaining module 805, configured to obtain a 32-bit crc value of the target pixel block from 32-bit crc values of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed.

In one possible design, the determining module 804 is specifically configured to:

and carrying out parallel processing on the pixel value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed to obtain a 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed.

In one possible design, the determining module 804 obtains a 32-bit crc value of a pixel block of each pixel position of a luminance component of the coding tree unit to be processed, including:

In a possible design, the saving module 806 is configured to, after the determining module 804 determines the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, obtain the value of the first preset bit and the value of the second preset bit from the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, respectively, and determine the coordinates of the corresponding pixel block; and storing the obtained values of the first preset bit and the second preset bit and the determined coordinates of the corresponding pixel blocks in the preset pixel block information table.

In one possible design, before the searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table, the searching module 801 is further configured to:

judging whether the number of times of searching the second preset bit value corresponding to the first preset bit value in the preset pixel block information table reaches a preset search number upper limit or not;

and if the number of times does not reach the upper limit of the preset search number of times, executing the step of searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table.

In one possible design, the obtaining module 802 is specifically configured to:

respectively determining cost values between the target pixel block and the searched pixel block to be processed corresponding to the second preset bit value and belonging to the preset pixel block information table;

and acquiring a pixel block corresponding to the minimum value of the cost value from the pixel block to be processed as the reference pixel block, and acquiring the coordinates of the reference pixel block from the preset pixel block information table.

In a possible design, the preset pixel block information table is a hash table, and the hash table takes a value of a first preset bit in the 32-bit crc values of the pixel block as key, and takes a value of a second preset bit in the 32-bit crc values of the pixel block and a coordinate of the pixel block as value.

The searching module 801 searches, according to a value of a first preset bit in the 32-bit crc value of the target pixel block, a preset pixel block information table for a value of a second preset bit corresponding to the value of the first preset bit, including:

taking the value of the first preset bit in the 32-bit crc value of the target pixel block as a search key, and searching a value corresponding to the search key in the hash table;

if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, the obtaining module 802 obtains the coordinates of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit, including:

and if the value of the second preset bit in the value corresponding to the searched search key is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinate of the reference pixel block in the value corresponding to the search key.

Referring to fig. 10, an electronic device 1000 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 1001 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1002 or a program loaded from a storage device 1008 into a Random Access Memory (RAM) 1003. In the RAM 1003, various programs and data necessary for the operation of the electronic apparatus 1000 are also stored. The processing device 1001, the ROM1002, and the RAM 1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

Generally, the following devices may be connected to the I/O interface 1005: input devices 1006 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 1007 including, for example, an LCD, a speaker, a vibrator, and the like; storage devices 1008 including, for example, magnetic tape, hard disk, and the like; and a communication device 1009. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data. While fig. 10 illustrates an electronic device 1000 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.

In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication means 1009, or installed from the storage means 1008, or installed from the ROM 1002. The computer program, when executed by the processing device 1001, performs the above-described functions defined in the methods of the embodiments of the present disclosure.

It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.

The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.

The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above embodiments.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of Network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of a unit does not in some cases constitute a limitation of the unit itself, for example, the first retrieving unit may also be described as a "unit for retrieving at least two internet protocol addresses".

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

In a first aspect, according to one or more embodiments of the present disclosure, there is provided a video processing method, including:

in a preset coding mode, searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table according to the first preset bit value in the 32-bit crc value of the target pixel block;

According to one or more embodiments of the present disclosure, before the searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table, the method further includes:

determining a 32-bit crc value of a pixel block of each pixel position of a luminance component of a coding tree unit to be processed;

and acquiring the 32-bit crc value of the target pixel block from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed.

According to one or more embodiments of the present disclosure, the determining a 32-bit crc value for a pixel block of each pixel position of a luma component of a coding tree unit to be processed comprises:

According to one or more embodiments of the present disclosure, the obtaining the 32-bit crc value of the pixel block of each pixel position of the luminance component of the coding tree unit to be processed includes:

According to one or more embodiments of the present disclosure, after the determining the 32-bit crc value of the pixel block of each pixel position of the luminance component of the coding tree unit to be processed, the method further includes:

respectively acquiring the value of the first preset bit and the value of the second preset bit from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed, and determining the coordinate of the corresponding pixel block;

storing the obtained values of the first preset bit and the second preset bit and the determined coordinates of the corresponding pixel blocks in the preset pixel block information table

According to one or more embodiments of the present disclosure, the obtaining coordinates of a reference pixel block from the preset pixel block information table according to the searched value of the second preset bit includes:

According to one or more embodiments of the present disclosure, the preset pixel block information table is a hash table, and a value of a first preset bit in 32-bit crc values of a pixel block and a value of a coordinate of the pixel block are taken as keys in the hash table;

searching a preset pixel block information table for a value of a second preset bit corresponding to the value of the first preset bit according to the value of the first preset bit in the 32-bit crc value of the target pixel block, including:

and taking the value of the first preset bit in the 32-bit crc value of the target pixel block as a search key, and searching the value corresponding to the search key in the hash table.

According to one or more embodiments of the present disclosure, if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinates of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit, includes:

In a second aspect, according to one or more embodiments of the present disclosure, there is provided a video processing apparatus including:

According to one or more embodiments of the present disclosure, the method further includes determining a 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed before the searching module searches the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit;

and the acquisition module is used for acquiring the 32-bit crc value of the target pixel block from the 32-bit crc value of the pixel block at each pixel position of the brightness component of the coding tree unit to be processed.

According to one or more embodiments of the present disclosure, the determining module is specifically configured to:

According to one or more embodiments of the present disclosure, the determining module obtains a 32-bit crc value for a pixel block of each pixel position of a luminance component of the coding tree unit to be processed, including:

According to one or more embodiments of the present disclosure, the apparatus further includes a saving module, configured to, after the determining module determines the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, obtain the value of the first preset bit and the value of the second preset bit from the 32-bit crc value of each pixel block at each pixel position of the luminance component of the coding tree unit to be processed, respectively, and determine the coordinates of the corresponding pixel block; and storing the obtained values of the first preset bit and the second preset bit and the determined coordinates of the corresponding pixel blocks in the preset pixel block information table.

According to one or more embodiments of the present disclosure, before the searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table, the searching module is further configured to:

judging whether the number of times of searching the second preset bit value corresponding to the first preset bit value in the preset pixel block information table reaches a preset search number upper limit or not; and if the number of times does not reach the upper limit of the preset search number of times, executing the step of searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table.

According to one or more embodiments of the present disclosure, the obtaining module is specifically configured to:

respectively determining cost values between the target pixel block and the searched pixel block to be processed corresponding to the second preset bit value and belonging to the preset pixel block information table; and acquiring a pixel block corresponding to the minimum value of the cost value from the pixel block to be processed as the reference pixel block, and acquiring the coordinates of the reference pixel block from the preset pixel block information table.

In a third aspect, according to one or more embodiments of the present disclosure, there is provided an electronic device including: at least one processor and memory;

the memory stores computer-executable instructions;

In a fourth aspect, according to one or more embodiments of the present disclosure, there is provided a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement the video processing method as set forth in the first aspect and various possible designs of the first aspect.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other embodiments in which any combination of the features described above or their equivalents does not depart from the spirit of the disclosure. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A video processing method, comprising:

in a preset coding mode, searching a second preset bit value corresponding to the first preset bit value in a preset pixel block information table according to the first preset bit value in the 32-bit cyclic redundancy check crc value of the target pixel block;

2. The method according to claim 1, further comprising, before the searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table:

3. The method of claim 2, wherein determining a 32-bit crc value for the pixel block at each pixel position of the luma component of the coding tree unit to be processed comprises:

4. The method of claim 2, wherein determining a 32-bit crc value for the pixel block at each pixel position of the luma component of the coding tree unit to be processed comprises:

5. The method of claim 4, wherein obtaining the 32-bit crc value for the pixel block at each pixel position of the luma component of the coding tree unit comprises:

6. The method of claim 2, further comprising, after said determining the 32-bit crc value for the pixel block for each pixel position of the luma component of the coding tree unit to be processed:

and storing the obtained values of the first preset bit and the second preset bit and the determined coordinates of the corresponding pixel blocks in the preset pixel block information table.

7. The method according to claim 1, further comprising, before the searching for the value of the second preset bit corresponding to the value of the first preset bit in the preset pixel block information table:

8. The method according to claim 1, wherein the obtaining the coordinates of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit comprises:

9. The method according to claim 1, wherein the predetermined pixel block information table is a hash table, and the hash table takes a value of a first predetermined bit of the 32-bit crc values of the pixel block as key, and takes a value of a second predetermined bit of the 32-bit crc values of the pixel block and coordinates of the pixel block as value;

if the searched value of the second preset bit is the same as the value of the second preset bit in the 32-bit crc value of the target pixel block, obtaining the coordinates of the reference pixel block from the preset pixel block information table according to the searched value of the second preset bit, including:

10. A video processing apparatus, comprising:

11. The apparatus according to claim 10, further comprising a determining module, for determining a 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed before the searching module searches the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit;

12. The apparatus of claim 11, wherein the determining module is specifically configured to:

13. The apparatus of claim 11, wherein the determining module is specifically configured to:

14. The apparatus of claim 13, wherein the determining module obtains a 32-bit crc value for the pixel block for each pixel position of the luma component of the coding tree unit to be processed, comprises:

15. The apparatus according to claim 11, further comprising a saving module, configured to, after the determining module determines the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, obtain the value of the first preset bit and the value of the second preset bit from the 32-bit crc value of the pixel block at each pixel position of the luminance component of the coding tree unit to be processed, respectively, and determine the coordinates of the corresponding pixel block; and storing the obtained values of the first preset bit and the second preset bit and the determined coordinates of the corresponding pixel blocks in the preset pixel block information table.

16. The apparatus of claim 10, wherein the searching module, before searching the preset pixel block information table for the value of the second preset bit corresponding to the value of the first preset bit, is further configured to:

17. The apparatus according to claim 10, wherein the obtaining module is specifically configured to:

18. An electronic device, comprising: at least one processor and memory;

the memory stores computer-executable instructions;

the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the video processing method of any of claims 1 to 9.

19. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, implement the video processing method of any one of claims 1 to 9.