CN111245209B - Interference signal suppression circuit and electrical equipment - Google Patents
Interference signal suppression circuit and electrical equipment Download PDFInfo
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- CN111245209B CN111245209B CN202010060560.1A CN202010060560A CN111245209B CN 111245209 B CN111245209 B CN 111245209B CN 202010060560 A CN202010060560 A CN 202010060560A CN 111245209 B CN111245209 B CN 111245209B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
- H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
- H02M1/123—Suppression of common mode voltage or current
Abstract
The invention discloses an interference signal suppression circuit and electrical equipment. Wherein, this circuit includes: a first end of the first-stage filter capacitor is connected with a first terminal of the interference source, and a second end of the first-stage filter capacitor is connected with a second terminal of the interference source; the differential mode signal loop comprises a first differential mode coil, a second differential mode coil and a magnetic ring; the first differential mode coil is wound in a first winding area of the magnetic ring, and the input end of the first differential mode coil is connected to the first end of the primary filter capacitor; and the second differential mode coil is wound in a second winding area of the magnetic ring, the output end of the second differential mode coil is connected to the second end of the primary filter capacitor, and the output end of the first differential mode coil is connected with the input end of the second differential mode coil. By the invention, interference signals can be completely absorbed and eliminated.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an interference signal suppression circuit and electrical equipment.
Background
In modern power electronic frequency conversion technology, there are two parts of low voltage and high voltage. As the functions of electrical equipment are more and more complex, the types of power supplies of the low-voltage part are more and the power is higher. Meanwhile, the miniaturization requirement is improved, the integration level of the control panel is high, the density of devices is improved, and the devices are easy to interfere with each other. When the IGBT or MOS of the high-voltage part works, the on-off of the IGBT or MOS generates strong voltage type and current type interference signals. It is easily coupled to other circuits through parasitic capacitance and parasitic inductance to cause electromagnetic interference (EMI) problems. Once the electromagnetic interference is propagated to the common circuit, other electronic devices are easy to malfunction, and extremely serious results are generated.
In order to suppress the influence of high frequency signals on other electric appliances of the common circuit, passive filter devices such as a common mode choke coil and a capacitor are provided at the power supply port. These devices are only interference signal suppression devices, and generally can only reduce the amplitude of interference signals, smooth spikes to a certain extent, and reduce the slope of interference signals. But the interference signal cannot be completely suppressed or absorbed.
Aiming at the problem that electromagnetic interference signals generated inside electrical equipment in the prior art cannot be completely inhibited or absorbed, an effective solution is not provided at present.
Disclosure of Invention
The embodiment of the invention provides an interference signal suppression circuit and electrical equipment, and aims to solve the problem that electromagnetic interference signals generated inside the electrical equipment cannot be completely suppressed or absorbed in the prior art.
In order to solve the above technical problem, the present invention provides an interference signal suppressing circuit, connected to an interference source, wherein the circuit includes:
a first end of the first-stage filter capacitor is connected with a first terminal of the interference source, and a second end of the first-stage filter capacitor is connected with a second terminal of the interference source;
the differential mode signal loop comprises a first differential mode coil, a second differential mode coil and a magnetic ring;
the first differential mode coil is wound in a first winding area of the magnetic ring, and the input end of the first differential mode coil is connected to the first end of the primary filter capacitor;
the second differential mode coil is wound in a second winding area of the magnetic ring, the output end of the second differential mode coil is connected to the second end of the primary filter capacitor, and the output end of the first differential mode coil is connected with the input end of the second differential mode coil;
the differential mode signal loop is used for consuming differential mode interference signals generated by the interference source.
Further, the first winding area and the second winding area are symmetrical about a first axis of symmetry of the magnetic ring.
Further, the direction of the magnetic field generated by the current in the first differential mode coil is the same as the direction of the magnetic field generated by the current in the second differential mode coil.
Further, the differential mode signal loop further comprises:
and the secondary filter capacitor is connected between the output end of the first differential mode coil and the input end of the second differential mode coil in series and is used for rapidly absorbing the differential mode interference signal.
Further, the differential mode signal loop further comprises:
and the resistor is arranged at two ends of the secondary filter capacitor in parallel and is used for consuming the differential mode interference signal.
Further, the differential mode signal loop further comprises:
the first unidirectional conducting element is arranged between the first end of the primary filter capacitor and the first terminal of the interference source and used for preventing the differential mode interference signal from conducting along the direction from the first end of the primary filter capacitor to the first terminal of the interference source;
and the second one-way conduction element is arranged between the second end of the primary filter capacitor and the second terminal of the interference source and used for preventing the differential mode interference signal from conducting along the direction from the second end of the primary filter capacitor to the second terminal of the interference source.
Further, the first unidirectional conducting element and/or the second unidirectional conducting element is a diode.
Further, the differential mode signal loop further comprises:
the first voltage source is arranged at two ends of the first unidirectional conducting element in parallel and used for providing conducting voltage for two ends of the first unidirectional conducting element;
and the second voltage source is arranged at two ends of the second one-way conduction element in parallel and used for providing conduction voltage for two ends of the second one-way conduction element.
Further, the circuit further comprises: a first common mode choke coil and a second common mode choke coil;
the first common mode choke coil is wound in a third winding area of the magnetic ring, the input end of the first common mode choke coil is connected with the first end of the primary filter capacitor, and the output end of the first common mode choke coil is connected with a first pole terminal of a power bus;
the second common mode choke coil is wound in a fourth winding area of the magnetic ring, the input end of the second common mode choke coil is connected with the second end of the primary filter capacitor, and the output end of the second common mode choke coil is connected with a second pole terminal of the power bus; the third winding area and the fourth winding area are symmetrical about a second symmetry axis of the magnetic ring, and the second symmetry axis is not coincident with the first symmetry axis;
the direction of a magnetic field generated by the current in the first common mode choke coil and the direction of a magnetic field generated by the current in the second common mode choke coil are the same, and the direction of a magnetic field generated by the current in the first differential mode coil and the direction of a magnetic field generated by the current in the second differential mode coil are the same.
Further, the circuit further comprises:
a first common mode filter capacitor, a first end of which is connected between the output end of the first common mode choke coil and the first pole terminal of the power bus, and a second end of which is grounded;
and a second common mode filter capacitor having a first end connected between the output end of the second common mode choke coil and the second pole terminal of the power bus, and a second end grounded.
Further, the circuit further comprises:
and the first end of the LISN line impedance stabilizing network is connected with the output end of the first common mode choke coil, the second end of the LISN line impedance stabilizing network is connected with the output end of the second common mode choke coil, the third end of the LISN line impedance stabilizing network is connected with the first pole terminal of the power bus, and the fourth end of the LISN line impedance stabilizing network is connected with the second pole terminal of the power bus, so that the LISN line impedance stabilizing network is used for isolating power grid interference and providing stable test impedance.
The invention also provides electrical equipment which comprises an interference source, a power supply and the interference signal suppression circuit.
By applying the technical scheme of the invention, the interference signal is absorbed by the primary filter capacitor and is released into the differential mode signal loop, so that the interference signal is consumed in the differential mode signal loop, and the interference signal is completely absorbed.
Drawings
FIG. 1 is a block diagram of an interference signal suppression circuit according to an embodiment of the present invention;
fig. 2 is a schematic view of the structure of a magnetic ring and the direction of its magnetic field according to an embodiment of the present invention;
FIG. 3 is a block diagram of an interference signal suppression circuit according to another embodiment of the present invention;
FIG. 4 is a block diagram of an interference signal suppression circuit according to yet another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a magnet ring according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of the current in the conductive lines and the direction of the magnetic field inside the magnetic ring according to another embodiment of the present invention;
fig. 7 is a block diagram of an interference signal suppressing circuit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and "a plurality" typically includes at least two.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe differential mode coils in embodiments of the present invention, these differential mode coils should not be limited to these terms. These terms are only used to distinguish between differential mode coils wound at different locations around the magnetic loop. For example, a first differential mode coil may also be referred to as a second differential mode coil, and similarly, a second differential mode coil may also be referred to as a first differential mode coil, without departing from the scope of embodiments of the present invention.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
It is also noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in the article or device in which the element is included.
Alternative embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Example 1
The present embodiment provides an interference signal suppressing circuit, fig. 1 is a structural diagram of an interference signal suppressing circuit according to an embodiment of the present invention, and as shown in fig. 1, the circuit is connected to an interference source in an electrical device, and includes: a first-stage filter capacitor C1, where a first end of the first-stage filter capacitor C1 is connected to a first terminal of the interference source, and a second end of the first-stage filter capacitor C1 is connected to a second terminal of the interference source, where the number of the first-stage filter capacitors may be 1, or two or more, and when the number of the first-stage filter capacitors C1 is two or more, each first-stage filter capacitor C1 is connected in parallel and then connected in series between the first terminal and the second terminal of the interference source, in this embodiment, the first-stage filter capacitor C1 includes C1, C1 … C1N, and N first-stage filter capacitors.
The circuit also comprises a differential mode signal loop 11, wherein the differential mode signal loop comprises a first differential mode coil 111, a second differential mode coil 112 and a magnetic ring 113; the first differential mode coil 111 is wound in a first winding area of the magnetic ring 113, and the input end of the first differential mode coil is connected to the first end of the primary filter capacitor C1; the second differential mode coil 112 is wound in the second winding area of the magnetic ring 113, an output end of the second differential mode coil 112 is connected to the second end of the primary filter capacitor C1, an output end of the first differential mode coil 111 is connected to an input end of the second differential mode coil 112, and the differential mode signal loop is configured to consume a differential mode interference signal DM generated by an interference source.
Fig. 2 is a schematic diagram of a structure of a magnetic ring and a magnetic field direction thereof according to an embodiment of the present invention, as shown in fig. 2, the magnetic ring is a hollow annular magnetic core having at least one symmetry axis, the annular magnetic core may be a circular magnetic core, a rectangular magnetic core, a square magnetic core, or another polygonal magnetic core capable of enabling at least two coils to be wound relatively, the magnetic ring includes at least a first winding area 113a and a second winding area 113b, the first winding area 113a and the second winding area 113b are symmetrically distributed based on a first symmetry axis Y of the magnetic ring 113, and it should be noted that although the first winding area 113a and the second winding area 113b are symmetrically distributed based on the first symmetry axis Y of the magnetic ring 113, specific positions where the first differential mode coil 111 and the second differential mode coil 112 are wound may not be symmetric about the first symmetry axis Y.
In fig. 2, the direction of the arrow on the wire represents the direction of the current, and the arrow on the magnetic ring 113 represents the direction of the induced magnetic field, in the implementation, according to the right-hand rule: the right hand is used for holding the electrified spiral conductor, the four fingers point to the direction of current, and then the end pointed by the thumb is the N pole of the induction magnetic field generated by the electrified spiral conductor. Since the magnetic ring 113 is a closed ring shape, and the first winding region 113a and the second winding region 113b are symmetrically distributed on two sides of the symmetry axis Y, in order to ensure that the directions of magnetic fields generated by the currents in the first differential mode coil 111 and the second differential mode coil 112 are the same, since the directions of the currents flowing in and flowing out of the first differential mode coil 111 and the second differential mode coil 112 are opposite, when winding, the directions of the currents in the first differential mode coil 111 and the second differential mode coil 112 are ensured to be opposite, that is, when the direction of the magnetic field is determined based on the right-hand rule, the directions of the four fingers are opposite, and it is ensured that the directions of the magnetic fields generated in the closed magnetic ring 113 are the same, that is, both counterclockwise or both clockwise.
The interference signal suppression circuit of the embodiment absorbs the differential mode interference signal generated by the interference source through the first-stage filter capacitor, and releases the interference signal into the differential mode signal loop, so that the interference signal is consumed in the differential mode signal loop, and the differential mode interference signal is completely absorbed.
Example 2
In this embodiment, another interference signal suppression circuit is provided, and fig. 3 is a structural diagram of an interference signal suppression circuit according to another embodiment of the present invention, because the capability of absorbing and consuming a differential mode interference signal DM is weak only based on a conductive wire, as shown in fig. 3, on the basis of the above embodiment, the differential mode signal loop 11 further includes: and a secondary filter capacitor C2 serially connected between the output end of the first differential mode coil 111 and the input end of the second differential mode coil 112, for rapidly absorbing the differential mode interference signal DM and avoiding diffusion propagation to the external space.
As mentioned above, the wire has a weak ability to consume the differential mode interference signal DM, and therefore, in order to enhance the ability to consume the differential mode interference signal DM, the differential mode signal loop 11 further includes: the resistor R and the resistor R are arranged at two ends of the secondary filter capacitor C2 in parallel and used for rapidly consuming the differential mode interference signal DM, converting the energy of the differential mode interference signal DM into heat energy, and avoiding excessive energy stored in the secondary filter capacitor C2 so as to avoid damaging the secondary filter capacitor C2.
After the differential mode interference signal DM generated by the interference source is derived by the differential mode signal loop, the differential mode interference signal DM may still return to the interference source, and in order to avoid the differential mode interference signal DM returning through the first terminal of the interference source, as shown in fig. 3, on the basis of the foregoing embodiment, the differential mode signal loop 11 further includes: a first unidirectional conducting element D1, disposed between the first end of the primary filter capacitor C1 and the first terminal of the interference source, for preventing the differential mode interference signal DM from conducting along the direction from the first end of the primary filter capacitor to the first terminal of the interference source;
similarly, in order to avoid the differential mode interference signal DM returning through the second terminal of the interference source, as shown in fig. 3, on the basis of the above embodiment, the differential mode signal loop 11 further includes a second one-way conducting element D2, disposed between the second terminal of the primary filter capacitor C1 and the second terminal of the interference source, for preventing the differential mode interference signal DM from conducting along the direction from the second terminal of the primary filter capacitor C1 to the second terminal of the interference source. The differential mode interference signal DM is limited in the differential mode signal loop 11 by the first one-way conductive element D1 and the second one-way conductive element D2, so as to realize the isolation function of the differential mode interference signal DM.
Specifically, in order to realize the unidirectional conduction function, the first unidirectional conducting element D1 and/or the second unidirectional conducting element D2 are diodes, an anode of the first unidirectional conducting element D1 is connected to the first terminal of the interference source, a cathode is connected to the first end of the primary filter capacitor C1, an anode of the second unidirectional conducting element D2 is connected to the first terminal of the interference source, and a cathode is connected to the second end of the primary filter capacitor C1.
Since the voltage value of the interference signal may be low and cannot trigger the first one-way conductive element D1 and/or the second one-way conductive element D2 to conduct, the differential mode signal loop 11 further includes: a first voltage source DC1, the first voltage source DC1 being arranged in parallel across the first unidirectional conducting element for providing a conducting voltage across the first unidirectional conducting element; and a second voltage source DC2, the second voltage source DC2 being arranged in parallel across the second unidirectional conducting element D2 for providing a conducting voltage across said second unidirectional conducting element.
Example 3
In this embodiment, another interference signal suppression circuit is provided, and fig. 4 is a structural diagram of an interference signal suppression circuit according to another embodiment of the present invention, where the interference signal suppression circuit in the above embodiment implements an effect of absorbing and consuming a differential mode interference signal DM generated by an interference source, but the interference source may also generate a common mode interference signal CM, and in order to eliminate the common mode interference signal CM generated by the interference source, as shown in fig. 4, on the basis of the above embodiment, the interference signal suppression circuit further includes: a first common mode choke coil 21 and a second common mode choke coil 22;
fig. 5 is a schematic structural diagram of a magnetic ring according to another embodiment of the present invention, as shown in fig. 5, the magnetic ring is a hollow annular magnetic core having at least two symmetry axes, and the magnetic ring includes a first winding area 113a, a second winding area 113b, a third winding area 113c, and a fourth winding area 113d, where the first winding area 113a and the second winding area 113b are symmetrically distributed based on a first symmetry axis Y of the magnetic ring 113, and the third winding area 113c and the fourth winding area 113d are symmetrically distributed based on a second symmetry axis X of the magnetic ring 113, and the second symmetry axis X is not coincident with the first symmetry axis Y, and it should be noted that the annular magnetic core may be circular, rectangular, or square, or another polygon capable of implementing two-by-two opposite winding of at least four coils.
Fig. 6 is a schematic diagram showing the current in the conducting wire and the magnetic field direction inside the magnetic ring according to another embodiment of the present invention, as shown in fig. 6, similar to the above embodiment, the energized spiral conducting wire is held by the right hand, the four fingers point to the current direction, and then the end pointed by the thumb is the N-pole of the magnetic field direction generated by the energized spiral conducting wire. Because the magnetic ring 113 is a closed ring, and the third winding area 113C and the fourth winding area 113d are symmetrically distributed on two sides of the symmetry axis Y, the first common mode choke coil 21 is wound on the third winding area 113C of the magnetic ring, the input end of the first common mode choke coil is connected with the first end of the first-stage filter capacitor C1, and the output end of the first common mode choke coil is connected with the first pole terminal of the power bus; the second common mode choke coil 22 is wound around the fourth winding area 113c of the magnetic loop, the input end of the second common mode choke coil is connected to the second end of the primary filter capacitor, the output end of the second common mode choke coil is connected to the second pole terminal of the power bus, since the flowing-in and flowing-out directions of the currents in the first common mode choke coil 21 and the second common mode choke coil 22 are the same, and in order to ensure that the directions of the magnetic fields generated by the currents in the first common mode choke coil 21 and the second common mode choke coil 22 are the same, during winding, the directions of the currents in the first common mode choke coil 21 and the second common mode choke coil 22 are opposite, that is, when the directions of the magnetic fields are determined based on the right-hand rule, the directions of the four fingers are opposite, that the directions of the magnetic fields generated in the closed magnetic loop 113 are the same, that is, both is, the counterclockwise direction or both are clockwise direction, and the directions of the magnetic fields generated by the currents in the first differential mode coil 111 and the second differential mode coil 112 are the same, by the design, the field intensity of the generated induction magnetic field can be increased, and interference signals can be eliminated.
It should be noted that, the first winding area 113a and the second winding area 113b are symmetrically distributed based on the first symmetry axis Y of the magnetic ring 113, and the third winding area 113c and the fourth winding area 113d are symmetrically distributed based on the second symmetry axis X of the magnetic ring 113, which is a preferred embodiment of the present invention, and in the specific implementation process, the first differential mode coil, the second differential mode coil, the first common mode choke coil 21 and the second common mode choke coil 22 are wound at different positions of the magnetic ring, so that the present invention can be implemented.
In order to further absorb the common mode interference signal, as shown in fig. 4, on the basis of the above embodiment, the circuit further includes: a first common-mode filter capacitor C3, a first end of the first common-mode filter capacitor C3 is connected between the output end of the first common-mode choke coil 21 and the first terminal of the power bus, and a second end thereof is grounded; similarly, a second common mode filter capacitor C4 is further included, a first end of the second common mode filter capacitor C4 is connected between the output end of the second common mode choke coil 22 and the second pole terminal of the power bus, and a second end thereof is grounded.
In order to provide a stable test impedance when testing for electromagnetic interference signals, as shown in fig. 4, the circuit further comprises: the LISN line impedance stabilizing network 31 is connected with the first end of the LISN line impedance stabilizing network 31 connected with the output end of the first common mode choke coil 21, the second end of the LISN line impedance stabilizing network 31 connected with the output end of the second common mode choke coil 22, the third end of the LISN line impedance stabilizing network connected with the first pole terminal of the power bus, and the fourth end of the LISN line impedance stabilizing network connected with the second pole terminal of the power bus, and is used for isolating power grid interference and providing stable test impedance.
Example 4
This embodiment provides another interference signal suppression circuit, and fig. 7 is a structural diagram of an interference signal suppression circuit according to another embodiment of the present invention, as shown in fig. 7: the circuit includes:
CXN, a magnetic ring 71, a first differential mode inductor L1, a second differential mode inductor L2, diodes D1 and D2, a first common mode inductor L3, a second common mode inductor L4, a secondary filter capacitor CX0 and a consumption resistor R.
The primary filter capacitor CX1, cx2.. CXN is used for absorbing an interference signal generated by an interference source load, and particularly has the smallest impedance to the interference signal of a resonant frequency, so that the absorption effect is particularly obvious; the diodes D1 and D2 have the function of controlling the unidirectional conduction of the interference signal and prevent the reverse flow of the interference signal; the first common-mode inductor L3 and the second common-mode inductor L4 are used for smoothing interference signals and performing partial consumption; the secondary filter capacitor CX0 is used for absorbing energy of the interference signal absorbed by the filter capacitors CX1, cx2.. CXN for circulation again, and the energy is smoothed through the first common-mode inductor L3 and the second common-mode inductor L4 in the flowing process; the consumption resistor R is used for consuming the energy of interference signals in the loop, and the phenomenon that the filtering action of the capacitor is invalid and damaged due to excessive stored energy is avoided;
differential mode interference signal DM: the interference signal flows through the loop circuit, namely, the direction of the interference signal in the two lines is opposite to that of the interference signal between the live line and the zero line or between the positive pole and the negative pole, and the interference signals in the two lines have the same magnitude.
Common mode interference signal CM: the interference signal flows through the loop from the line to the ground, and the direction and the size of the interference signal in the two lines are the same.
And (3) a filtering cycle process:
differential mode interference signal DM enters into filter capacitor CX1CX2.. CXN after diode D1 and D2, and the reverse blocking effect of diode leads to differential mode interference signal can not release from primary filter capacitor CX1, CX2.. CXN and return to former circuit. The differential mode interference signal DM is transmitted to a next-stage circuit after passing through the magnetic ring 71;
generally, a common mode signal CM in a circuit passes through the first common mode inductor L3 and the first common mode inductor L4, and a magnetic field generated by each common mode signal CM in the magnetic ring 71 has the same direction, so that the magnetic field effect of the magnetic ring 71 is enhanced. And then the interference signal is led into the ground through a common mode filter capacitor CY, so that an interference signal transmission loop is formed. Through the adjustment of the winding direction, the direction of the magnetic field generated by the differential mode interference signal CM is the same as the direction of the magnetic field generated by the first common mode inductance L3 and the first common mode inductance L4. Not only increases the field intensity of the magnetic field in the magnetic ring 71, but also provides a differential mode magnetic field for a differential mode signal differential mode loop in the filter capacitor. The suppression and the smoothing of the differential mode interference signal are facilitated.
In order to avoid the magnetic ring 71 from inductively blocking the differential mode signal and causing the signal to propagate to other capacitive spaces, a secondary filtering capacitor CX0 is added in a post-stage circuit, and the capacitor can absorb the interference signal into the capacitor as soon as possible and avoid the diffusion propagation to the external space.
And finally, adding a consumption resistor R to convert the interference signal into heat energy to be consumed. Thus, the energy generated by the interference signal is consumed, and is not stored in the capacitor too much, so that the capacitor is prevented from being damaged; or the effect of the secondary filter capacitance CX0 on absorbing the interference signal disappears due to excessive energy storage.
The interference signal suppression circuit of this embodiment, absorb differential mode interference signal in an independent circulating circuit, keep apart with other routes, and with interference energy consumption in a circulating circuit, avoid interference signal to spread other sharing circuit, avoid appearing the too much inefficacy of electric capacity energy storage or damaging simultaneously, can realize absorption and suppression to differential mode interference signal, simultaneously can be through the inductance of increase common mode inductance, restrain common mode interference ability, through the above-mentioned scheme, finally realize sparingly developing and matching the experimental time, effectively improve the test success rate, improve complete machine EMC experiment qualification rate.
Example 5
The embodiment provides an electrical apparatus, which includes an interference source, a power supply, and an interference signal suppression circuit in the above embodiment, and the electrical apparatus may be an air conditioner, a television, or other household electrical appliances.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An interference signal suppression circuit connected to an interference source, the circuit comprising:
a first end of the first-stage filter capacitor is connected with a first terminal of the interference source, and a second end of the first-stage filter capacitor is connected with a second terminal of the interference source;
the differential mode signal loop comprises a first differential mode coil, a second differential mode coil and a magnetic ring;
the first differential mode coil is wound in a first winding area of the magnetic ring, and the input end of the first differential mode coil is connected to the first end of the primary filter capacitor;
the second differential mode coil is wound in a second winding area of the magnetic ring, the output end of the second differential mode coil is connected to the second end of the primary filter capacitor, and the output end of the first differential mode coil is connected with the input end of the second differential mode coil; wherein the first winding area and the second winding area are symmetric about a first axis of symmetry of the magnetic loop;
the differential mode signal loop is used for consuming differential mode interference signals generated by an interference source;
further comprising:
a first common mode choke coil and a second common mode choke coil; the first common mode choke coil is wound in a third winding area of the magnetic ring, the input end of the first common mode choke coil is connected with the first end of the primary filter capacitor, and the output end of the first common mode choke coil is connected with a first pole terminal of a power bus; the second common mode choke coil is wound in a fourth winding area of the magnetic ring, the input end of the second common mode choke coil is connected with the second end of the primary filter capacitor, and the output end of the second common mode choke coil is connected with a second pole terminal of the power bus; the third winding area and the fourth winding area are symmetrical about a second symmetry axis of the magnetic ring, and the second symmetry axis is not coincident with the first symmetry axis; the direction of a magnetic field generated by the current in the first common mode choke coil and the direction of a magnetic field generated by the current in the second common mode choke coil are the same, and the direction of a magnetic field generated by the current in the first differential mode coil and the direction of a magnetic field generated by the current in the second differential mode coil are the same.
2. The circuit of claim 1, wherein the direction of the magnetic field generated by the current in the first differential mode coil is the same as the direction of the magnetic field generated by the current in the second differential mode coil.
3. The circuit of claim 1, wherein the differential mode signal loop further comprises:
and the secondary filter capacitor is connected between the output end of the first differential mode coil and the input end of the second differential mode coil in series and is used for rapidly absorbing the differential mode interference signal.
4. The circuit of claim 3, wherein the differential mode signal loop further comprises:
and the resistor is arranged at two ends of the secondary filter capacitor in parallel and is used for consuming the differential mode interference signal.
5. The circuit of claim 1, wherein the differential mode signal loop further comprises:
the first unidirectional conducting element is arranged between the first end of the primary filter capacitor and the first terminal of the interference source and used for preventing the differential mode interference signal from conducting along the direction from the first end of the primary filter capacitor to the first terminal of the interference source;
and the second one-way conduction element is arranged between the second end of the primary filter capacitor and the second terminal of the interference source and used for preventing the differential mode interference signal from conducting along the direction from the second end of the primary filter capacitor to the second terminal of the interference source.
6. The circuit of claim 5, wherein the first and/or second unidirectional conducting elements are diodes.
7. The circuit of claim 5, wherein the differential mode signal loop further comprises:
the first voltage source is arranged at two ends of the first unidirectional conducting element in parallel and used for providing conducting voltage for two ends of the first unidirectional conducting element;
and the second voltage source is arranged at two ends of the second one-way conduction element in parallel and used for providing conduction voltage for two ends of the second one-way conduction element.
8. The circuit of claim 1, further comprising:
a first common mode filter capacitor, a first end of which is connected between the output end of the first common mode choke coil and the first pole terminal of the power bus, and a second end of which is grounded;
and a second common mode filter capacitor having a first end connected between the output end of the second common mode choke coil and the second pole terminal of the power bus, and a second end grounded.
9. The circuit of claim 1, further comprising:
and the first end of the LISN line impedance stabilizing network is connected with the output end of the first common mode choke coil, the second end of the LISN line impedance stabilizing network is connected with the output end of the second common mode choke coil, the third end of the LISN line impedance stabilizing network is connected with the first pole terminal of the power bus, and the fourth end of the LISN line impedance stabilizing network is connected with the second pole terminal of the power bus, so that the LISN line impedance stabilizing network is used for isolating power grid interference and providing stable test impedance.
10. An electrical apparatus comprising an interference source and a power supply, characterized by further comprising an interference signal suppression circuit according to any one of claims 1 to 9.
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