CN111244238A - High-brightness semiconductor light-emitting diode chip and manufacturing method thereof - Google Patents
High-brightness semiconductor light-emitting diode chip and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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Abstract
The invention provides a high-brightness semiconductor light-emitting diode chip which comprises a graphical sapphire substrate, wherein the graphical sapphire substrate comprises a sapphire substrate with raised pictures and texts on the upper surface, and DBR picture layers are arranged on the raised pictures and texts. According to the chip, the raised pictures and texts are arranged on the sapphire substrate, so that nucleation during epitaxial growth is facilitated, and the crystal quality and the ESD resistance are improved; the DBR layer is arranged on the raised pattern and text, so that the reflectivity of the substrate to light emitted by the active region is improved, and the luminous intensity is improved. The invention also discloses a manufacturing method of the chip, which adopts a unique manufacturing process of the graphical sapphire substrate to obtain the high-quality graphical sapphire substrate, and then combines the deposition of the buffer layer, the N-type nitride semiconductor layer, the current expansion layer, the active layer, the P-type nitride semiconductor layer, the current blocking layer and the transparent conducting layer and the manufacturing of the N-type electrode and the P-type electrode to obtain the LED product with high luminous brightness, good antistatic capability and good reverse voltage resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-brightness semiconductor light-emitting diode chip and a manufacturing method thereof.
Background
Light Emitting Diode (LED) blue chips are the "engine" for semiconductor lighting. Since the gallium nitride (GaN) -based LED has made a successful breakthrough of p-GaN, the technical progress is very obvious, the growth quality of the epitaxial layer is obviously improved, and the dislocation density can be controlled to 106/cm2In the following, research on the light emitting mechanism of the multi-quantum well LED has been made, and research on various fields such as epitaxial growth, chip manufacturing, light emitting efficiency, and packaging application in the semiconductor illumination field has been conducted more thoroughly.
At present, the photoelectric conversion efficiency of the chip in the illumination field during normal operation breaks through 75%, and the luminous efficiency of the conventional high-luminous-efficiency illumination packaging body lamp bead can also reach 240 lm/W.
The most widely used substrate for GaN-based LEDs is a sapphire substrate. Due to the fact that large lattice constant mismatch and thermal conductivity mismatch exist between the GaN and the sapphire, a grown GaN light emitting layer is stressed in a compression mode, crystal quality is poor, a large number of crystal defects such as dislocation exist, and the brightness, light emitting efficiency, ESD resistance and reverse voltage resistance of the LED chip are greatly affected.
In conclusion, the development of the LED chip capable of effectively improving the luminous brightness of the device, the antistatic capability of the device and the reverse voltage resistance capability and the manufacturing method thereof are significant.
Disclosure of Invention
The invention discloses a high-brightness semiconductor light-emitting diode chip (namely an LED chip) which has a simple structure and can effectively improve the luminous brightness of a device, the antistatic capability of the device and the reverse voltage resistance, and the specific technical scheme is as follows:
the utility model provides a high brightness semiconductor light emitting diode chip, includes graphical sapphire substrate, graphical sapphire substrate includes that the upper surface has the sapphire substrate of protruding picture and text, be equipped with the DBR picture layer on the protruding picture and text. In the invention: the sapphire substrate is provided with the raised patterns and texts, so that nucleation is facilitated during epitaxial growth, namely, nucleation is firstly performed on the part, which is not covered with the DBR layer, on the upper surface of the sapphire during growth, the dislocation density is facilitated to be reduced, and the crystal quality and the ESD resistance are improved; the DBR is arranged on the raised patterns and texts, so that the reflectivity of the substrate to light emitted by the active region can be improved, and the luminous intensity is improved. Make the patterned substrate and adopt the protruding picture and text on the sapphire substrate and the combination of DBR picture layer through the DBR, establish the DBR picture layer (be unfavorable for follow-up epitaxial growth) with traditional simple sapphire patterned substrate or sapphire substrate whole upper surface and compare, have unique reflection configuration, can ensure the growth demand of epitaxial layers such as follow-up buffer layer, can improve epitaxial layer crystal quality again and improve the light that the reflection active area sent, thereby reach the effect that improves device luminous brightness, improve device antistatic effect and improve the ability of anti reverse voltage.
In the invention, the reflectivity of the DBR layer in a visible light wave band of 380-800nm is more than 95%. The light emitting brightness is high.
In the invention, the specification of the structure formed by the raised image-text and the DBR layer is as follows: the width (the preferred diameter) of the bottom end is 1-4um, the height is 1-3um, and the distance between the adjacent structures is 0.2-0.5 um; in the same structure, the height of the DBR layer is 0.5-2.0 times of the height of the raised graphics context. By adopting the specification parameter setting, the LED device with high brightness and good EDS performance can be further obtained.
In the invention, the DBR layer is a structure formed by alternately laminating silicon dioxide layers and titanium dioxide layers, and the thickness of each layer is simulated by optical software to form a distributed Bragg reflector. The DBR layer is easy to obtain in material and low in cost, so that a good insulation effect can be achieved, an electric leakage prevention effect can be achieved, and the safety of the whole device is improved; the thickness of each layer is arranged to form a distributed Bragg reflector, so that light emitted by the active region is optimally reflected, and the brightness is favorably improved.
The invention further comprises a buffer layer, an N-type nitride semiconductor layer, a current expansion layer, an active layer, a P-type nitride semiconductor layer, a current blocking layer and a transparent conducting layer which are sequentially arranged on the basis of the graphical sapphire substrate, wherein the N-type electrode is arranged on the N-type nitride semiconductor layer, and the P-type electrode is arranged on the current blocking layer and the transparent conducting layer. By manufacturing the epitaxial layer on the graphical sapphire substrate, the LED chip product with high luminous brightness, good antistatic capability and good reverse voltage resistance is obtained.
In the invention, the transparent conducting layer and the p-type nitride semiconductor layer are coaxially arranged, and the vertical distance from the side edge of the transparent conducting layer to the axis is smaller than the vertical distance from the side edge of the p-type nitride semiconductor layer to the axis by 0.1-15 um. The LED light source can improve the light emitting area of the LED to the maximum extent, thereby improving the brightness of the LED.
The invention also discloses a manufacturing method of the high-brightness semiconductor light-emitting diode chip, which comprises the following steps of manufacturing the graphical sapphire substrate:
step one, cleaning a sapphire substrate plane sheet;
depositing a DBR layer on the upper surface of the sapphire substrate plane sheet;
step three, manufacturing a graph to obtain a graphical sapphire substrate, which specifically comprises the following steps: firstly, manufacturing a plurality of cylindrical structures in a photoetching mode; then, a plurality of pattern structures are manufactured through an etching method; finally, cleaning and baking to obtain a graphical sapphire substrate; wherein: the diameter of the cylindrical structures is 2-4um, and the interval between the adjacent cylindrical structures is 0.2-1 um; the upper part of the pattern layer structure is a DBR pattern layer, the lower part of the pattern layer structure is a sapphire stone material layer, the bottom width diameter of the pattern structure is 1-4um, the height of the pattern structure is 1-3um, the height of the DBR pattern layer is 0.5-2.0 times of the height of the sapphire stone material layer, and the interval between every two adjacent pattern structures is 0.2-0.5 um.
Preferably, in the above technical solution, the cleaning in the first step includes the following steps:
step 1.1, firstly, ultrasonically cleaning by using acetone, and then washing by using deionized water; wherein: the cleaning time is 3-15 min;
step 1.2, firstly adopting ammonia water and hydrogen peroxide for cleaning, and then adopting deionized water for washing, wherein: the volume ratio of the ammonia water to the hydrogen peroxide is 4: 1, cleaning for 3-15 min;
step 1.3, firstly adopting sulfuric acid hydrogen peroxide for cleaning, and then adopting deionized water for washing, wherein: the volume ratio of the sulfuric acid to the hydrogen peroxide to the water is 5: 1: 1, cleaning for 3-15 min;
and step 1.4, spin-drying and baking in a nitrogen atmosphere.
Preferably, in the above technical solution, the method for depositing the DBR layer in the second step is evaporation and/or sputtering; the DBR layer is a structure formed by alternately laminating silicon dioxide layers and titanium dioxide layers, and the reflectivity of the DBR layer in a visible light wave band of 380-800nm is larger than 95%.
Preferably, the method further comprises depositing a buffer layer, an n-type nitride semiconductor layer, a current spreading layer, an active layer, a p-type nitride semiconductor layer, a current blocking layer and a transparent conductive layer on the patterned sapphire substrate; an N-type electrode is arranged on the N-type nitride semiconductor layer, and a P-type electrode is arranged on the current blocking layer and the transparent conducting layer; the N-type electrode and the P-type electrode are both of electrode structures, and the electrode structures are composed of a Ni layer with the thickness of 0.1-20nm, a Cr layer with the thickness of 1-60nm, an Al layer with the thickness of 20-300nm, a Pt layer with the thickness of 10-200nm and an Au layer with the thickness of 400-3000 nm.
According to the invention, a unique patterned sapphire substrate manufacturing process is adopted to obtain a high-quality patterned sapphire substrate, and then the buffer layer, the N-type nitride semiconductor layer, the current expansion layer, the active layer, the P-type nitride semiconductor layer, the current barrier layer and the transparent conducting layer are combined for deposition and the N-type electrode and the P-type electrode are manufactured, so that the LED product with high luminous brightness, good antistatic capability and good reverse voltage resistance is obtained.
In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural view of a high-luminance semiconductor light-emitting diode chip in embodiment 1;
FIG. 2 is a schematic diagram of the structure of the patterned sapphire substrate of FIG. 1;
FIG. 3 is an enlarged schematic view of the convex mesa surface structure of FIG. 1;
FIG. 4 is a flow chart of the fabrication of a high-brightness semiconductor light emitting diode chip in example 1;
FIG. 5 is a graph showing a comparison of the brightness of the LED obtained in example 1 and that of a conventional LED;
FIG. 6 is a graph comparing the antistatic ability of the LED obtained in example 1 and a conventional LED;
the LED light source comprises a patterned sapphire substrate, 1.1 sapphire substrate, 1.2 raised pictures and texts, 1.3 DBR picture layers, 2 buffer layers, 3N-type nitride semiconductor layers, 4 current expansion layers, 5 active layers, 6P-type nitride semiconductor layers, 7 current blocking layers, 8 transparent conducting layers, 9N-type electrodes, 10P-type electrodes, 11 protective passivation layers.
Detailed Description
Embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways, which are defined and covered by the claims.
Example (b):
the high-brightness semiconductor light-emitting diode chip is an LED chip with a DBR (distributed Bragg reflector) patterned substrate, the size specification of the LED chip is 550um multiplied by 875um, and in detail, the LED chip is shown in figure 1 and specifically comprises a patterned sapphire substrate 1, a buffer layer 2, an N-type nitride semiconductor layer 3, a current expansion layer 4, an active layer 5, a P-type nitride semiconductor layer 6, a current blocking layer 7, a transparent conducting layer 8, a P-type electrode 9, an N-type electrode 10 and a passivation protective layer 11.
The specific structure of the patterned sapphire substrate 1 is as follows: the graphical sapphire substrate 1 comprises a sapphire substrate 1.1 with raised pictures and texts 1.2 on the upper surface, wherein DBR picture layers 1.3 are arranged on the raised pictures and texts 1.2, and are shown in detail in FIG. 2; the DBR layer 1.3 is a structure formed by alternately laminating silicon dioxide layers and titanium dioxide layers, the refractive indexes of the two materials are respectively 1.45-1.52 and 2.45-2.55, the thicknesses of the layers are simulated by optical software to form a distributed Bragg reflector, and the reflectivity of the DBR layer 1.3 in a visible light wave band of 380-800nm is more than 95 percent; the specification of the structure formed by the raised image-text 1.2 and the DBR image layer 1.3 is as follows: the diameter of the bottom end (i.e., the diameter of the portion in contact with the sapphire substrate 1.1, i.e., the diameter of the lowermost end of the structure in fig. 1) is 1-4um (preferably 3um), the height is 1-3um (preferably 2um), and the interval between adjacent structures is 0.2-0.5um (preferably 0.3 um); in the same structure, the height of the DBR layer 1.3 is 0.5-2.0 times (1.2 times in fig. 2) the height of the raised image-text 1.2. In addition, the shapes of the structures formed by the raised images and texts 1.2 and the DBR layer 1.3 can be a yurt, an octagonal cone, a hexagonal cone, a pentagonal cone and the like, and are set according to actual requirements (such as the luminous efficiency of a device), and the bottom width diameter, the height, the interval and the like of the structures can also be adjusted according to requirements.
Growing a buffer layer 2, an n-type nitride semiconductor layer 3, a current spreading layer 4, an active layer 5 and a p-type nitride semiconductor layer 6 on the patterned sapphire substrate 1 to form a nitride semiconductor structure with a convex mesa, which is shown in detail in fig. 3; a current barrier layer 7 is arranged on the first surface of the convex table top; and transparent conducting layers 8 are arranged on the upper surfaces of the current resistance layers 7 right above the first surface of the convex table top.
The P-type electrode 9 comprises a P-type pad and a P-type line electrode, the lower end of the P-type pad is arranged on the first upper surface of the convex table top, and the lower end of the P-type line electrode is arranged on the transparent conducting layer 8.
The lower end of the N-type electrode 10 is disposed on the second upper surface of the mesa.
The passivation protection layer 11 is arranged on the surface of the transparent conductive layer 8 and the second surface of the convex table top except the region of the N electrode, or a current blocking pattern layer is further arranged on the first upper surface of the convex table top, and the transparent conductive layer 8 is arranged on the current blocking pattern layer, the first upper surface and the upper surface of the current blocking layer 7 which is positioned right above the first upper surface; the P-type line electrode is positioned right above the current blocking pattern layer.
The current blocking layer 7, the current blocking pattern layer and the passivation protective layer 9 are made of insulating materialsThe edge material is silicon dioxide (SiO)2)。
Transparent conducting layer 8 with p type nitride semiconductor layer 6 sets up with the axle center, just the side of transparent conducting layer 8 is compared to the perpendicular distance of axle center the side of p type nitride semiconductor layer 6 is little 0.1-15um to the perpendicular distance of axle center.
The structure of the P-type electrode 9 is the same as that of the N-type electrode 10, the electrode structure comprises metal layers of Ni, Cr, Al, Pt, Au and the like, the thickness of the Ni layer in the electrode structure is 0.1-20nm, the thickness of the Cr layer is 1-60nm, the thickness of the Al layer is 20-300nm, the thickness of the Pt layer is 10-200nm, the thickness of the Au layer is 400-3000nm, and the thickness of each metal layer in the electrode structure can be selected according to actual requirements.
The specific steps of the manufacturing of the LED chip refer to fig. 4, which specifically includes the following steps:
firstly, manufacturing a patterned sapphire substrate 1, which specifically comprises the following steps:
step one, cleaning a sapphire substrate plane sheet (namely, cleaning a plane substrate): step 1.1, firstly, ultrasonically cleaning by using acetone, and then washing by using deionized water; wherein: the cleaning time is 3-15min (preferably 12 min); step 1.2, firstly adopting ammonia water and hydrogen peroxide for cleaning, and then adopting deionized water for washing, wherein: the volume ratio of the ammonia water to the hydrogen peroxide is 4: 1, the cleaning time is 3-15min (preferably 10 min); step 1.3, firstly adopting sulfuric acid hydrogen peroxide for cleaning, and then adopting deionized water for washing, wherein: the volume ratio of sulfuric acid (mass fraction 98%), hydrogen peroxide (mass fraction 30%) and water is 5: 1: 1, the cleaning time is 3-15min (preferably 15 min); and step 1.4, spin-drying and baking in a nitrogen atmosphere.
Depositing a DBR layer (namely depositing a DBR) on the upper surface of the sapphire substrate plane sheet, and specifically, alternately depositing a silicon dioxide layer and a titanium dioxide layer by using an optical film plating machine;
step three, manufacturing a graph to obtain a graphical sapphire substrate, which specifically comprises the following steps: firstly, a plurality of cylindrical structures (namely, pattern substrate photoetching) are manufactured in a photoetching mode, and photoetching specifically comprises the steps of photoresist evening, soft baking, exposure, development, film hardening and the like (refer to the prior art), wherein the thickness of the photoresist is 2-2.8 um; then etching the substrateMaking multiple pattern structures (i.e. pattern substrate etching), etching gas CF4/BCl3/Ar, or CHF3/BCl3Ar; finally cleaning (removing photoresist by acetone, removing photoresist by several times, then cleaning with deionized water), baking (at 100 deg.C, under N2Baking under atmosphere) to obtain a patterned sapphire substrate (namely, removing photoresist, cleaning and spin-drying); wherein: the diameter of the cylindrical structures is 2-4um (preferably 4um), and the interval between the adjacent cylindrical structures is 0.2-1um (preferably 0.3 um); the upper portion of the pattern layer structure is a DBR pattern layer, the lower portion of the pattern layer structure is a sapphire stone material layer, the bottom width diameter of the pattern structure is 1-4um (preferably 3um), the height of the pattern structure is 1-3um (preferably 3um), the height of the DBR pattern layer is 0.5-2.0 times (preferably 1.2 times) of the height of the sapphire stone material layer, and the interval between adjacent pattern structures is 0.2-0.5um (preferably 0.5).
And secondly, growing an epitaxial wafer (namely epitaxial growth), and growing a GaN-based semiconductor layer on the prepared patterned sapphire substrate 1 by using a metal organic chemical deposition (MOCVD) method, wherein the GaN-based semiconductor layer comprises a complete LED epitaxial structure (namely the epitaxial wafer) such as a buffer layer u-GaN, an n-type nitride semiconductor layer n-GaN, an active layer MQW, a p-type nitride semiconductor layer p-GaN and the like.
And thirdly, manufacturing a chip. After the epitaxial wafer grown in the second step is cleaned (i.e., the epitaxial wafer is cleaned), a convex table is firstly manufactured (i.e., a convex table is manufactured), specifically, the convex table is manufactured by using a photoetching and dry etching method, and the used materials, equipment, processes and the like refer to the prior art; then depositing a current barrier layer (namely manufacturing the current barrier layer), wherein the material of the current barrier layer is silicon oxide, and the current barrier layer is manufactured through photoetching and wet etching, wherein the current barrier layer and the bonding pad under the bonding pad are coaxially designed, and the current barrier layer is also arranged under the p-finger line; depositing Indium Tin Oxide (ITO) of a transparent conducting layer (namely manufacturing a current expansion layer) in a sputtering mode, wherein the thickness of the ITO is 20-200nm (preferably 100nm), and making a designed pattern by photoetching and wet etching methods, wherein a solution used in the wet etching is an ITO etching solution (a mixed solution of ferric chloride and hydrochloric acid) which is directly purchased; then, manufacturing a P electrode and an N electrode (namely manufacturing P, N electrodes) by using a negative photoetching and metal evaporation method; then, depositing silicon oxide by PECVD (plasma enhanced chemical vapor deposition) to prepare a passivation protective layer (namely, preparing the passivation protective layer), wherein the thickness of the passivation protective layer is 50-300nm (preferably 280nm), and exposing the P electrode and the N electrode by photoetching and wet etching; and finally, plating a DBR reflecting layer on the back after thinning, and then cracking the wafer into single LED core particles in an invisible cutting mode.
Processing steps and process parameters which are not disclosed in the embodiment can be obtained according to the prior art.
Compared with the traditional pattern substrate, the LED chip of the embodiment has higher luminous brightness and ESD resistance, and the rest photoelectric parameters are not affected: fig. 5 is a brightness comparison between the LED chip of the present embodiment and the conventional LED chip. Fig. 6 is a comparison graph of the antistatic ability of the LED chip of the present embodiment and the conventional LED chip, the ESD resistance test mode in fig. 6 is a human body mode, the used equipment is ZY920ESD resistance test equipment of ZOYER corporation, the test is started from 1000V, 200V is step by step, each ESD level is positive and negative once, until the device fails, the ESD test level before the failure is recorded as the ESD resistance value of the device under test.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The high-brightness semiconductor light-emitting diode chip is characterized by comprising a graphical sapphire substrate (1), wherein the graphical sapphire substrate (1) comprises a sapphire substrate (1.1) with raised pictures and texts (1.2) on the upper surface, and a DBR picture layer (1.3) is arranged on the raised pictures and texts (1.2).
2. The high-brightness semiconductor light-emitting diode chip as claimed in claim 1, wherein the reflectivity of the DBR layer (1.3) in the visible light band of 380-800nm is greater than 95%.
3. The high-brightness semiconductor light-emitting diode chip as claimed in claim 1, wherein the bump pattern (1.2) and the DBR layer (1.3) form a structure having the following specifications: the width of the bottom end is 1-4um, the height is 1-3um, and the distance between adjacent structures is 0.2-0.5 um; in the same structure, the height of the DBR image layer (1.3) is 0.5-2.0 times of the height of the raised image-text (1.2).
4. The high-brightness semiconductor light-emitting diode chip as claimed in claim 1, wherein the DBR layer (1.3) is a structure in which a silicon dioxide layer and a titanium dioxide layer are alternately laminated.
5. The high-brightness semiconductor light-emitting diode chip according to any one of claims 1 to 4, further comprising a buffer layer (2), an N-type nitride semiconductor layer (3), a current spreading layer (4), an active layer (5), a P-type nitride semiconductor layer (6), a current blocking layer (7), and a transparent conductive layer (8) which are sequentially disposed based on the patterned sapphire substrate (1), wherein the N-type electrode (9) is disposed on the N-type nitride semiconductor layer (3), and the P-type electrode (10) is disposed on the current blocking layer (7) and the transparent conductive layer (8).
6. The high brightness semiconductor light emitting diode chip as claimed in claim 5, wherein said transparent conductive layer (8) is coaxially disposed with said p-type nitride semiconductor layer (6), and a vertical distance from a side edge of said transparent conductive layer (8) to an axis is smaller than a vertical distance from a side edge of said p-type nitride semiconductor layer (6) to an axis by 0.1-15 μm.
7. A method for manufacturing a high-brightness semiconductor light-emitting diode chip is characterized by comprising the following steps of manufacturing a graphical sapphire substrate (1):
step one, cleaning a sapphire substrate plane sheet;
depositing a DBR layer on the upper surface of the sapphire substrate plane sheet;
step three, manufacturing a graph to obtain a graphical sapphire substrate (1), which specifically comprises the following steps: firstly, manufacturing a plurality of cylindrical structures in a photoetching mode; then, a plurality of pattern structures are manufactured through an etching method; finally, cleaning and baking to obtain a graphical sapphire substrate (1); wherein: the diameter of the cylindrical structures is 2-4um, and the distance between adjacent cylindrical structures is 0.2-1 um; the upper portion of the graph structure is a DBR layer, the lower portion of the graph structure is a sapphire stone material layer, the width of the bottom end of the graph structure is 1-4um, the height of the graph structure is 1-3um, the height of the DBR layer is 0.5-2.0 times of the height of the sapphire stone material layer, and the distance between every two adjacent graph structures is 0.2-0.5 um.
8. The method for manufacturing a high-brightness semiconductor light-emitting diode chip as claimed in claim 7, wherein the cleaning in the first step comprises the steps of:
step 1.1, ultrasonically cleaning for 3-15min by using acetone, and then washing by using deionized water;
step 1.2, firstly cleaning with ammonia water and hydrogen peroxide for 3-15min, and then washing with deionized water, wherein: the volume ratio of the ammonia water to the hydrogen peroxide is 4: 1;
step 1.3, firstly adopting sulfuric acid and hydrogen peroxide to clean for 3-15min, and then adopting deionized water to rinse, wherein: the volume ratio of the sulfuric acid to the hydrogen peroxide to the water is 5: 1: 1;
and step 1.4, spin-drying and baking in a nitrogen atmosphere.
9. The method for manufacturing a high brightness semiconductor light emitting diode chip as claimed in claim 8, wherein the DBR layer deposition in the second step is evaporation and/or sputtering; the DBR layer is a structure formed by alternately laminating silicon dioxide layers and titanium dioxide layers, and the reflectivity of the DBR layer in a visible light wave band of 380-800nm is larger than 95%.
10. The method for manufacturing a high brightness semiconductor light emitting diode chip as claimed in any one of claims 7-9, further comprising depositing a buffer layer (2), an n-type nitride semiconductor layer (3), a current spreading layer (4), an active layer (5), a p-type nitride semiconductor layer (6), a current blocking layer (7) and a transparent conductive layer (8) on said patterned sapphire substrate (1); an N-type electrode (9) is provided on the N-type nitride semiconductor layer (3), and a P-type electrode (10) is provided on the current blocking layer (7) and the transparent conductive layer (8); the N-type electrode (9) and the P-type electrode (10) are both of electrode structures, and the electrode structures are composed of at least two of a Ni layer with the thickness of 0.1-20nm, a Cr layer with the thickness of 1-60nm, an Al layer with the thickness of 20-300nm, a Pt layer with the thickness of 10-200nm and an Au layer with the thickness of 400-3000 nm.
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| CN111933772A (en) * | 2020-07-09 | 2020-11-13 | 厦门士兰明镓化合物半导体有限公司 | Light emitting diode and method for manufacturing the same |
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| CN111933772A (en) * | 2020-07-09 | 2020-11-13 | 厦门士兰明镓化合物半导体有限公司 | Light emitting diode and method for manufacturing the same |
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| CN111697114A (en) * | 2020-07-29 | 2020-09-22 | 东南大学苏州研究院 | LED chip with vertical structure and preparation method thereof |
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