CN111244186A - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the same Download PDFInfo
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- CN111244186A CN111244186A CN201811441985.6A CN201811441985A CN111244186A CN 111244186 A CN111244186 A CN 111244186A CN 201811441985 A CN201811441985 A CN 201811441985A CN 111244186 A CN111244186 A CN 111244186A
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- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000007769 metal material Substances 0.000 claims abstract description 3
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- 239000000463 material Substances 0.000 description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses a thin film transistor and a manufacturing method thereof. The grid is arranged on the substrate, and the grid dielectric layer is arranged on the grid. The patterned semiconductor layer is disposed on the gate dielectric layer. The source electrode and the drain electrode are respectively arranged on different sides of the patterned semiconductor layer and are electrically connected with the patterned semiconductor layer. The light blocking layer is configured on the patterned semiconductor layer and directly contacts the patterned semiconductor layer, wherein the light blocking layer is made of a non-metal material. The dielectric layer covers the light blocking layer, the source electrode and the drain electrode.
Description
Technical Field
The invention relates to a thin film transistor and a manufacturing method thereof.
Background
A thin film transistor is one of field effect transistors, and is often applied to a display device. The channel in the thin film transistor may be made using amorphous silicon or an oxide semiconductor. However, these semiconductor materials are very sensitive to light. When the oxide semiconductor is irradiated by light, the generated photoelectric effect has a great influence on the electrical property and stability of the thin film transistor. Therefore, a novel thin film transistor is needed to protect the oxide semiconductor from light.
Disclosure of Invention
The present invention is directed to a thin film transistor, which can prevent a semiconductor layer from being exposed to light to cause a leakage current and/or a threshold voltage shift, and can prevent a parasitic capacitance from being formed.
According to an aspect of the present invention, a thin film transistor is provided, which includes a substrate, a gate electrode, a gate dielectric layer, a patterned semiconductor layer, a source electrode, a drain electrode, a light blocking layer, and a dielectric layer. The grid is arranged on the substrate, and the grid dielectric layer is arranged on the grid. The patterned semiconductor layer is disposed on the gate dielectric layer. The source electrode and the drain electrode are respectively arranged on different sides of the patterned semiconductor layer and are electrically connected with the patterned semiconductor layer. The light blocking layer is configured on the patterned semiconductor layer and directly contacts the patterned semiconductor layer, wherein the light blocking layer is made of a non-metal material. The dielectric layer covers the light blocking layer, the source electrode and the drain electrode.
According to one or more embodiments of the present invention, the average transmittance of the light blocking layer to ultraviolet rays is 0.01 to 30%.
According to one or more embodiments of the present invention, the average transmittance of the light-blocking layer for blue light is less than 90%, wherein the wavelength of the blue light is 450-475 nm.
According to one or more embodiments of the present invention, the average transmittance of the light blocking layer to light having a wavelength of 1 to 600 nm is less than 80%.
According to one or more embodiments of the present invention, the light blocking layer has a distance from the source electrode to the drain electrode, and the distance is 2 to 20 micrometers.
According to one or more embodiments of the present invention, the light blocking layer completely covers the top surface of the patterned semiconductor layer, and the source and drain electrodes extend from the side surfaces of the patterned semiconductor layer to the light blocking layer, respectively.
According to another aspect of the present invention, there is provided a method for fabricating a semiconductor structure, comprising the steps of: providing a substrate; forming a gate electrode on a substrate; forming a gate dielectric layer to cover the gate; forming a semiconductor layer on the gate dielectric layer; forming a patterned photoresist layer on the semiconductor layer; patterning the semiconductor layer by patterning the photoresist layer to form a patterned semiconductor layer; performing blackening treatment, roughening treatment or combination thereof on the patterned photoresist layer to form a photoresist layer; forming a source electrode and a drain electrode on the grid dielectric layer, wherein the source electrode and the drain electrode are respectively contacted with different side walls of the patterned semiconductor layer; and forming a dielectric layer to cover the light blocking layer, the source electrode and the drain electrode.
According to one or more embodiments of the present invention, the step of forming the patterned photoresist layer comprises: forming a photoresist layer on the semiconductor layer; exposing the photoresist layer using a half tone (halftone) mask; and developing the photoresist layer to form a patterned photoresist layer, wherein the patterned photoresist layer comprises a first portion and a second portion, and the thickness of the first portion is greater than that of the second portion.
According to one or more embodiments of the present invention, before the step of performing the blackening treatment, the roughening treatment or the combination thereof on the patterned photoresist layer, an ashing (ashing) process is performed to remove a first portion of the patterned photoresist layer to expose a portion of the patterned semiconductor layer.
According to one or more embodiments of the present invention, the blackening process includes performing a baking process on the patterned photoresist layer to form the photoresist layer.
According to one or more embodiments of the present invention, the temperature of the baking process is 110 ℃ to 280 ℃.
According to one or more embodiments of the present invention, the roughening process includes performing a dry etching process on the patterned photoresist layer to form the light blocking layer.
According to still another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising the steps of: providing a substrate; forming a gate electrode on a substrate; forming a gate dielectric layer to cover the gate; forming a source electrode and a drain electrode on the grid dielectric layer; forming a semiconductor layer on the source electrode and the drain electrode, wherein the semiconductor layer covers the grid dielectric layer, the source electrode and the drain electrode; forming a patterned photoresist layer on the semiconductor layer; patterning the semiconductor layer by patterning the photoresist layer to form a patterned semiconductor layer; performing blackening treatment, roughening treatment or combination thereof on the patterned photoresist layer to form a photoresist layer; and forming a dielectric layer to cover the light blocking layer, the source electrode, the drain electrode and the patterned semiconductor layer.
According to one or more embodiments of the present invention, the blackening process includes performing a baking process on the patterned photoresist layer to form the photoresist layer.
According to one or more embodiments of the present invention, the temperature of the baking process is 110 ℃ to 280 ℃.
According to one or more embodiments of the present invention, the roughening process includes performing a dry etching process on the patterned photoresist layer to form the light blocking layer.
Compared with the prior art, the thin film transistor can effectively prevent light from irradiating the semiconductor layer, and avoid the critical voltage deviation of the semiconductor layer from influencing the electrical property of the thin film transistor. In addition, the manufacturing method of the thin film transistor can manufacture the thin film transistor, does not need to strip the photoresist used in the patterning semiconductor layer, and also reduces the process difficulty.
Drawings
Fig. 1 shows a tft generally including a light blocking layer.
Fig. 2 is a schematic cross-sectional view of a thin film transistor according to some embodiments of the invention.
Fig. 3 is a schematic cross-sectional view of a thin film transistor according to some embodiments of the invention.
Fig. 4 is a schematic cross-sectional view of a thin film transistor according to some embodiments of the invention.
Fig. 5A to 5I illustrate a method of fabricating a thin film transistor according to some embodiments of the present invention.
Fig. 6A to 6F illustrate a method of fabricating a thin film transistor according to some embodiments of the present invention.
Fig. 7A to 7G illustrate a method of fabricating a thin film transistor according to some embodiments of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present description. Of course, these examples are merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature encompasses embodiments in which the first feature is in direct contact with the second feature, and embodiments in which the first feature is not in direct contact with the second feature are also encompassed.
Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, the formation, connection, and/or coupling of a feature to another feature in the present disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features are formed interposing the features, such that the features may not be in direct contact. Further, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the elements in use or operation.
In addition, the "source" and "drain" in the present invention may be interchanged according to different designs. Thus, in some embodiments, a "source" described below may be a "drain" and a "drain" may be a "source".
Referring to fig. 1, a cross-sectional view of a typical tft with a light blocking layer is shown. As shown, the light blocking layer 110 is disposed on the dielectric layer 120, and the light blocking layer 110 is made of metal. Therefore, parasitic capacitances are easily formed between the light blocking layer 110 and the source 130, the drain 140, and the light blocking layer 110 and the gate 150. In fig. 1, the position of the parasitic capacitance is indicated by a dotted line. The parasitic capacitance affects the electrical characteristics of the tft 100, resulting in a decrease in performance of the tft 100. Therefore, a novel thin film transistor is required to improve the problem of parasitic capacitance and simultaneously protect the semiconductor layer from light irradiation.
The invention provides a thin film transistor, which can prevent a semiconductor layer from being irradiated by light to cause leakage current and/or critical voltage deviation, and can prevent parasitic capacitance from being formed.
Referring to fig. 2, a cross-sectional view of a thin film transistor 200 according to some embodiments of the invention is shown. The thin film transistor 200 includes a substrate 210, a gate electrode 220, a gate dielectric layer 230, a patterned semiconductor layer 240, a source electrode 250, a drain electrode 260, a light blocking layer 270, and a dielectric layer 280. In the thin film transistor 200, a gate electrode 220 is located on a substrate 210, and a gate dielectric layer 230 covers the gate electrode 220. The patterned semiconductor layer 240, the source 250 and the drain 260 are disposed on the gate dielectric layer 230, wherein the source 250 is in contact with the side 241 of the patterned semiconductor layer 240, and the drain 260 is in contact with the side 242 of the patterned semiconductor layer 240, so that the source 250 and the drain 260 are disposed on different sides of the patterned semiconductor layer 240. It is noted that the source 250 and the drain 260 extend from the side surfaces 241 and 242 of the patterned semiconductor layer 240 to the top surface 243 of the patterned semiconductor layer 240, respectively. That is, the source 250 and the drain 260 are electrically connected to the patterned semiconductor layer 240 through the side 241, the side 242, and the top 243 of the patterned semiconductor layer 240.
The light blocking layer 270 is positioned on the patterned semiconductor layer 240 and directly contacts the patterned semiconductor layer 240. In some embodiments, the light blocking layer 270 covers only a portion of the patterned semiconductor layer 240, and the source electrode 250 and the drain electrode 260 also cover only another portion of the patterned semiconductor layer 240, wherein the light blocking layer 270 and the source electrode 250 and the drain electrode 260 do not contact each other. Further, the light-blocking layer 270 and the source and drain electrodes 250 and 260 have a pitch P therebetween, and the pitch P is about 2 microns to about 20 microns, such as 3 microns, 4 microns, 5 microns, 10 microns, or 15 microns. Since the light blocking layer 270 has a distance P from the source and drain electrodes 250 and 260, a portion of the patterned semiconductor layer 240 is exposed. The dielectric layer 280 fills the gap between the light blocking layer 270 and the source and drain electrodes 250 and 260 and contacts the exposed patterned semiconductor layer 240. The pitch P provides process margin, thereby increasing process yield.
The dielectric layer 280 covers the patterned semiconductor layer 240, the source electrode 250, the drain electrode 260, and the light blocking layer 270.
In the thin film transistor 200 shown in fig. 2, no parasitic capacitance is generated because no metal light blocking layer is disposed above the source 250, the drain 260 and the gate 220. In addition, since the source 250 and the drain 260 respectively extend from the sidewalls 241 and 242 of the patterned semiconductor layer 240 to the top surface 243, the contact area between the source 250 and the drain 260 and the patterned semiconductor layer 240 is large, and the electrical connection effect is good.
Another aspect of the present invention provides a pixel structure, which includes the thin film transistor 200 and the pixel electrode layer 290, as shown in fig. 2. In some embodiments, the material of the pixel electrode layer 290 may be indium tin oxide. The pixel electrode layer 290 is electrically connected to the source electrode 250 or the drain electrode 260, such that the pixel electrode layer 290 is electrically connected to the data line. In some embodiments, the dielectric layer 280 includes an opening 281, the opening 281 exposes the source electrode 250 or the drain electrode 260, and the pixel electrode layer 290 is electrically connected to the source electrode 250 or the drain electrode 260 through the opening 281.
Referring to fig. 3, a cross-sectional view of a thin film transistor 300 according to some embodiments of the invention is shown. Similar to the thin film transistor 200 shown in fig. 2, the thin film transistor 300 includes a substrate 310, a gate electrode 320, a gate dielectric layer 330, a patterned semiconductor layer 340, a source electrode 350, a drain electrode 360, a light blocking layer 370 and a dielectric layer 380, wherein the substrate 310, the gate electrode 320 and the gate dielectric layer 330 may be the same as or similar to the substrate 210, the gate electrode 220 and the gate dielectric layer 230 shown in fig. 2, and are not repeated herein. The patterned semiconductor layer 340, the source 350, and the drain 360 are disposed on the gate dielectric layer 330, and the light blocking layer 370 is disposed on the patterned semiconductor layer 340. The source 350 and the drain 360 contact the sidewalls 341 and 342 of the patterned semiconductor layer 340, respectively, and extend from the sidewalls 341 and 342 of the patterned semiconductor layer 340 to the top surface 371 of the light blocking layer 370. The source 350 and the drain 360 are electrically connected to the patterned semiconductor layer 340 through the sidewall 341 and the sidewall 342 of the patterned semiconductor layer 340, respectively. It is noted that the light blocking layer 370 completely covers the top surface 343 of the patterned semiconductor layer 340.
Since the light blocking layer 370 completely covers the top surface 343 of the patterned semiconductor layer 340, the patterned semiconductor layer 340 is completely protected, and the threshold voltage shift of the patterned semiconductor layer 340 caused by the light irradiating the patterned semiconductor layer 340 is prevented from affecting the electrical property of the thin film transistor 300.
In addition, the dielectric layer 380 covers the source 350, the drain 360 and the light blocking layer 370.
Another aspect of the present invention provides a pixel structure, which includes the thin film transistor 300 and the pixel electrode layer 390, as shown in fig. 3. In some embodiments, the material of the pixel electrode layer 390 may be indium tin oxide. The pixel electrode layer 390 is electrically connected to the source electrode 350 or the drain electrode 360, such that the pixel electrode layer 390 is electrically connected to the data line. In some embodiments, the dielectric layer 380 includes an opening 381, the opening 381 exposes the source electrode 350 or the drain electrode 360, and the pixel electrode layer 390 is electrically connected to the source electrode 350 or the drain electrode 360 through the opening 381.
In the thin film transistor 300 shown in fig. 3, no parasitic capacitance is generated because no metal light blocking layer is disposed above the source 350, the drain 360 and the gate 320. Moreover, since the light blocking layer 370 completely covers the top surface 343 of the patterned semiconductor layer 340, the patterned semiconductor layer 340 is completely prevented from being irradiated by light.
Referring to fig. 4, a cross-sectional view of a tft 400 according to some embodiments of the invention is shown. Similar to the embodiment shown in fig. 2, the thin film transistor 400 of fig. 4 includes a substrate 410, a gate 420, a gate dielectric layer 430, a patterned semiconductor layer 440, a source 450, a drain 460, a light blocking layer 470 and a dielectric layer 480, wherein the substrate 410, the gate 420 and the gate dielectric layer 430 are the same as or similar to the substrate 210, the gate 220 and the gate dielectric layer 230, and are not repeated herein.
The source electrode 450 and the drain electrode 460 are disposed on the gate dielectric layer 430, and the patterned semiconductor layer 440 is disposed on the source electrode 450 and the drain electrode 460. Further illustrated, the patterned semiconductor layer 440 extends along the source 450 and drain 460 electrodes and contacts the gate dielectric layer 430. Therefore, the contact area between the patterned semiconductor layer 440 and the source and drain electrodes 450 and 460 is large, and the electrical connection therebetween is also preferable. In addition, unlike the embodiment shown in fig. 2 and 3, in the thin film transistor 400, the gap between the source electrode 450 and the drain electrode 460 is filled with the patterned semiconductor layer 440.
It is noted that the light-blocking layer 470 completely covers the top surface 441 of the patterned semiconductor layer 440, so as to prevent light from irradiating the patterned semiconductor layer 440. Therefore, the thin film transistor 400 has both good electrical connection and excellent light blocking.
The dielectric layer covers the source electrode 450, the drain electrode 460, the patterned semiconductor layer 440, and the light blocking layer 470.
Another aspect of the present invention is to provide a pixel structure, which includes the thin film transistor 400 and the pixel electrode layer 490, as shown in fig. 4. In some embodiments, the material of the pixel electrode layer 490 may be indium tin oxide. The pixel electrode layer 490 is electrically connected to the source electrode 450 or the drain electrode 460, such that the pixel electrode layer 490 is electrically connected to the data line. In some embodiments, the dielectric layer 480 includes an opening 481, the opening 481 exposes the source electrode 450 or the drain electrode 460, and the pixel electrode layer 490 is electrically connected to the source electrode 450 or the drain electrode 460 through the opening 481.
In some embodiments, the material of the patterned semiconductor layer 240, the patterned semiconductor layer 340 and the patterned semiconductor layer 440 may be, for example, a metal oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) or a combination thereof.
In some embodiments, the average transmittance of the light blocking layer 270, the light blocking layer 370, and the light blocking layer 470 is about 0.01% to about 30%, for example, 0.05%, 0.1%, 0.5%, 1%, 5%, 10%, 15%, 20%, or 25%. In some embodiments, the average transmittance of the light blocking layer 270, the light blocking layer 370, and the light blocking layer 470 for blue light is less than about 90%, such as 85%, 80%, 30%, 25%, 20%, 15%, or 10%, wherein the wavelength range of blue light is 450-475 nm. In still other embodiments, the average transmittance of light blocking layer 270, light blocking layer 370, and light blocking layer 470 for light having a wavelength of 1-600 nanometers is less than about 80%, such as 75%, 65%, 55%, 50%, 45%, or 40%. Further, in some embodiments, light blocking layer 270, light blocking layer 370, and light blocking layer 470 have a thickness of about 0.5 microns to about 5 microns, such as 1 micron, 2 microns, 3 microns, or 4 microns.
In some embodiments, the material of the light blocking layer 270, the light blocking layer 370 and the light blocking layer 470 may be, for example, a phenolic resin, an acryl resin or a polyimide resin (polyimide). In certain embodiments, the materials of light blocking layer 270, light blocking layer 370, and light blocking layer 470 comprise carbon.
The invention also provides a manufacturing method of the thin film transistor. Referring to fig. 5A to 5I, methods of fabricating a thin film transistor according to some embodiments of the invention are illustrated. First, as shown in fig. 5A, a substrate 210 is provided, a gate 220 is formed on the substrate 210, and a gate dielectric layer 230 is formed to cover the gate 220.
Thereafter, as shown in fig. 5B, a semiconductor layer 235 is formed on the gate dielectric layer 230. In some embodiments, the semiconductor layer 235 is conformally formed on the gate dielectric layer 230. In some embodiments, the material of the semiconductor layer 235 is a metal oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), or a combination thereof.
Then, as shown in fig. 5C, a photoresist layer 245 is formed on the semiconductor layer 235. In some embodiments, the photoresist layer 245 may be formed using a coating and drying process. The material of the photoresist layer 245 may be a phenolic resin, an acryl resin, a polyimide resin (polyimide), or other suitable photoresist materials.
Next, referring to fig. 5D, a patterning process is performed on the photoresist layer 245 to form a patterned photoresist layer 255. It is noted that the patterning process includes exposing the photoresist layer 245 using a half tone (halftone) mask and developing the photoresist layer 245 to form the patterned photoresist layer 255. Therefore, the thickness of the patterned photoresist layer 255 is not uniform, but has a thickness distribution according to the design of the halftone mask. The patterned photoresist layer 255 includes a first portion 2551 and a second portion 2552, wherein the thickness of the first portion 2551 is greater than the thickness of the second portion 2552. Further, the thickness distribution of the first portion 2551 and the second portion 2552 can be different according to the design of the halftone mask.
As shown in fig. 5E, a patterning process is performed on the semiconductor layer 235 by patterning the photoresist layer 255 to form a patterned semiconductor layer 240. In some embodiments, the patterning process includes wet etching the semiconductor layer 235 using the patterned photoresist layer 255 as a mask. Similar to a general wet etching process, the semiconductor layer 235 covered by the patterned photoresist layer 255 is not etched, so the thickness of the patterned photoresist layer 255 does not affect the etching quality.
Next, as shown in fig. 5F, an ashing (ashing) process is performed on the patterned photoresist layer 255. The ashing process reduces the thickness of the patterned photoresist layer 255, and thus the thinner portions of the patterned photoresist layer 255 are etched away. In some embodiments, the ashing process includes removing the second portion 2552 of the patterned photoresist layer 255 while leaving the first portion 2551 of the patterned photoresist layer 255, thereby exposing a portion of the patterned semiconductor layer 240. In addition, the ashing process also removes portions of first portion 2551, such that the thickness of first portion 2551 is reduced.
Thereafter, in some embodiments, as shown in fig. 5G, a blackening process may be performed on the first portion 2551 of the remaining patterned photoresist layer 255 to form the photoresist layer 270. The blackening process includes a baking process, which can make the first portion 2551 of the patterned photoresist layer 255 turn black, and the blackening degree of the first portion 2551 of the patterned photoresist layer 255 is different according to the temperature of the baking process. In some embodiments, the baking process carbonizes a portion of the first portion 2551 of the patterned photoresist layer 255, thereby achieving the light blocking effect. In certain embodiments, the temperature of the baking process may be 110 ℃ to 280 ℃, such as 150 ℃, 200 ℃, or 250 ℃.
Referring to fig. 5H, in some embodiments, a roughening process may be performed on the first portion 2551 of the patterned photoresist layer 255 to form the light-blocking layer 270. The roughening process may include a dry etching process. In further detail, the dry etching process may roughen the surface of the first portion 2551 of the patterned photoresist layer 255, so as to prevent the light from directly irradiating the patterned semiconductor layer 240 through the first portion 2551 of the patterned photoresist layer 255.
Both the blackening treatment and the roughening treatment can reduce the transmittance of the first portion 2551 of the patterned photoresist layer 255 to light. Accordingly, in some embodiments, only the blackening process may be performed on the first portion 2551 of the patterned photoresist layer 255. In other embodiments, only the roughening process may be performed on the first portion 2551 of the patterned photoresist layer 255. In still other embodiments, a blackening process and a roughening process may be performed on the first portion 2551 of the patterned photoresist layer 255.
Thereafter, as shown in fig. 5I, a source electrode 250 and a drain electrode 260 are formed on the patterned semiconductor layer 240. In some embodiments, a portion of the source electrode 250 and the drain electrode 260 is disposed on the gate dielectric layer 230, and another portion of the source electrode 250 and the drain electrode 260 is disposed on the patterned semiconductor layer 240. In detail, the source electrode 250 and the drain electrode 260 extend from the sidewall 241 and the sidewall 242 of the patterned semiconductor layer 240 to the top surface 243 of the patterned semiconductor layer 240, respectively. Therefore, the source 250 and the drain 260 are in contact with the sidewall 241, the sidewall 242 and the top surface 243 of the patterned semiconductor layer 240, so that the source 250 and the drain 260 are better electrically connected with the patterned semiconductor layer 240, and the contact resistance (contact resistance) is smaller. The source and drain electrodes 250 and 260 have a pitch P with respect to the light blocking layer 270, where the pitch P is at least 2 micrometers, such as 3 micrometers, 4 micrometers, or 5 micrometers. The spacing P between the source 250 and drain 260 and the light blocking layer 270 provides a larger process margin, thereby improving process yield.
In addition, a dielectric layer 280 may be formed to cover the source 250, the drain 260, the patterned semiconductor layer 240 and the light blocking layer 270. In some embodiments, the dielectric layer 280 fills the gap between the source and drain electrodes 250 and 260 and the light blocking layer 270. In some embodiments, the dielectric layer 280 includes an opening 281, and the pixel electrode 290 is formed on the dielectric layer 280 and electrically connected to the source electrode 250 or the drain electrode 260 through the opening 281.
The invention also provides another manufacturing method of the thin film transistor. Referring to fig. 6A to 6F, methods of fabricating a thin film transistor according to some embodiments of the invention are shown. As shown in fig. 6A, a substrate 310 is provided, a gate electrode 320 is formed on the substrate 310, and a gate dielectric layer 330 is formed to cover the gate electrode 320.
As shown in fig. 6B, a semiconductor layer 335 is formed on the gate dielectric layer 330. Thereafter, as shown in fig. 6C, a patterned photoresist layer 355 is formed on the semiconductor layer 335. Unlike the patterned photoresist layer 255 shown in fig. 5D, the thickness of the patterned photoresist layer 355 is more uniform. Next, as shown in fig. 6D, a patterning process is performed on the semiconductor layer 335 by patterning the photoresist layer 355 to form a patterned semiconductor layer 340, wherein the patterned photoresist layer 355 completely covers a top surface 343 of the patterned semiconductor layer 340.
Thereafter, as shown in fig. 6E, a blackening process, a roughening process, or a combination thereof is performed on the patterned photoresist layer 355 to form a light blocking layer 370. As described above, the blackening treatment may include a baking process, which makes the patterned photoresist layer 355 blacker. In some embodiments, the baking process carbonizes at least a portion of the patterned photoresist layer 355, thereby achieving the effect of blocking light. In certain embodiments, the temperature of the baking process may be 110 ℃ to 280 ℃, such as 150 ℃, 200 ℃, or 250 ℃. In some embodiments, the roughening process may comprise a dry etching process. In further detail, the dry etching process may roughen the surface of the patterned photoresist layer 355 to prevent the light from directly irradiating the patterned semiconductor layer 340 through the patterned photoresist layer 355. In some embodiments, the light blocking layer 370 completely covers the top surface 343 of the patterned semiconductor layer 340.
Next, as shown in fig. 6F, a source 350 and a drain 360 are formed on the gate dielectric layer 330, wherein the source 350 and the drain 360 extend from the side 341 and the side 342 of the patterned semiconductor layer to the top 371 of the light-blocking layer 370. Then, a dielectric layer 380 is formed to cover the source 350, the drain 360 and the light blocking layer 370. In some embodiments, dielectric layer 380 may include an opening 381. In some embodiments, a pixel electrode 390 may be formed on the dielectric layer 380, and the pixel electrode 390 is electrically connected to the source electrode 350 or the drain electrode 360 through the opening 381.
The invention also provides another manufacturing method of the thin film transistor. Referring to fig. 7A to 7G, methods of fabricating a thin film transistor according to some embodiments of the invention are illustrated. Referring to fig. 7A, a substrate 410 is provided, and a gate 420 and a gate dielectric layer 430 are sequentially formed, wherein the gate 420 is formed on the substrate 410, and the gate dielectric layer 430 covers the gate 420.
Next, referring to fig. 7B and 7C, a source 450 and a drain 460 are formed on the gate dielectric layer 430, and a semiconductor layer 435 is formed on the source 450 and the drain 460. In some embodiments, the semiconductor layer 435 is conformally formed on the source 450, drain 460, and gate dielectric layer 430.
Thereafter, as shown in fig. 7D and 7E, a patterned photoresist layer 455 is formed on the semiconductor layer 435, and the semiconductor layer 435 is patterned by patterning the photoresist layer 455 to form a patterned semiconductor layer 440. The patterned photoresist layer 455 completely covers the top surface 441 of the patterned semiconductor layer 440.
Then, as shown in fig. 7F, a blackening process, a roughening process, or a combination thereof is performed on the patterned photoresist layer 455 to form a light blocking layer 470. As described above, the blackening process includes a baking process, and the roughening process includes a dry etching process. The baked patterned photoresist layer 455 has a darker color and thus is less likely to be penetrated by light. The roughened patterned photoresist layer 455 can scatter light due to the rough top surface, thereby preventing the light from directly irradiating the patterned semiconductor layer 440.
Referring to fig. 7G, a dielectric layer 480 is formed, wherein the dielectric layer 480 covers the source electrode 450, the drain electrode 460, the patterned semiconductor layer 440 and the light blocking layer 470. In some embodiments, the dielectric layer 480 includes an opening 481, and the opening 481 exposes a portion of the source 450 or the drain 460. In some embodiments, a pixel electrode 490 may also be formed on the dielectric layer 480 and in the opening 481, and the source electrode 450 or the drain electrode 460 may be electrically connected to an external wiring through the pixel electrode 490.
Some embodiments of the present invention are exemplarily described below, table 1 is test conditions of the embodiments, and table 2 is test data of the light-blocking layer of the embodiments.
TABLE 1
| Examples | Thickness of light blocking layer | Baking temperature | Dry etching |
| 1 | 1.5 |
220℃ | Is free of |
| 2 | 2.0 |
220℃ | Is free of |
| 3 | 1.5 micron | Without baking | Is provided with |
| 4 | 1.5 |
220℃ | Is provided with |
TABLE 2
In tables 1 and 2, examples 1 and 2 did not perform the dry etching process, and examples 3 and 4 performed the dry etching process. In addition, the baking process was not performed in example 3. As can be seen from the data in table 2, the light transmittance of the light blocking layer can be greatly reduced through the baking process or the dry etching process. For example, the average transmission of ultraviolet light is reduced to below about 30%. The average transmittance of the light-blocking layer to blue light is less than about 90% wherein the wavelength of the blue light is 450-475 nm. The wavelength range of the full band in table 2 is 1-600 nm, and the average transmittance of the light blocking layer is less than about 80% at the full band. As can be seen from example 4, the use of both the baking and dry etching processes can achieve a better light blocking effect. In addition, the light transmittance of the light-blocking layer is also affected by the thickness, and the greater the thickness of the light-blocking layer is, the lower the light transmittance is, and the better the light-blocking effect is.
The thin film transistor provided by the invention can effectively prevent light from irradiating the semiconductor layer, and the critical voltage deviation of the semiconductor layer is avoided, so that the electrical property of the thin film transistor is not influenced. In addition, the manufacturing method of the thin film transistor can manufacture the thin film transistor, does not need to strip the photoresist used in the patterning semiconductor layer, and reduces the process difficulty.
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (16)
1. A thin film transistor, comprising:
a substrate;
a gate electrode disposed on the substrate;
a gate dielectric layer disposed on the gate electrode;
a patterned semiconductor layer disposed on the gate dielectric layer;
the source electrode and the drain electrode are respectively arranged on different sides of the patterned semiconductor layer and are electrically connected with the patterned semiconductor layer;
the light blocking layer is configured on the patterned semiconductor layer and directly contacts the patterned semiconductor layer, wherein the light blocking layer is made of a non-metal material; and
and the dielectric layer covers the light blocking layer, the source electrode and the drain electrode.
2. The thin film transistor according to claim 1, wherein the light blocking layer has an average transmittance of 0.01 to 30% for ultraviolet rays.
3. The thin film transistor of claim 1, wherein the average transmittance of the light blocking layer to blue light is less than 90%, and wherein the wavelength of the blue light is 450-475 nm.
4. The thin film transistor of claim 1, wherein the average transmittance of the light blocking layer for light having a wavelength of 1 to 600 nm is less than 80%.
5. The thin film transistor according to claim 1, wherein the light blocking layer has a distance from the source electrode and the drain electrode, and the distance is 2 to 20 μm.
6. The thin film transistor of claim 1, wherein the light blocking layer completely covers a top surface of the patterned semiconductor layer, and the source electrode and the drain electrode extend from a side surface of the patterned semiconductor layer onto the light blocking layer, respectively.
7. A method for manufacturing a thin film transistor includes the steps of:
providing a substrate;
forming a gate electrode on the substrate;
forming a gate dielectric layer to cover the gate;
forming a semiconductor layer on the gate dielectric layer;
forming a patterned photoresist layer on the semiconductor layer;
patterning the semiconductor layer through the patterned photoresist layer to form a patterned semiconductor layer;
carrying out blackening treatment, roughening treatment or combination thereof on the patterned photoresist layer to form a photoresist layer;
forming a source electrode and a drain electrode on the gate dielectric layer, wherein the source electrode and the drain electrode respectively contact different sidewalls of the patterned semiconductor layer; and
and forming a dielectric layer to cover the light-blocking layer, the source electrode and the drain electrode.
8. The method of claim 7, wherein forming the patterned photoresist layer comprises:
forming a photoresist layer on the semiconductor layer;
exposing the photoresist layer by using a half-tone photomask; and
developing the photoresist layer to form the patterned photoresist layer, wherein the patterned photoresist layer comprises a first portion and a second portion, and the thickness of the first portion is greater than that of the second portion.
9. The method of claim 8, further comprising performing an ashing process to remove the first portion of the patterned photoresist layer to expose a portion of the patterned semiconductor layer prior to the step of performing the blackening treatment, the roughening treatment, or a combination thereof on the patterned photoresist layer.
10. The method of claim 7, wherein the blackening process comprises performing a baking process on the patterned photoresist layer to form the light blocking layer.
11. The method of claim 10, wherein the temperature of the baking process is 110 ℃ to 280 ℃.
12. The method of claim 7, wherein the roughening process comprises performing a dry etching process on the patterned photoresist layer to form the light blocking layer.
13. A method for manufacturing a thin film transistor includes the steps of:
providing a substrate;
forming a gate electrode on the substrate;
forming a gate dielectric layer to cover the gate;
forming a source and a drain on the gate dielectric layer;
forming a semiconductor layer on the source and the drain, wherein the semiconductor layer covers the gate dielectric layer, the source and the drain;
forming a patterned photoresist layer on the semiconductor layer;
patterning the semiconductor layer through the patterned photoresist layer to form a patterned semiconductor layer;
carrying out blackening treatment, roughening treatment or combination thereof on the patterned photoresist layer to form a photoresist layer; and
and forming a dielectric layer to cover the light-blocking layer, the source electrode, the drain electrode and the patterned semiconductor layer.
14. The method of claim 13, wherein the blackening process comprises performing a baking process on the patterned photoresist layer to form the light blocking layer.
15. The method of manufacturing of claim 14, wherein the temperature of the baking process is 110 ℃ to 280 ℃.
16. The method of claim 13, wherein the roughening process comprises performing a dry etching process on the patterned photoresist layer to form the light blocking layer.
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