CN111244046A - Three-dimensional memory, preparation method thereof and electronic equipment - Google Patents
Three-dimensional memory, preparation method thereof and electronic equipment Download PDFInfo
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- CN111244046A CN111244046A CN202010068208.2A CN202010068208A CN111244046A CN 111244046 A CN111244046 A CN 111244046A CN 202010068208 A CN202010068208 A CN 202010068208A CN 111244046 A CN111244046 A CN 111244046A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The application provides a three-dimensional memory, a preparation method of the three-dimensional memory and electronic equipment. The three-dimensional memory comprises a substrate and a dielectric layer. The substrate has a first region and a second region, and the first region is connected with the second region. The dielectric layer is arranged on one side of the base body and comprises a connecting piece and a radiating piece, and the connecting piece is connected with the base body. The radiating piece comprises a first radiating piece and a second radiating piece, the first radiating piece is connected with at least part of the second radiating piece, and the first radiating piece is arranged close to the base body compared with the second radiating piece. The first heat dissipation part is connected with at least part of the second heat dissipation part, so that the second heat dissipation part can absorb a large amount of heat during bonding, and when the heat absorbed by the part of the second heat dissipation part is too large, the heat can be conducted to the rest of the second heat dissipation part through the first heat dissipation part, and therefore the heat of the second heat dissipation part is uniformly distributed. The three-dimensional memory provided by the application can effectively prevent local heat from being too concentrated during bonding, and reduces the stability and the service life of the three-dimensional memory.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a three-dimensional memory, a preparation method of the three-dimensional memory and electronic equipment.
Background
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, and the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. For example, users desire stable performance and long lifetime of three-dimensional memories. However, a large amount of heat is generated when the memory array device chip and the peripheral device chip are bonded together, and the local heat is too concentrated due to uneven heat distribution, so that the stability and the service life of the three-dimensional memory are reduced.
Disclosure of Invention
In view of this, a first aspect of the present application provides a three-dimensional memory, comprising:
a substrate having a first region and a second region, the first region connecting the second region;
the dielectric layer is arranged on one side of the base body and comprises a connecting piece and a heat dissipation piece, the orthographic projection of the connecting piece on the base body is positioned in the first area, the orthographic projection of the heat dissipation piece on the base body is positioned in the second area, and the connecting piece is connected with the base body; the heat dissipation member comprises a first heat dissipation member and a second heat dissipation member, the first heat dissipation member is connected with at least part of the second heat dissipation member, and the first heat dissipation member is arranged close to the substrate compared with the second heat dissipation member.
The three-dimensional memory that this application first aspect provided is through making first heat dissipation part be close to than the second heat dissipation part the base member setting to control first heat dissipation part is connected to at least part of second heat dissipation part, and a plurality of second heat dissipation parts can absorb a large amount of heats when bonding like this, and when the heat that some second heat dissipation parts absorb was too big, the second heat dissipation part of remaining connection is given with heat conduction to accessible first heat dissipation part, thereby makes the heat distribution of second heat dissipation part even. The three-dimensional memory provided by the application can effectively prevent local heat from being too concentrated during bonding, and reduces the stability and the service life of the three-dimensional memory.
Wherein the first heat sink member is spaced apart from the base.
The dielectric layer further comprises an insulating piece arranged between the connecting piece and the radiating piece, and one side, deviating from the base body, of the radiating piece is flush with one side, deviating from the base body, of the insulating piece.
The first heat dissipation part is provided with a through hole, and the through hole penetrates through the surface close to the second heat dissipation part and the surface departing from the second heat dissipation part.
When the number of the through holes is one, the through holes are distributed in a snake shape, a zigzag shape or a ring shape; or when the number of the through holes is multiple, the through holes are arranged in an array.
The through holes are polygonal in shape, and when the number of the through holes is multiple, the edges of the second heat dissipation part corresponding to the through holes are connected with the first heat dissipation part.
And one second heat dissipation part is connected between every two adjacent through holes.
The base body comprises a first substrate, a peripheral device layer and a peripheral interconnection layer, wherein the peripheral device layer is arranged on one side of the first substrate, the peripheral interconnection layer is arranged on one side, away from the first substrate, of the peripheral device layer, and the dielectric layer is arranged on one side, away from the first substrate, of the peripheral interconnection layer;
or, the base body comprises a second substrate, a storage array device layer and an array interconnection layer, the storage array device layer is arranged on one side of the second substrate, the array interconnection layer is arranged on one side, deviating from the second substrate, of the storage array device layer, and the dielectric layer is arranged on one side, deviating from the second substrate, of the array interconnection layer.
A second aspect of the application provides an electronic device comprising a three-dimensional memory as provided in the first aspect of the application and a processor for writing data into the three-dimensional memory and reading data from the three-dimensional memory.
The electronic equipment that this application second aspect provided, through utilizing the three-dimensional storage that this application first aspect provided, make first heat dissipation part compare and be close to in the second heat dissipation part the base member sets up, and control first heat dissipation part and be connected to few part second heat dissipation part, the second heat dissipation part can absorb a large amount of heats when carrying out the bonding like this, and when the absorptive heat of part second heat dissipation part was too big, the first heat dissipation part of accessible conducts the heat for remaining second heat dissipation part, thereby make the heat distribution of second heat dissipation part even, can effectively improve electronic equipment's stability and life.
A third aspect of the present application provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a substrate having a first region and a second region, the first region connecting the second region;
forming a dielectric layer on one side of the substrate, wherein the dielectric layer comprises a connecting piece and a heat dissipation piece, the orthographic projection of the connecting piece on the substrate is positioned in the first area, the orthographic projection of the heat dissipation piece on the substrate is positioned in the second area, and the connecting piece is connected with the substrate; the heat dissipation member comprises a first heat dissipation member and a second heat dissipation member, the first heat dissipation member is connected with at least part of the second heat dissipation member, and the first heat dissipation member is arranged close to the substrate compared with the second heat dissipation member.
In the preparation method provided by the third aspect of the present application, the first heat sink member and the second heat sink member are formed, so that the first heat sink member is disposed closer to the substrate than the second heat sink member, and the first heat sink member is connected to at least a part of the second heat sink member. The second heat dissipation part can absorb a large amount of heat during bonding, and when the heat absorbed by part of the second heat dissipation part is too large, the heat can be conducted to the rest of the second heat dissipation parts through the first heat dissipation part, so that the heat of the second heat dissipation part is uniformly distributed. The preparation method provided by the application can effectively prevent the local heat from being too concentrated during bonding, and reduces the stability and the service life of the three-dimensional memory.
Wherein the "forming a dielectric layer on one side of the substrate" includes:
forming a first sub-dielectric layer on one side of the substrate, wherein the first sub-dielectric layer comprises a first connecting part and a first heat dissipation part, the orthographic projection of the first connecting part on the substrate is positioned in the first region, the orthographic projection of the first heat dissipation part on the substrate is positioned in the second region, the first connecting part is connected with the substrate, and the first heat dissipation part and the substrate are arranged at intervals;
the second sub-dielectric layer is formed on one side, away from the substrate, of the first sub-dielectric layer, the second sub-dielectric layer comprises a second connecting portion and a second heat dissipation portion, the orthographic projection of the second connecting portion on the substrate is located in the first area, the orthographic projection of the second heat dissipation portion on the substrate is located in the second area, the second connecting portion is connected with the first connecting portion, and at least part of the second heat dissipation portion is connected with the first heat dissipation portion.
Wherein the "forming the first sub-dielectric layer on one side of the substrate" includes:
depositing a first insulating layer on one side of the base body, and etching the first insulating layer in the first area so that one side, facing away from the base body, of the first insulating layer in the second area is higher than one side, facing away from the base body, of the first insulating layer in the first area;
simultaneously forming a first connecting part and a first heat dissipation part in the first insulating layer, wherein the orthographic projection of the first connecting part on the substrate is positioned in the first area, the orthographic projection of the first heat dissipation part on the substrate is positioned in the second area, the first connecting part is connected with the substrate, and the first heat dissipation part and the substrate are arranged at intervals; and
and flattening the first insulating layer positioned in the second area so that the side, facing away from the base body, of the first insulating layer positioned in the second area is flush with the side, facing away from the base body, of the first insulating layer positioned in the first area.
Wherein, after the step of performing planarization treatment on the first insulating layer located in the second region, the method further comprises:
and etching the first heat dissipation part to enable the first heat dissipation part to be provided with a plurality of through holes which are arranged in an array mode.
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a schematic diagram of a three-dimensional memory according to a first embodiment of the present application.
Fig. 2 is a schematic diagram of a three-dimensional memory according to a second embodiment of the present application.
Fig. 3 is a schematic diagram of a three-dimensional memory according to a third embodiment of the present application.
Fig. 4 is a schematic diagram of a three-dimensional memory according to a fourth embodiment of the present application.
Fig. 5 is a schematic diagram of a three-dimensional memory according to a fifth embodiment of the present application.
Fig. 6 is a schematic diagram of a three-dimensional memory according to a sixth embodiment of the present application.
Fig. 7 is a schematic view of a first heat sink member according to a first embodiment of the present disclosure.
Fig. 8 is a schematic view of a first heat sink member according to a second embodiment of the present application.
Fig. 9 is a schematic view of a first heat sink member according to a third embodiment of the present application.
Fig. 10 is a schematic view of a first heat sink member according to a fourth embodiment of the present application.
Fig. 11 is a process flow diagram of a manufacturing method according to a first embodiment of the present disclosure.
Fig. 12 is a process flow diagram of a manufacturing method according to a second embodiment of the present application.
Fig. 13-14 are schematic diagrams of the three-dimensional memory corresponding to steps S110 and S120 in fig. 12, respectively.
Fig. 15 is a process flow diagram of a manufacturing method according to a third embodiment of the present application.
Fig. 16-18 are schematic diagrams of the three-dimensional memory corresponding to steps S111, S112, and S113 in fig. 15, respectively.
Fig. 19 is a process flow diagram of a manufacturing method according to a fourth embodiment of the present application.
Fig. 20 is a schematic diagram of the three-dimensional memory corresponding to step S114 in fig. 19.
Description of reference numerals:
the three-dimensional memory comprises a three-dimensional memory body-1, a base body-10, a first region-11, a second region-12, a first substrate-13, a peripheral device layer-14, a peripheral interconnection layer-15, a second substrate-16, a memory array device layer-17, an array interconnection layer-18, a dielectric layer-20, a first sub-dielectric layer-201, a second sub-dielectric layer-202, a connecting piece-21, a first connecting piece-211, a second connecting piece-212, a heat dissipation piece-22, a first heat dissipation piece-221, a through hole-2211, a second heat dissipation piece-222, an insulating piece-23 and a first insulating layer-24.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications are also considered as the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic view of a three-dimensional memory according to a first embodiment of the present disclosure. In the present embodiment, the three-dimensional memory 1 includes a substrate 10 and a dielectric layer 20. Wherein the substrate 10 has a first region 11 and a second region 12, the first region 11 connecting the second region 12. The dielectric layer 20 is arranged on one side of the substrate 10, the dielectric layer 20 comprises a connector 21 and a heat sink 22, an orthographic projection of the connector 21 on the substrate 10 is located in the first region 11, an orthographic projection of the heat sink 22 on the substrate 10 is located in the second region 12, and the connector 21 is connected with the substrate 10; the heat dissipation member 22 includes a first heat dissipation member 221 and a second heat dissipation member 222, the first heat dissipation member 221 is connected to at least a portion of the second heat dissipation member 222, and the first heat dissipation member 221 is disposed closer to the substrate 10 than the second heat dissipation member 222.
The substrate 10 provided in the present application serves to form the dielectric layer 20 and functions as a substrate. As can be seen from the above, the three-dimensional memory 1 may include a memory array device chip and/or a peripheral device chip. The substrate 10 provided herein may be a peripheral device substrate 10 or a memory array device substrate 10. Please refer to fig. 2 and fig. 3 together. Fig. 2 is a schematic diagram of a three-dimensional memory according to a second embodiment of the present application. Fig. 3 is a schematic diagram of a three-dimensional memory according to a third embodiment of the present application. When the base 10 is a peripheral device base 10, referring to fig. 2, the base 10 includes a first substrate 13, a peripheral device layer 14, and a peripheral interconnection layer 15, the peripheral device layer 14 is disposed on one side of the first substrate 13, the peripheral interconnection layer 15 is disposed on one side of the peripheral device layer 14 away from the first substrate 13, and the dielectric layer 20 is disposed on one side of the peripheral interconnection layer 15 away from the first substrate 13. In which a plurality of structural elements are provided in the peripheral interconnect layer 15, which structural elements need to be electrically connected to other structural elements in the three-dimensional memory 1, and therefore subsequently a connector 21 needs to be provided in the dielectric layer 20 to extract the structural elements. When the base 10 is a memory array device base 10, referring to fig. 3, the base 10 includes a second substrate 16, a memory array device layer 17, and an array interconnection layer 18, the memory array device layer 17 is disposed on one side of the second substrate 16, the array interconnection layer 18 is disposed on one side of the memory array device layer 17 facing away from the second substrate 16, and the dielectric layer 20 is disposed on one side of the array interconnection layer 18 facing away from the second substrate 16. Here, a plurality of structural elements are also provided in the array interconnection layer 18, and these structural elements also need to be electrically connected with other structural elements in the three-dimensional memory 1, so that connectors 21 need to be provided in the dielectric layer 20 to lead out the structural elements.
In addition, the substrate 10 has a first region 11 and a second region 12, wherein the first region 11 may be a region corresponding to a structure in the peripheral interconnection layer 15 or the array interconnection layer 18, and the first region 11 may also be referred to as a connection region. The second region 12 is a region of the peripheral interconnection layer 15 or the array interconnection layer 18 without a structural member, and the region is mainly used for improving the bonding effect between the memory array device chip and the peripheral device chip and improving the connection performance and the heat dissipation performance, and the second region 12 may also be referred to as a heat dissipation region.
The dielectric layer 20 provided in the present application is disposed on the substrate 10, and the dielectric layer 20 includes a connector 21 and a heat sink 22. The connecting member 21 is disposed corresponding to the first region 11 and connected to the substrate 10, and the connecting member 21 is used for leading out the structural member in the peripheral interconnection layer 15 or the array interconnection layer 18 to be electrically connected to other structural members. And the heat dissipation member 22 is disposed corresponding to the second region 12. The heat sink 22 includes a first heat sink 221 disposed close to the substrate 10 and a second heat sink 222 disposed far from the substrate 10. The second heat sink piece 222 is used to provide a bonding contact point to improve the connection effect. The second heat sink piece 222 can also be used to absorb heat generated during bonding.
In the prior art, each second heat sink piece 222 is connected to one first heat sink piece 221. This corresponds to each of the second heat sink members 222 individually absorbing heat generated upon bonding and storing the heat therein. The heat is not evenly distributed to each of the second heat sink pieces 222, and typically some of the second heat sink pieces 222 absorb more heat while the remaining second heat sink pieces 222 absorb less heat. Therefore, excessive heat absorbed into the second heat sink 222 may cause excessive local heat concentration in the three-dimensional memory 1, which may affect other structural members in the three-dimensional memory 1, thereby reducing the stability and lifespan of the three-dimensional memory 1. Therefore, in the present invention, only one first heat sink part 221 is provided, or it can be understood that a plurality of first heat sink parts 221 in the prior art are integrated together to form one first heat sink part 221, so that the first heat sink part 221 is disposed closer to the substrate 10 than the second heat sink part 222, and the first heat sink part 221 is controlled to be connected to at least part of the second heat sink part 222. In this way, the second heat sink member 222 absorbs a large amount of heat during bonding, and when the amount of heat absorbed by some of the second heat sink members 222 is too large, the heat can be conducted to the remaining second heat sink members 222 through the first heat sink member 221, so that the heat of the second heat sink members 222 is uniformly distributed. The three-dimensional memory 1 provided by the application can effectively prevent the local heat from being too concentrated during bonding, and reduces the stability and the service life of the three-dimensional memory 1. In the drawings, all the second heat sink members 222 are connected to the first heat sink member 221. Of course, it is within the scope of the present application that a portion of the second heat sink piece 222 is connected to the first heat sink piece 221.
Referring to fig. 4, fig. 4 is a schematic view of a three-dimensional memory according to a fourth embodiment of the present disclosure. In this embodiment, the first heat sink member 221 is provided at a distance from the base 10.
The first heat dissipation part 221 and the substrate 10 can be arranged at intervals, namely, the first heat dissipation part 221 is not connected with the substrate 10, and a certain gap is formed between the first heat dissipation part 221 and the substrate 10, so that the first heat dissipation part 221 can prevent heat from being conducted to the structural members in the peripheral interconnection layer 15 or the array interconnection layer 18 after heat of the second heat dissipation part 222 is conducted to the first heat dissipation part 221, and the stability and the service life of the three-dimensional memory 1 are affected.
Referring to fig. 5, fig. 5 is a schematic view of a three-dimensional memory according to a fifth embodiment of the present application. In this embodiment, the dielectric layer 20 further includes an insulating element 23 disposed between the connecting element 21 and the heat dissipating element 22, and one side of the connecting element 21 and one side of the heat dissipating element 22, which are away from the substrate 10, are flush with one side of the insulating element 23, which is away from the substrate 10.
The dielectric layer 20 provided by the present application may further include an insulating member 23, wherein the insulating member 23 is used to fix the connector 21 and the heat sink 22. The insulating member 23 also serves to electrically isolate the connecting member 21 from the heat sink 22. Specifically, the present application may now form the insulating member 23 on the substrate 10, then etch a hole in the insulating member 23 by a photolithography process, and finally deposit various materials in the hole to finally form the connecting member 21 and the insulating member 23. This application can make connecting piece 21 with one side that heat dissipation piece 22 deviates from base member 10 with one side that insulating part 23 deviates from base member 10 flushes, can make the terminal surface that dielectric layer 20 deviates from base member 10 become more level and more smooth like this, reduces its roughness, can be more favorable to carrying out the bonding, improves three-dimensional memory 1's connection performance.
Referring to fig. 6, fig. 6 is a schematic view of a three-dimensional memory according to a sixth embodiment of the present application. In this embodiment, the first heat dissipation member 221 has a through hole 2211, and the through hole 2211 penetrates through a surface close to the second heat dissipation member 222 and a surface away from the second heat dissipation member 222.
In the present embodiment, the first heat sink member 221 may be provided with the through hole 2211, so that stress in the first heat sink member 221 may be reduced and the life of the first heat sink member 221 may be improved. Secondly, the opening of the through holes 2211 also increases the surface area of the first heat sink part 221, thereby improving the heat dissipation performance of the first heat sink part 221.
Referring to fig. 7 and 8 together, fig. 7 is a schematic view of a first heat sink portion according to a first embodiment of the present disclosure. Fig. 8 is a schematic view of a first heat sink member according to a second embodiment of the present application. In this embodiment, when the number of the through holes 2211 is one, the through holes 2211 are arranged in a serpentine shape, a zigzag shape, or a ring shape; alternatively, when the number of the through holes 2211 is plural, the through holes 2211 are arranged in an array. The number of the through holes 2211 in the present application may be one or more. When the number of the through holes 2211 is one, the through holes 2211 may have other shapes such as a serpentine shape, a zigzag shape, or a ring-shaped arrangement, so as to increase the area of the through holes 2211. Fig. 7 illustrates the serpentine arrangement of through-holes 2211. When the number of the through holes 2211 is plural, the plural through holes 2211 may be arranged in an array, so that the second heat sink member 222 is better connected to the first heat sink member 221.
Referring to fig. 9, fig. 9 is a schematic view of a first heat sink according to a third embodiment of the present disclosure. The through holes 2211 are polygonal in shape, and when the number of the through holes 2211 is large, the second heat sink member 222 is connected to the first heat sink member 221 at a side corresponding to the through hole 2211.
When the number of the through holes 2211 is plural, optionally, the shape of the through holes 2211 is a polygon, and the second heat sink member 222 is connected to the first heat sink member 221 at the side corresponding to the through holes 2211. It can also be understood that the region where the second heat sink member 222 connects the first heat sink member 221 is disposed near the edge of the through-hole 2211, not near the corner of the through-hole 2211. This can reduce the process difficulty of connecting the second heat sink member 222 to the first heat sink member 221.
Referring to fig. 10, fig. 10 is a schematic view of a first heat sink according to a fourth embodiment of the present disclosure. One second heat sink member 222 is connected between two adjacent through holes 2211.
The present application may connect one second heat sink member 222 between two adjacent through holes 2211. It can also be understood that only one second heat sink member 222 is connected between the edges of two adjacent through holes 2211, so that the second heat sink members 222 are prevented from being excessively concentrated and the second heat sink members 222 are uniformly distributed. Not only can the process difficulty of connecting the second heat sink piece 222 with the first heat sink piece 221 be further reduced, but also the heat distributed to the second heat sink piece 222 by the first heat sink piece 221 can be more even.
The application further provides an electronic device comprising a processor and the three-dimensional memory 1 as provided in the above embodiments of the application, wherein the processor is used for writing data into the three-dimensional memory 1 and reading data from the three-dimensional memory.
The application also provides an electronic device comprising the three-dimensional memory 1 provided by the application. Specifically, the electronic device may be an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, an electronic digital camera, or the like having a storage device. The electronic device of the present application typically further includes a processor, an input-output device, a display device, and the like. The three-dimensional memory 1 provided by the application is manufactured by processes such as packaging and the like to form a storage device such as a flash memory, and the storage device is used for storing files or data and is called by a processor. Specifically, the processor may write data into the storage device, i.e., the three-dimensional memory 1 provided in the present application, or may read data from the storage device, i.e., the three-dimensional memory 1 provided in the present application. The input and output device is used for inputting instructions or outputting signals, and the display device visualizes the signals to realize various functions of the electronic equipment. By adopting the three-dimensional memory 1 provided by the application, the electronic equipment not only greatly reduces the preparation time and the preparation cost of the electronic equipment, but also improves the stability and the storage performance of the electronic equipment.
In addition to the three-dimensional memory 1 provided above, the present application also provides a method for manufacturing the three-dimensional memory 1. The three-dimensional memory 1 and the method for manufacturing the three-dimensional memory 1 provided by the embodiment of the present application can achieve the technical effects of the present application, and both can be used together or independently, and the present application is not particularly limited thereto. For example, as one embodiment, the above-mentioned three-dimensional memory 1 may be manufactured using the manufacturing method of the three-dimensional memory 1 provided below.
Referring to fig. 11, fig. 11 is a process flow chart of a manufacturing method according to a first embodiment of the present disclosure. The present embodiment provides a method for manufacturing a three-dimensional memory 1, including S100 and S200. The details of S100 and S200 are as follows.
S100, providing a substrate 10, wherein the substrate 10 is provided with a first area 11 and a second area 12, and the first area 11 is connected with the second area 12.
S200, forming a dielectric layer 20 on one side of the substrate 10, wherein the dielectric layer 20 comprises a connector 21 and a heat sink 22, an orthographic projection of the connector 21 on the substrate 10 is located in the first region 11, an orthographic projection of the heat sink 22 on the substrate 10 is located in the second region 12, and the connector 21 is connected with the substrate 10; the heat dissipation member 22 includes a first heat dissipation member 221 and a second heat dissipation member 222, the first heat dissipation member 221 is connected to at least a portion of the second heat dissipation member 222, and the first heat dissipation member 221 is disposed closer to the substrate 10 than the second heat dissipation member 222.
In the preparation method provided by the application, the first heat sink part 221 and the second heat sink part 222 are formed, so that the first heat sink part 221 is arranged close to the substrate 10 compared with the second heat sink part 222, and the first heat sink part 221 is connected with at least part of the second heat sink part 222. In this way, the second heat sink member 222 absorbs a large amount of heat during bonding, and when the amount of heat absorbed by some of the second heat sink members 222 is too large, the heat can be conducted to the remaining second heat sink members 222 through the first heat sink member 221, so that the heat of the second heat sink members 222 is uniformly distributed. The preparation method provided by the application can effectively prevent the local heat from being too concentrated during bonding, and reduces the stability and the service life of the three-dimensional memory 1.
Referring to fig. 12-14 together, fig. 12 is a process flow diagram of a manufacturing method according to a second embodiment of the present disclosure. Fig. 13-14 are schematic diagrams of the three-dimensional memory corresponding to steps S110 and S120 in fig. 12, respectively. In the present embodiment, S100 "forming the dielectric layer 20 on one side of the substrate 10" includes S110 and S120. The details of S110 and S120 are as follows.
Referring to fig. 13, in S110, a first sub-dielectric layer 201 is formed on one side of the substrate 10, the first sub-dielectric layer 201 includes a first connection portion 211 and a first heat dissipation portion 221, an orthographic projection of the first connection portion 211 on the substrate 10 is located in the first region 11, an orthographic projection of the first heat dissipation portion 221 on the substrate 10 is located in the second region 12, the first connection portion 211 is connected to the substrate 10, and the first heat dissipation portion 221 and the substrate 10 are spaced apart from each other.
Referring to fig. 14, in S120, the second sub-dielectric layer 202 is formed on a side of the first sub-dielectric layer 201 away from the substrate 10, the second sub-dielectric layer 202 includes a second connection portion 212 and a second heat dissipation portion 222, an orthographic projection of the second connection portion 212 on the substrate 10 is located in the first region 11, an orthographic projection of the second heat dissipation portion 222 on the substrate 10 is located in the second region 12, the second connection portion 212 is connected to the first connection portion 211, and at least a portion of the second heat dissipation portion 222 is connected to the first heat dissipation portion 221.
The dielectric layer 20 may be formed by first forming the first sub-dielectric layer 201 and then forming the second sub-dielectric layer 202 on the first sub-dielectric layer 201. In forming the first sub-dielectric layer 201, the first connection portion 211 and the first heat sink portion 221 may be formed at the same time. Subsequently, when the second sub-dielectric layer 202 is formed, the second connection part 212 and the second heat sink part 222 may be simultaneously formed. The first connection portion 211 and the second connection portion 212 together form the connection member 21, the first heat sink portion 221 and the second heat sink portion 222 together form the heat sink 22, and the first sub-dielectric layer 201 and the second sub-dielectric layer 202 together form the insulating member 23. This may be more advantageous in preparing the first heat sink member 221 such that the first heat sink member 221 is spaced apart from the base 10, and may be more advantageous in preparing the first heat sink member 221 having a complicated structure.
Referring to fig. 15-18 together, fig. 15 is a process flow diagram of a manufacturing method according to a third embodiment of the present disclosure. Fig. 16-18 are schematic diagrams of the three-dimensional memory corresponding to steps S111, S112, and S113 in fig. 15, respectively. In this embodiment, S110 "forming the first sub-dielectric layer 201 on one side of the substrate 10" includes S111, S112, and S113. The details of S111, S112, and S113 are as follows.
Referring to fig. 16, S111, a first insulating layer 24 is deposited on one side of the substrate 10, and the first insulating layer 24 in the first region 11 is etched, so that a side of the first insulating layer 24 in the second region 12 facing away from the substrate 10 is higher than a side of the first insulating layer 24 in the first region 11 facing away from the substrate 10.
Referring to fig. 17 and S112, a first connection portion 211 and a first heat sink portion 221 are simultaneously formed in the first insulating layer 24, an orthographic projection of the first connection portion 211 on the substrate 10 is located in the first region 11, an orthographic projection of the first heat sink portion 221 on the substrate 10 is located in the second region 12, the first connection portion 211 is connected to the substrate 10, and the first heat sink portion 221 and the substrate 10 are spaced apart from each other.
Referring to fig. 18, in S113, the first insulating layer 24 in the second region 12 is planarized, so that a side of the first insulating layer 24 in the second region 12 facing away from the substrate 10 is flush with a side of the first insulating layer 24 in the first region 11 facing away from the substrate 10.
In order to form the first heat sink part 221 spaced apart from the base 10, a first insulating layer 24 having a relatively large thickness may be deposited on the base 10, and then the first insulating layer 24 located in the first region 11 may be etched, even though the thickness of the first insulating layer 24 corresponding to the first connection part 211 is reduced. Then, via holes are formed in the first insulating layer 24 by a photolithography process, and then the via holes are filled with a material, thereby forming the first connection portion 211 and the first heat sink portion 221 at the same time. Since the materials are deposited simultaneously, the thickness of the first connection portion 211 is the same as that of the first heat sink portion 221, but since the thickness of the first insulating layer 24 corresponding to the first region 11 is small and the thickness of the first insulating layer 24 corresponding to the second region 12 is large, the first connection portion 211 can be connected to the substrate 10, and the first heat sink portion 221 cannot be connected to the substrate 10, so that the first heat sink portion 221 is spaced apart from the substrate 10. Finally, a planarization process is performed to make a side of the first insulating layer 24 located in the second region 12 away from the substrate 10 flush with a side of the first insulating layer 24 located in the first region 11 away from the substrate 10, so as to form a second sub-dielectric layer 202 in the following.
Referring to fig. 19 to 20 together, fig. 19 is a process flow diagram of a manufacturing method according to a fourth embodiment of the present disclosure. Fig. 20 is a schematic diagram of the three-dimensional memory corresponding to step S114 in fig. 19. In this embodiment, after the step S113 "planarizing the first insulating layer 24 located in the second region 12", the method further includes a step S114. The details of S114 are as follows.
Referring to fig. 20, in S114, the first heat dissipation portion 221 is etched, so that a plurality of through holes 2211 arranged in an array are formed on the first heat dissipation portion 221.
After planarization, the first heat dissipation portion 221 may be etched, so that the first heat dissipation portion 221 is provided with a plurality of through holes 2211 arranged in an array. The specific arrangement of the through holes 2211 is described in detail above, and the detailed description of the application is omitted here.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (13)
1. A three-dimensional memory, the three-dimensional memory comprising:
a substrate having a first region and a second region, the first region connecting the second region;
the dielectric layer is arranged on one side of the base body and comprises a connecting piece and a heat dissipation piece, the orthographic projection of the connecting piece on the base body is positioned in the first area, the orthographic projection of the heat dissipation piece on the base body is positioned in the second area, and the connecting piece is connected with the base body; the heat dissipation member comprises a first heat dissipation member and a second heat dissipation member, the first heat dissipation member is connected with at least part of the second heat dissipation member, and the first heat dissipation member is arranged close to the substrate compared with the second heat dissipation member.
2. The three-dimensional memory according to claim 1, wherein the first heat sink member is spaced apart from the substrate.
3. The three-dimensional memory according to claim 1, wherein the dielectric layer further comprises an insulating member disposed between the connector and the heat sink, the connector being flush with a side of the heat sink facing away from the substrate and a side of the insulating member facing away from the substrate.
4. The three-dimensional memory according to claim 2, wherein the first heat sink member is provided with a through hole, and the through hole penetrates through a surface close to the second heat sink member and a surface away from the second heat sink member.
5. The three-dimensional memory according to claim 4, wherein when the number of the through holes is one, the through holes are arranged in a serpentine shape, a zigzag shape, or a ring shape; or when the number of the through holes is multiple, the through holes are arranged in an array.
6. The three-dimensional memory according to claim 5, wherein the through-holes have a polygonal shape, and when the number of the through-holes is plural, the second heat sink member is connected to the first heat sink member at an edge corresponding to the through-holes.
7. The three-dimensional memory according to claim 6, wherein one of the second heat sink members is connected between adjacent two of the through holes.
8. The three-dimensional memory according to claim 1, wherein the base body comprises a first substrate, a peripheral device layer, and a peripheral interconnect layer, the peripheral device layer being disposed on a side of the first substrate, the peripheral interconnect layer being disposed on a side of the peripheral device layer facing away from the first substrate, and the dielectric layer being disposed on a side of the peripheral interconnect layer facing away from the first substrate;
or, the base body comprises a second substrate, a storage array device layer and an array interconnection layer, the storage array device layer is arranged on one side of the second substrate, the array interconnection layer is arranged on one side, deviating from the second substrate, of the storage array device layer, and the dielectric layer is arranged on one side, deviating from the second substrate, of the array interconnection layer.
9. An electronic device comprising a three-dimensional memory according to any one of claims 1-8 and a processor for writing data to and reading data from the three-dimensional memory.
10. A method for preparing a three-dimensional memory, the method comprising:
providing a substrate having a first region and a second region, the first region connecting the second region;
forming a dielectric layer on one side of the substrate, wherein the dielectric layer comprises a connecting piece and a heat dissipation piece, the orthographic projection of the connecting piece on the substrate is positioned in the first area, the orthographic projection of the heat dissipation piece on the substrate is positioned in the second area, and the connecting piece is connected with the substrate; the heat dissipation member comprises a first heat dissipation member and a second heat dissipation member, the first heat dissipation member is connected with at least part of the second heat dissipation member, and the first heat dissipation member is arranged close to the substrate compared with the second heat dissipation member.
11. The method of claim 10, wherein the forming a dielectric layer on one side of the substrate comprises:
forming a first sub-dielectric layer on one side of the substrate, wherein the first sub-dielectric layer comprises a first connecting part and a first heat dissipation part, the orthographic projection of the first connecting part on the substrate is positioned in the first region, the orthographic projection of the first heat dissipation part on the substrate is positioned in the second region, the first connecting part is connected with the substrate, and the first heat dissipation part and the substrate are arranged at intervals;
the second sub-dielectric layer is formed on one side, away from the substrate, of the first sub-dielectric layer, the second sub-dielectric layer comprises a second connecting portion and a second heat dissipation portion, the orthographic projection of the second connecting portion on the substrate is located in the first area, the orthographic projection of the second heat dissipation portion on the substrate is located in the second area, the second connecting portion is connected with the first connecting portion, and at least part of the second heat dissipation portion is connected with the first heat dissipation portion.
12. The method of claim 11, wherein forming the first sub-dielectric layer on one side of the substrate comprises:
depositing a first insulating layer on one side of the base body, and etching the first insulating layer in the first area so that one side, facing away from the base body, of the first insulating layer in the second area is higher than one side, facing away from the base body, of the first insulating layer in the first area;
simultaneously forming a first connecting part and a first heat dissipation part in the first insulating layer, wherein the orthographic projection of the first connecting part on the substrate is positioned in the first area, the orthographic projection of the first heat dissipation part on the substrate is positioned in the second area, the first connecting part is connected with the substrate, and the first heat dissipation part and the substrate are arranged at intervals; and
and flattening the first insulating layer positioned in the second area so that the side, facing away from the base body, of the first insulating layer positioned in the second area is flush with the side, facing away from the base body, of the first insulating layer positioned in the first area.
13. The method according to claim 12, further comprising, after the planarizing the first insulating layer in the second region:
and etching the first heat dissipation part to enable the first heat dissipation part to be provided with a plurality of through holes which are arranged in an array mode.
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