CN111243649B - Shift register unit and display panel - Google Patents
Shift register unit and display panel Download PDFInfo
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- CN111243649B CN111243649B CN202010075638.7A CN202010075638A CN111243649B CN 111243649 B CN111243649 B CN 111243649B CN 202010075638 A CN202010075638 A CN 202010075638A CN 111243649 B CN111243649 B CN 111243649B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention relates to the technical field of display, and provides a shift register unit and a display panel. The shift register unit includes a shift register circuit and a control circuit. The shift register circuit is used for inputting a first shift signal to the first output end; the control circuit is connected with the first output end and used for generating a plurality of second shift signals which are sequentially shifted and output according to the first shift signals; wherein an effective period of each of the second shift signals is within an effective period of the first shift signal. The grid driving circuit formed by the shift register units can realize finer line direction scanning through the same number of shift register units, so that the brightness control precision of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register unit and a display panel.
Background
The pixel driving circuit usually adopts an internal compensation scheme to avoid abnormal display caused by the electrical difference of the driving transistors. The pixel driving circuit of the internal compensation method requires a plurality of driving signals (e.g., Reset, Gate, EM signals) to be matched with each other.
In the related art, it is generally required to provide the gate driving circuit EM GOA for outputting the enable signal EM. In order to simplify the structure of the gate driving circuit EM GOA, each stage of the shift register unit may be connected to a plurality of rows of pixel units, so that each stage of the shift register unit simultaneously inputs the enable signal EM to the plurality of rows of pixel units, thereby driving the plurality of rows of pixel units to emit light simultaneously.
In the gate driving circuit EM GOA, in order to connect a plurality of rows of pixel cells to each of the polar shift register cells, each of the shift register cells needs to output a sufficiently long active level. In the related art, the duration of the shift register unit outputting the active level is generally increased by increasing the period of the clock signal. However, when the period of the change of the clock signal increases, the minimum adjustment step size of the active level of the enable signal EM increases accordingly. Meanwhile, the enable signal EM is also used for controlling the brightness of the pixel unit, and accordingly, the brightness adjustment step length of the pixel unit is correspondingly increased, so that the precision of brightness adjustment of the pixel unit is affected, and finally, the phenomenon of brightness bar screen flashing occurs during brightness adjustment of the display panel.
It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a shift register unit and a display panel. The shift register unit can solve the technical problem of low brightness adjustment precision of the display panel in the related art.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.
According to one aspect of the present invention, a shift register unit is provided, which includes a shift register circuit, a control circuit. The shift register circuit is used for inputting a first shift signal to the first output end; the control circuit is connected with the first output end and used for generating a plurality of second shift signals which are sequentially shifted and output according to the first shift signals; wherein an effective period of each of the second shift signals is within an effective period of the first shift signal.
In an exemplary embodiment of the present invention, the shift register unit is applied to a display panel including a pixel driving circuit, and the second shift signal is used as an enable signal of the pixel driving circuit.
In one exemplary embodiment of the present invention, the control circuit includes a plurality of sub-control circuits; each sub-control circuit is connected with the first output terminal, the control signal terminal, the first power terminal, the second power terminal and the second output terminal, and is used for responding to the valid level signals of the control signal terminal and the first output terminal to transmit the signal of the first power terminal to the second output terminal, and is used for responding to the invalid level signal of the control signal terminal to transmit the signal of the second power terminal to the second output terminal.
In an exemplary embodiment of the present invention, the sub-control circuit is further configured to transmit the signal of the second power source terminal to the second output terminal in response to the disable level signal of the first output terminal.
In one exemplary embodiment of the present invention, the sub control circuit includes: a first P-type transistor, a second P-type transistor, and a third N-type transistor. The control end of the first P-type transistor is connected with the first output end, the first end of the first P-type transistor is connected with a first power supply end, the second end of the first P-type transistor is connected with a first node, and the first P-type transistor is used for responding to the effective level of the first output end to conduct the first power supply end and the first node; the first end of the second P-type transistor is connected with the first node, the second end of the second P-type transistor is connected with the second output end, the control end of the second P-type transistor is connected with the control signal end, and the second P-type transistor is used for responding to the effective level of the control signal end to conduct the first node and the second output end; the first end of the third N-type transistor is connected with the second output end, the second end of the third N-type transistor is connected with the second power supply end, and the control end of the third N-type transistor is connected with the control signal end and used for responding to the invalid level of the control signal end to conduct the second power supply end and the second output end.
In an exemplary embodiment of the present invention, the sub-control circuit includes a first P-type transistor, a second P-type transistor, a third N-type transistor, and a fourth N-type transistor. The control end of the first P-type transistor is connected with the first output end, the first end of the first P-type transistor is connected with a first power supply end, the second end of the first P-type transistor is connected with a first node, and the first P-type transistor is used for responding to the effective level of the first output end to conduct the first power supply end and the first node; the first end of the second P-type transistor is connected with the first node, the second end of the second P-type transistor is connected with the second output end, the control end of the second P-type transistor is connected with the control signal end, and the second P-type transistor is used for responding to the effective level of the control signal end to conduct the first node and the second output end; the first end of the third N-type transistor is connected with the second output end, the second end of the third N-type transistor is connected with the second power supply end, and the control end of the third N-type transistor is connected with the control signal end and used for responding to the invalid level of the control signal end to conduct the second power supply end and the second output end. The fourth N-type transistor has a first end connected to the second output end, a second end connected to a second power supply end, and a control end connected to the first output end, and is configured to respond to the invalid level signal of the first output end to turn on the second output end and the second power supply end.
In one exemplary embodiment of the present invention, the shift register circuit includes: the first input circuit, the first output circuit, the second input circuit, the second output circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit. The first input circuit is connected with an input end, a second node and a first clock signal end and is used for responding to a signal of the first clock signal end to transmit a signal of the input end to the second node; the first output circuit is connected with the second node, the first output end and a third power supply end and is used for responding to the signal of the second node and transmitting the signal of the third power supply end to the first output end; the second input circuit is connected with the first clock signal terminal, the third power supply terminal and the third node and is used for responding to the signal of the first clock signal terminal and transmitting the signal of the third power supply terminal to the third node; the second output circuit is connected with a third power supply end, a third node, a second clock signal end, a fourth power supply end, a first output end and a fourth node, and is used for responding to the signals of the third node and the second clock signal end to transmit the signal of the third power supply end to the fourth node and responding to the signal of the fourth node to transmit the signal of the fourth power supply end to the first output end; the first pull-down circuit is connected with the second node, the third node and the first clock signal end and is used for responding to the signal of the second node and transmitting the signal of the first clock signal end to the third node; the second pull-down circuit is connected with the second node, the third node, the second clock signal terminal and the fourth power supply terminal and is used for responding to the signals of the second clock signal terminal and the third node and transmitting the signal of the fourth power supply terminal to the second node; the third pull-down circuit is connected to the fourth power source terminal, the second node, and the fourth node, and is configured to transmit a signal of the fourth power source terminal to the fourth node in response to a signal of the second node.
In an exemplary embodiment of the present invention, the first input circuit includes a fifth transistor, a first terminal of the fifth transistor is connected to the input terminal, a second terminal of the fifth transistor is connected to the second node, and a control terminal of the fifth transistor is connected to the first clock signal terminal. The first output circuit comprises a sixth transistor and a first capacitor, wherein the first end of the sixth transistor is connected with the third power supply end, the second end of the sixth transistor is connected with the first output end, and the control end of the sixth transistor is connected with the second node; the first capacitor is connected between the second node and the second clock signal terminal. The second input circuit comprises a seventh transistor, a first end of the seventh transistor is connected with the third power supply end, a second end of the seventh transistor is connected with the third node, and a control end of the seventh transistor is connected with the first clock signal end. The second output circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. A first end of the eighth transistor is connected with a third power supply end, and a control end of the eighth transistor is connected with the third node; a first end of the ninth transistor is connected with a second end of the eighth transistor, a second end of the ninth transistor is connected with the fourth node, and a control end of the ninth transistor is connected with the second clock signal end; a tenth transistor having a first terminal connected to the fourth power terminal, a second terminal connected to the first output terminal, and a control terminal connected to the fourth node; the second capacitor is connected between the second clock signal end and the third node; a third capacitor is connected between the fourth node and the fourth supply terminal. The first pull-down circuit comprises an eleventh transistor, wherein a first end of the eleventh transistor is connected with the third node, a second end of the eleventh transistor is connected with the first clock signal end, and a control end of the eleventh transistor is connected with the second node. The second pull-down circuit includes: a twelfth transistor and a thirteenth transistor. A first end of the twelfth transistor is connected with the fourth power supply end, and a control end of the twelfth transistor is connected with the third node; and the first end of the thirteenth transistor is connected with the second end of the twelfth transistor, the second end of the thirteenth transistor is connected with the second node, and the control end of the thirteenth transistor is connected with the second clock signal end. The third pull-down circuit comprises a fourteenth transistor, wherein a first end of the fourteenth transistor is connected with a fourth node, a second end of the fourteenth transistor is connected with a fourth power supply end, and a control end of the fourteenth transistor is connected with the second node.
In an exemplary embodiment of the present invention, the control circuit further includes a plurality of inverters, and the inverters are disposed in one-to-one correspondence with the sub-control circuits and connected to the second output terminals of the plurality of sub-control circuits.
According to an aspect of the present invention, there is provided a display panel including a gate driving circuit including a plurality of cascaded shift register units as described above.
The present disclosure provides a shift register unit and a display panel, wherein the shift register unit includes a shift register circuit and a control circuit. The shift register circuit is used for inputting a first shift signal to the first output end; the control circuit is connected with the first output end and used for generating a plurality of second shift signals which are sequentially shifted and output according to the first shift signals; wherein an effective period of each of the second shift signals is within an effective period of the first shift signal. The gate driving circuit can output a first shift signal through a small number of shift register units, and simultaneously, a control circuit generates a plurality of second shift signals which are sequentially shifted and output according to the first shift signal, so that an enable signal can be input to a pixel row through the second shift signals. On one hand, the grid driving circuit formed by the shift register unit has a simple structure, so that the frame width of the display panel is smaller; on the other hand, the pixel rows of the display panel can be scanned by a larger number of second shift signal rows, so that the number of rows of pixel units which are scanned simultaneously is reduced, and the brightness control precision of the display panel is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of a pixel driving circuit in the related art;
FIG. 2 is a timing diagram of a portion of nodes in an exemplary embodiment of the pixel driving circuit of FIG. 1;
FIG. 3 is a timing diagram of a portion of nodes in another exemplary embodiment of the pixel driving circuit of FIG. 1;
FIG. 4 is a diagram illustrating a shift register unit according to the related art;
FIG. 5 is a timing diagram of a portion of the nodes of an exemplary embodiment of the shift register cell of FIG. 4;
FIG. 6 is a schematic diagram of an exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 7 is a timing diagram of a second shift signal in an exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 8 is a schematic diagram of another exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 9 is a schematic diagram of another exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 10 is a timing diagram of a portion of the nodes of an exemplary embodiment of the shift register cell of FIG. 9;
FIG. 11 is a schematic diagram of another exemplary embodiment of a shift register cell according to the present disclosure;
fig. 12 is a schematic structural diagram of another exemplary embodiment of a shift register unit according to the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
As shown in fig. 1 and 2, fig. 1 is a schematic structural diagram of a pixel driving circuit in the related art. Fig. 2 is a timing diagram of a portion of nodes in an exemplary embodiment of the pixel driving circuit of fig. 1. The pixel driving circuit includes first to seventh transistors M1-M7, a capacitor C, and a light emitting unit OLED, wherein the first to seventh transistors M1-M7 are P-type transistors. The pixel driving circuit driving method comprises three stages: a reset phase, a compensation phase and a light emitting phase. As shown in fig. 2, in the reset phase T1: the enable signal terminal EM is a high level signal, the Reset signal terminal Reset is a low level signal, the Gate driving signal terminal Gate is a high level signal, the first transistor M1 and the seventh transistor M7 are turned on, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, and the reference voltage terminal Vref inputs a Reset signal to the first node N1 and the second node N2. In the compensation phase T2: the enable signal end EM is a high-level signal, the Reset signal end Reset is a high-level signal, the Gate driving signal end Gate is a low-level signal, the first transistor M1, the seventh transistor M7, the fifth transistor M5 and the sixth transistor M6 are turned off, the second transistor M2 and the fourth transistor M4 are turned on, and the data signal end Vdata inputs a compensation voltage V to the first node, wherein the compensation voltage V is Vdata + Vth, Vdata is a signal voltage of the data signal end Vdata, and Vth is a threshold voltage of the third transistor M3. In the light emitting stage: the enable signal terminal EM is a low level signal, the Reset signal terminal Reset is a high level signal, the Gate driving signal terminal Gate is a high level signal, the first transistor M1, the seventh transistor M7, the second transistor M2 and the fourth transistor M4 are turned off, the fifth transistor M5 and the sixth transistor M6 are turned on, and the light emitting unit OLED emits light under the action of a voltage between the first power terminal VDD and the second power terminal VSS. In addition, the signal of the enable signal terminal EM can also adjust the light emission luminance of the pixel unit. For example, as shown in fig. 3, a timing diagram of a portion of nodes in another exemplary embodiment of the pixel driving circuit of fig. 1 is shown. The enable signal EM may be continuously at a high level for a period of T4 so as to make the light emitting unit OLED in an off state, and the light emitting luminance of the row of pixel cells in one frame may be controlled by controlling the duration of T4, wherein the longer the duration of the high level of the enable signal EM is, the lower the light emitting luminance of the light emitting unit OLED is. The multiple rows of pixel units applying the pixel driving circuit may also share the same enable signal terminal, for example, as the timing of the enable signal terminal EM shown in fig. 3, the enable signal output by the enable signal terminal drives the pixel units of the current row in the stages of T1 and T2 in cooperation with the signals of the Reset signal terminal Reset and the Gate driving signal terminal Gate shown in fig. 3, and the enable signal can complete the Reset phase and the compensation phase in cooperation with the Reset signal and the Gate driving signal of the next row of pixel units in the periods of T2 and T3.
As shown in fig. 4 and 5, fig. 4 is a schematic structural diagram of a shift register unit in the related art, and fig. 5 is a timing diagram of a portion of nodes in an exemplary embodiment of the shift register unit in fig. 4. The shift register unit includes fifth to fourteenth transistors T5 to T14, first to third capacitors C1 to C3, and an inverter PI. As shown in fig. 5, the driving method of the shift register unit includes 5 stages, wherein the fifth transistor T5 to the fourteenth transistor T14 may be P-type transistors, the first power signal terminal VGL is continuously at a low level, and the second power signal terminal VGH is continuously at a high level. In the first stage T1, the first clock signal terminal CLK1 is at a low level, the second clock signal terminal CLK2 is at a high level, the Input terminal Input is at a low level, the fifth transistor T5, the sixth transistor T6 and the fourteenth transistor T14 are turned on, the second power supply terminal VGH precharges a high-level signal to the third capacitor C3, and the output terminal Eout is at a high level; in the second stage T2, the first clock signal terminal CLK1 is at a high level, the second clock signal terminal CLK2 is at a high level, the Input terminal Input is at a low level, the eleventh transistor T11 is turned on, the first clock signal terminal charges the capacitor C2 with a high level signal to turn off the twelfth transistor T12, and the output terminal Eout outputs a high level; in the third stage T3, the first clock signal terminal CLK1 is at a high level, the front portion of the second clock signal terminal CLK2 is at a low level, the Input terminal Input is at a low level, the eighth transistor T8 is turned off under the action of the high level of the capacitor C2, and the output terminal Eout outputs a high level; in the fourth stage T4, the first clock signal terminal CLK1 is at a low level, the second clock signal terminal CLK2 is at a high level, the Input terminal Input is at a low level, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 are turned on, the first power terminal VGL and the first clock signal terminal precharge the second capacitor C2 at a low level, and the output terminal Eout outputs a high level; in the fifth stage T5, the first clock signal terminal CLK1 is at a low level for a part of the period, the second clock signal terminal CLK2 is at a high level, the Input terminal Input is at a high level, the fifth transistor T5 is turned on, the sixth transistor T6 and the eleventh transistor T11 are turned off, and the output terminal Eout maintains at a high level in the previous period. After the fifth stage T5, when the second clock signal terminal CLK2 goes low, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned on, and the output terminal Eout outputs low. As shown in fig. 5, in order to enable the output terminal Eout to simultaneously connect a plurality of rows of pixel cells, the output terminal Eout needs to output a high level for a long period of time. The length of time for which the output terminal Eout outputs the high level can be increased by increasing the periods of the first clock signal terminal and the second clock signal terminal in the related art in general. For example, as shown in fig. 5, the periods of the first and second clock signal terminals may be 4H, where 1H is a duration in which the gate driving signal terminal Gata outputs a low level in fig. 2. At this time, the output terminal Eout outputs the high level for a period of 6H. The output end Eout can be connected with two rows of pixel units, wherein the high level of the first 3H duration in the output end Eout can be used for completing the reset stage and the compensation stage of the two rows of pixel units, and the subsequent high level duration can affect the brightness of the pixel units, wherein the longer the high level duration of the output end Eout is, the shorter the light emitting duration of the pixel units is, and the lower the brightness of the pixel units is. The shift register unit can control the duration of the high level of the output end Eout through the signal of the Input end Input, so as to control the brightness of the pixel unit, for example, when the duration of the low level of the Input end Input is increased by 4H, the duration of the high level of the output end Eout is increased by 4H, and the lighting duration of the pixel unit is decreased by 4H, so as to decrease the lighting brightness of the pixel unit. However, since the period of the change of the CLK2 at the first clock signal terminal CLK1 and the second clock signal terminal is 4H, the step change amount of the active level (low level) of the Input signal at the Input terminal needs to match the multiple set to 4H, and the output terminal Eout can output the shift signal with the same step change amount of the active level (high level). Therefore, when the brightness of the pixel unit is adjusted through the Input terminal Input, the minimum step size of the brightness adjustment is 4H, and the minimum step size of the brightness adjustment is long, so that the brightness adjustment precision of the pixel unit is affected.
Based on this, the present exemplary embodiment provides a shift register unit, as shown in fig. 6, which is a schematic structural diagram of an exemplary embodiment of the shift register unit of the present disclosure. The shift register unit comprises a shift register circuit 1 and a control circuit 2. The shift register circuit 1 is configured to input a first shift signal to a first output terminal OUT 1; the control circuit 2 is connected to the first output terminal OUT1, and is configured to generate a plurality of second shift signals sequentially shifted and output according to the first shift signal; wherein an effective period of each of the second shift signals is within an effective period of the first shift signal.
Fig. 7 is a timing diagram of the second shift signal in an exemplary embodiment of the shift register unit according to the present disclosure. Wherein the active periods of the first and second shift signals may be high level signals. The timing of the first shift signal Sg1 may be the same as the timing of the output end Eout in fig. 5, and the high level durations thereof are all 6H. The plurality of second shift signals may include second shift signals Sg21, Sg22, Sg23, Sg24, the second shift signals Sg21, Sg22, Sg23, Sg24 are sequentially shift-output, the high level duration of the second shift signals Sg21, Sg22, Sg23, Sg24 may be 3H, and adjacent second shift signals are shift-output with an interval of 1H. The second shift signal may provide an enable signal to a row of pixel cells, respectively. For example, the second shift signal Sg21 may provide enable signals for a reset phase and a compensation phase to a row of pixel cells in the first and second periods T1 and T2, and the second shift signal Sg21 may affect the light emission luminance of the pixel cells through the high-level duration of the third period T3. Obviously, the second shift signal can control the high level duration affecting the light emission of the pixel unit to 1H. On one hand, the grid driving circuit formed by the shifting register unit can realize the driving of a plurality of rows of pixel units through a smaller number of shifting register units. On the other hand, the grid driving circuit formed by the shift register unit can improve the brightness adjustment precision of the display panel on the premise of not changing the number of the shift register units.
In this exemplary embodiment, as shown in fig. 8, which is a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure, the shift register circuit may include: the first input circuit 11, the first output circuit 12, the second input circuit 13, the second output circuit 14, the first pull-down circuit 15, the second pull-down circuit 16, and the third pull-down circuit 17. The first Input circuit 11 is connected to an Input terminal Input, a second node N2, and a first clock signal terminal CLK1, and is configured to transmit a signal of the Input terminal Input to a second node N2 in response to a signal of the first clock signal terminal CLK 1; the first output circuit 12 is connected to the second node N2, the first output terminal OUT1, and the third power supply terminal VGL2 for transmitting the signal of the third power supply terminal VGL2 to the first output terminal OUT1 in response to the signal of the second node N2; the second input circuit 13 is connected to the first clock signal terminal CLK1, the third power source terminal VGL2, and the third node N3, and is configured to transmit a signal of the third power source terminal VGL2 to the third node N3 in response to a signal of the first clock signal terminal CLK 1; the second output circuit 14 is connected to a third power source terminal VGL2, a third node N3, a second clock signal terminal CLK2, a fourth power source terminal VGH2, a first output terminal OUT1, a fourth node N4, for transmitting a signal of the third power source terminal VGL2 to the fourth node N4 in response to signals of the third node N3 and the second clock signal terminal CLK2, and for transmitting a signal of the fourth power source terminal VGH2 to the first output terminal OUT1 in response to a signal of the fourth node N4; the first pull-down circuit 15 is connected to the second node N2, the third node N3, and the first clock signal terminal CLK1, and configured to transmit a signal of the first clock signal terminal CLK1 to the third node N3 in response to a signal of the second node N2; the second pull-down circuit 16 is connected to the second node N2, the third node N3, the second clock signal terminal CLK2 and the fourth power supply terminal VGH2, and is configured to transmit a signal of the fourth power supply terminal VGH2 to the second node N2 in response to signals of the second clock signal terminal CLK2 and the third node N3; the third pull-down circuit 17 is connected to the fourth power supply terminal VGH2, the second node N2 and the fourth node N4, and is configured to transmit a signal of the fourth power supply terminal VGH2 to the fourth node N4 in response to a signal of the second node N2.
In the exemplary embodiment, as shown in fig. 8, the first Input circuit 11 may include a fifth transistor T5, a first terminal of which is connected to the Input terminal, a second terminal of which is connected to the second node N2, and a control terminal of which is connected to the first clock signal terminal CLK 1. The first output circuit 12 may include a sixth transistor T6 and a first capacitor C1, wherein a first terminal of the sixth transistor T6 is connected to the third power source terminal VGL2, a second terminal is connected to the first output terminal OUT1, and a control terminal is connected to the second node N2; the first capacitor C1 is connected between the second node N2 and the second clock signal terminal CLK 2. The second input circuit 13 may include a seventh transistor T7, a first terminal of the seventh transistor T7 is connected to the third power source terminal VGL2, a second terminal thereof is connected to the third node N3, and a control terminal thereof is connected to the first clock signal terminal CLK 1. The second output circuit 14 may include: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3. A first terminal of the eighth transistor T8 is connected to the third power source terminal VGL2, and a control terminal thereof is connected to the third node N3; a first terminal of the ninth transistor T9 is connected to the second terminal of the eighth transistor T8, a second terminal thereof is connected to the fourth node N4, and a control terminal thereof is connected to the second clock signal terminal CLK 2; a tenth transistor T10 having a first terminal connected to the fourth power source terminal VGH2, a second terminal connected to the first output terminal OUT1, and a control terminal connected to the fourth node N4; a second capacitor is connected between the second clock signal terminal CLK2 and the third node N3; the third capacitor is connected between the fourth node N4 and the fourth power terminal VGH 2. The first pull-down circuit 15 may include an eleventh transistor T11, a first terminal of the eleventh transistor T11 is connected to the third node N3, a second terminal of the eleventh transistor T11 is connected to the first clock signal terminal CLK1, and a control terminal of the eleventh transistor T11 is connected to the second node N2. The second pull-down circuit 16 may include: a twelfth transistor T12, a thirteenth transistor T13. A first terminal of the twelfth transistor T12 is connected to the fourth power source terminal VGH2, and a control terminal thereof is connected to the third node N3; the thirteenth transistor T13 has a first terminal connected to the second terminal of the twelfth transistor T12, a second terminal connected to the second node N2, and a control terminal connected to the second clock signal terminal CLK 2. The third pull-down circuit 17 may include a fourteenth transistor T14, a first terminal of the fourteenth transistor T14 is connected to the fourth node N4, a second terminal thereof is connected to the fourth power source terminal VGH2, and a control terminal thereof is connected to the second node N2.
The fifth to fourteenth transistors may be P-type transistors, the signal of the third power source terminal VGL2 is at a low level, and the level of the fourth power source terminal VGH2 is at a high level. The driving method of the shift register circuit may be the same as the driving method of the shift register unit in fig. 4, in which the signal of the first output terminal OUT1 of the shift register circuit shown in fig. 8 and the signal timing of the output terminal Nout of the shift register unit shown in fig. 4 are the same. It should be understood that in other exemplary embodiments, the shift register circuit may have other driving methods, for example, the period of the change of the first clock signal terminal CLk1 and the second clock signal terminal CLk2 may be 5H, 6H, etc. The shift register circuit may have other structures, which are within the scope of the present disclosure.
In the present exemplary embodiment, as shown in fig. 9, a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure is shown. The control circuit 2 may include 4 sub-control circuits 21, 22, 23, 24; the sub-control circuit 21 is connected to the first output terminal OUT1, the control signal terminal CN1, the first power supply terminal VGL1, the second power supply terminal VGH1, and the second output terminal OUT21, for transmitting the signal of the first power supply terminal VGL1 to the second output terminal OUT21 in response to the active level signals of the control signal terminal CN1 and the first output terminal OUT1, and for transmitting the signal of the second power supply terminal VGH1 to the second output terminal OUT21 in response to the inactive level signal of the control signal terminal. The sub-control circuit 22 is connected to the first output terminal OUT1, the control signal terminal CN2, the first power supply terminal VGL1, the second power supply terminal VGH1, and the second output terminal OUT22, and is configured to transmit a signal of the first power supply terminal VGL1 to the second output terminal OUT22 in response to an active level signal of the control signal terminal and the first output terminal OUT1, and to transmit a signal of the second power supply terminal VGH1 to the second output terminal OUT22 in response to an inactive level signal of the control signal terminal. The sub-control circuit 23 is connected to the first output terminal OUT1, the control signal terminal CN3, the first power supply terminal VGL1, the second power supply terminal VGH1, and the second output terminal OUT23, and is configured to transmit a signal of the first power supply terminal VGL1 to the second output terminal OUT23 in response to an active level signal of the control signal terminal and the first output terminal OUT1, and to transmit a signal of the second power supply terminal VGH1 to the second output terminal OUT23 in response to an inactive level signal of the control signal terminal. The sub-control circuit 24 is connected to the first output terminal OUT1, the control signal terminal CN4, the first power supply terminal VGL1, the second power supply terminal VGH1, and the second output terminal OUT24, and is configured to transmit a signal of the first power supply terminal VGL1 to the second output terminal OUT24 in response to an active level signal of the control signal terminal and the first output terminal OUT1, and to transmit a signal of the second power supply terminal VGH1 to the second output terminal OUT24 in response to an inactive level signal of the control signal terminal.
In the present exemplary embodiment, as shown in fig. 9, the sub-control circuit 21 may include: a first P-type transistor T11, a second P-type transistor T21, and a third N-type transistor T31. A first P-type transistor having a control terminal connected to the first output terminal OUT1, a first terminal connected to a first power supply terminal VGL1, and a second terminal connected to a first node N11, for turning on the first power supply terminal VGL1 and a first node N11 in response to an active level of the first output terminal OUT 1; a second P-type transistor having a first terminal connected to the first node N11, a second terminal connected to the second output terminal OUT21, and a control terminal connected to the control signal terminal CN1, and being responsive to an active level of the control signal terminal CN1 to turn on the first node N11 and the second output terminal OUT 21; the third N-type transistor T31 has a first terminal connected to the second output terminal OUT21, a second terminal connected to the second power terminal VGH1, and a control terminal connected to the control signal terminal CN1, and is configured to respond to an inactive level of the control signal terminal CN1 to turn on the second power terminal VGH1 and the second output terminal OUT 21. The sub-control circuit 22 may include: a first P-type transistor T12, a second P-type transistor T22, and a third N-type transistor T32. A first P-type transistor having a control terminal connected to the first output terminal OUT1, a first terminal connected to a first power supply terminal VGL1, and a second terminal connected to a first node N12, for turning on the first power supply terminal VGL1 and a first node N12 in response to an active level of the first output terminal OUT 1; a second P-type transistor having a first terminal connected to the first node N12, a second terminal connected to the second output terminal OUT22, and a control terminal connected to the control signal terminal CN2, and being responsive to an active level of the control signal terminal CN2 to turn on the first node N12 and the second output terminal OUT 22; the third N-type transistor T32 has a first terminal connected to the second output terminal OUT22, a second terminal connected to the second power terminal VGH1, and a control terminal connected to the control signal terminal CN2, and is configured to respond to an inactive level of the control signal terminal CN2 to turn on the second power terminal VGH1 and the second output terminal OUT 22. The sub control circuit 23 may include: a first P-type transistor T13, a second P-type transistor T23, and a third N-type transistor T33. A first P-type transistor having a control terminal connected to the first output terminal OUT1, a first terminal connected to a first power supply terminal VGL1, and a second terminal connected to a first node N13, for turning on the first power supply terminal VGL1 and a first node N13 in response to an active level of the first output terminal OUT 1; a second P-type transistor having a first terminal connected to the first node N13, a second terminal connected to the second output terminal OUT23, and a control terminal connected to the control signal terminal CN3, and being responsive to an active level of the control signal terminal CN3 to turn on the first node N13 and the second output terminal OUT 23; the third N-type transistor T33 has a first terminal connected to the second output terminal OUT23, a second terminal connected to the second power terminal VGH1, and a control terminal connected to the control signal terminal CN3, and is configured to respond to an inactive level of the control signal terminal CN3 to turn on the second power terminal VGH1 and the second output terminal OUT 23. The sub-control circuit 24 may include: a first P-type transistor T14, a second P-type transistor T24, and a third N-type transistor T34. A first P-type transistor having a control terminal connected to the first output terminal OUT1, a first terminal connected to a first power supply terminal VGL1, and a second terminal connected to a first node N14, for turning on the first power supply terminal VGL1 and a first node N14 in response to an active level of the first output terminal OUT 1; a second P-type transistor having a first terminal connected to the first node N14, a second terminal connected to the second output terminal OUT24, and a control terminal connected to the control signal terminal CN4, and being responsive to an active level of the control signal terminal CN4 to turn on the first node N14 and the second output terminal OUT 24; the third N-type transistor T34 has a first terminal connected to the second output terminal OUT24, a second terminal connected to the second power terminal VGH1, and a control terminal connected to the control signal terminal CN4, and is configured to respond to an inactive level of the control signal terminal CN4 to turn on the second power terminal VGH1 and the second output terminal OUT 24. The first power supply terminal signal may be a low level signal, and the second power supply terminal signal may be a high level signal. The active levels of the first output terminal OUT1 and the control signal terminal may be low, and the inactive levels may be high.
Fig. 10 is a timing diagram of a portion of the nodes in an exemplary embodiment of the shift register cell of fig. 9. Taking the sub-control circuit 21 as an example, in a stage where the first output terminal OUT1 outputs a low level, when the control signal terminal CN1 is at a low level, the second P-type transistor T21 is turned on, the third N-type transistor T31 is turned off, the first power terminal VGL1 outputs a low level signal to the second output terminal OUT21, when the control signal terminal CN1 is at a high level, the second P-type transistor T21 is turned off, the third N-type transistor T31 is turned on, and the second power terminal VGH1 outputs a high level signal to the second output terminal OUT 21. So that the second output terminal OUT21 can be controlled to output a preset signal by the signal of the control signal terminal CN 1. The signals of the second output terminals OUT21, OUT22, OUT23, OUT24 may be the same as the inverted signals of the signals Sg21, Sg22, Sg23, Sg24 in fig. 7. Fig. 11 is a schematic structural diagram of another exemplary embodiment of a shift register unit according to the present disclosure. The control circuit may further comprise 4 inverters PI1, PI2, PI3 and PI4, each of which is connected to the second output terminal of the 4 sub-control circuits to invert the signal at the second output terminal, thereby obtaining signals Sg21, Sg22, Sg23 and Sg24 in fig. 7.
It should be appreciated that in other exemplary embodiments, the control circuit may also generate other numbers of second shift signals from the first shift signal. Accordingly, the control circuit may also include other numbers of sub-control circuits. The number of the control circuits is the same as that of the second shift signals. In addition, the second shift signal may also provide an enable signal to the plurality of rows of pixel cells.
In the present exemplary embodiment, the sub-control circuit may be further configured to transmit the signal of the second power source terminal VGH1 to the second output terminal OUT2 in response to the inactive level signal of the first output terminal OUT 1. Fig. 12 is a schematic structural diagram of another exemplary embodiment of a shift register unit according to the present disclosure. The sub-control circuit 21 may further include a fourth N-type transistor T41. The fourth N-type transistor T41 has a first terminal connected to the second output terminal OUT21, a second terminal connected to the second power source terminal VGH1, and a control terminal connected to the first output terminal OUT1, and is configured to respond to an inactive level signal of the first output terminal OUT1 to turn on the second output terminal OUT21 and the second power source terminal VGH 1. The sub-control circuit 22 may further include a fourth N-type transistor T42. The fourth N-type transistor T42 has a first terminal connected to the second output terminal OUT22, a second terminal connected to the second power source terminal VGH1, and a control terminal connected to the first output terminal OUT1, and is configured to respond to an inactive level signal of the first output terminal OUT1 to turn on the second output terminal OUT22 and the second power source terminal VGH 1. The sub-control circuit 23 may further include a fourth N-type transistor T43. The fourth N-type transistor T43 has a first terminal connected to the second output terminal OUT23, a second terminal connected to the second power source terminal VGH1, and a control terminal connected to the first output terminal OUT1, and is configured to respond to an inactive level signal of the first output terminal OUT1 to turn on the second output terminal OUT23 and the second power source terminal VGH 1. The sub-control circuit 24 may also have a fourth N-type transistor T44. The fourth N-type transistor T44 has a first terminal connected to the second output terminal OUT24, a second terminal connected to the second power source terminal VGH1, and a control terminal connected to the first output terminal OUT1, and is configured to respond to an inactive level signal of the first output terminal OUT1 to turn on the second output terminal OUT24 and the second power source terminal VGH 1. The fourth N-type transistor is further configured to ensure that the second shift signal is at a high level when the first shift signal is at a high level.
The present exemplary embodiment also provides a display panel including a gate driving circuit including a plurality of cascaded shift register units as described above. The display panel can be applied to display devices such as televisions, mobile phones and tablet computers.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (9)
1. A shift register cell, comprising:
a shift register circuit for inputting a first shift signal to a first output terminal;
the control circuit is connected with the first output end and is used for generating a plurality of second shift signals which are sequentially shifted and output according to the first shift signals;
wherein an effective period of each of the second shift signals is within an effective period of the first shift signal;
the control circuit comprises a plurality of sub-control circuits;
each sub-control circuit is connected with the first output terminal, the control signal terminal, the first power terminal, the second power terminal and the second output terminal, and is used for responding to the valid level signals of the control signal terminal and the first output terminal to transmit the signal of the first power terminal to the second output terminal, and is used for responding to the invalid level signal of the control signal terminal to transmit the signal of the second power terminal to the second output terminal.
2. The shift register unit according to claim 1, wherein the shift register unit is applied to a display panel including a pixel driving circuit, and the second shift signal is used as an enable signal of the pixel driving circuit.
3. The shift register cell of claim 1, wherein the sub-control circuit is further configured to transmit the signal of the second power supply terminal to the second output terminal in response to the inactive level signal of the first output terminal.
4. The shift register cell of claim 1, wherein the sub-control circuit comprises:
a first P-type transistor having a control terminal connected to the first output terminal, a first terminal connected to a first power terminal, and a second terminal connected to a first node, for responding to an active level of the first output terminal to turn on the first power terminal and the first node;
a second P-type transistor, having a first end connected to the first node, a second end and a second output end, and a control end connected to the control signal end, for responding to the active level of the control signal end to conduct the first node and the second output end;
and the third N-type transistor is connected with the second output end at the first end, the second end and the control end at the second power end, and is used for responding to the invalid level of the control signal end to conduct the second power end and the second output end.
5. The shift register cell of claim 3, wherein the sub-control circuit comprises:
a first P-type transistor having a control terminal connected to the first output terminal, a first terminal connected to a first power terminal, and a second terminal connected to a first node, for responding to an active level of the first output terminal to turn on the first power terminal and the first node;
a second P-type transistor, having a first end connected to the first node, a second end and a second output end, and a control end connected to the control signal end, for responding to the active level of the control signal end to conduct the first node and the second output end;
a third N-type transistor, having a first end connected to the second output end, a second end connected to the second power end, and a control end connected to the control signal end, for responding to the invalid level of the control signal end to turn on the second power end and the second output end;
and the fourth N-type transistor is connected with the second output end at a first end, connected with a second power supply end at a second end and connected with the first output end at a control end, and is used for responding to the invalid level signal of the first output end to conduct the second output end and the second power supply end.
6. The shift register cell of claim 1, wherein the shift register circuit comprises:
the first input circuit is connected with an input end, a second node and a first clock signal end and is used for responding to a signal of the first clock signal end to transmit a signal of the input end to the second node;
a first output circuit connected to said second node, to a first output terminal, to a third power supply terminal, for transmitting a signal of said third power supply terminal to said first output terminal in response to a signal of said second node;
the second input circuit is connected with the first clock signal terminal, a third power supply terminal and a third node and is used for responding to the signal of the first clock signal terminal and transmitting the signal of the third power supply terminal to the third node;
a second output circuit, connected to a third power source terminal, a third node, a second clock signal terminal, a fourth power source terminal, a first output terminal, and a fourth node, for transmitting a signal of the third power source terminal to the fourth node in response to a signal of the third node and the second clock signal terminal, and for transmitting a signal of the fourth power source terminal to the first output terminal in response to a signal of the fourth node;
a first pull-down circuit connected to the second node, a third node, and a first clock signal terminal, for transmitting a signal of the first clock signal terminal to the third node in response to a signal of the second node;
the second pull-down circuit is connected with the second node, the third node, the second clock signal end and the fourth power supply end and is used for responding to the signals of the second clock signal end and the third node and transmitting the signal of the fourth power supply end to the second node;
and the third pull-down circuit is connected with the fourth power supply end, the second node and the fourth node and is used for responding to the signal of the second node and transmitting the signal of the fourth power supply end to the fourth node.
7. The shift register cell of claim 6,
the first input circuit includes:
a fifth transistor, having a first terminal connected to the input terminal, a second terminal connected to the second node, and a control terminal connected to the first clock signal terminal;
the first output circuit includes:
a sixth transistor, having a first terminal connected to the third power terminal, a second terminal connected to the first output terminal, and a control terminal connected to the second node;
the first capacitor is connected between the second node and the second clock signal end;
the second input circuit includes:
a seventh transistor, having a first end connected to the third power terminal, a second end connected to the third node, and a control end connected to the first clock signal terminal;
the second output circuit includes:
the first end of the eighth transistor is connected with a third power supply end, and the control end of the eighth transistor is connected with the third node;
a ninth transistor, a first end of which is connected to the second end of the eighth transistor, a second end of which is connected to the fourth node, and a control end of which is connected to the second clock signal end;
a tenth transistor having a first terminal connected to the fourth power terminal, a second terminal connected to the first output terminal, and a control terminal connected to the fourth node;
the second capacitor is connected between the second clock signal end and the third node;
a third capacitor connected between the fourth node and the fourth power supply terminal;
the first pull-down circuit includes:
an eleventh transistor, having a first terminal connected to the third node, a second terminal connected to the first clock signal terminal, and a control terminal connected to the second node;
the second pull-down circuit includes:
a twelfth transistor, having a first terminal connected to the fourth power terminal and a control terminal connected to the third node;
a thirteenth transistor, having a first end connected to the second end of the twelfth transistor, a second end connected to the second node, and a control end connected to the second clock signal end;
the third pull-down circuit includes:
and the fourteenth transistor is connected with the fourth node at the first end, the fourth power supply end at the second end and the second node at the control end.
8. The shift register cell of claim 1, wherein the control circuit further comprises:
and the phase inverters are arranged in one-to-one correspondence with the sub-control circuits and are connected to the second output ends of the sub-control circuits.
9. A display panel comprising a gate driver circuit including a plurality of cascaded shift register cells according to any one of claims 1 to 8.
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| WO2023225946A1 (en) * | 2022-05-26 | 2023-11-30 | 京东方科技集团股份有限公司 | Shift register unit, driving control circuit, display apparatus and driving method |
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