CN111243644B - Counting method of enhanced flash and enhanced flash - Google Patents
Counting method of enhanced flash and enhanced flash Download PDFInfo
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- CN111243644B CN111243644B CN201911389103.0A CN201911389103A CN111243644B CN 111243644 B CN111243644 B CN 111243644B CN 201911389103 A CN201911389103 A CN 201911389103A CN 111243644 B CN111243644 B CN 111243644B
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
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Abstract
The invention discloses a counting method of an enhanced flash and the enhanced flash, and the method comprises the following steps: when the rising edge of the clock signal and the added signal are simultaneously effective, the counting unit increases 1 on the basis of the initial value to obtain the current counting value, and the counting value is input into the remapping unit; the remapping unit carries out high-low bit conversion on the counting value to obtain a remapped counting value; the non-volatile memory control unit writes the remapped count value to non-volatile memory. The invention realizes the relative balance of the PE cycles of the counter in the nonvolatile memory, thereby reducing the size of the nonvolatile memory and the area of a chip.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a counting method of an enhanced flash and the enhanced flash.
Background
Currently, an enhanced FLASH with a Response Protection Monotonic Calculator (RPMC) is a Basic Input-Output System (BIOS) chip that is pushed by Intel and includes a large-capacity FLASH chip and RPMC circuitry. Among them, the RPMC circuit is the focus of design, and the requirements of the RPMC circuit are non-volatile and monotonically increasing. In order to meet the requirement, the current design method is to use a nonvolatile memory to directly correspond to four sets of 32-bit RPMCs, because each set of RPMCs is 32 bits, assuming that the product is guaranteed to be updated 5 times in 1 minute for 10 years, the required PE cycle (number of times of erasing) is 10x365x24x60x5 ═ 26,280,000, whereas the PE cycle of the conventional nonvolatile memory is only 100,000 times, and a set of 32-bit RPMCs is 8,410bits of nonvolatile memory, and the current design method needs too many nonvolatile memories.
Disclosure of Invention
The invention mainly aims to solve the technical problem that the enhanced FLASH in the prior art needs too much nonvolatile memory.
In order to achieve the above object, the present invention provides a counting method of an enhanced flash, the method being applied to an enhanced flash, the enhanced flash including a counting unit, a remapping unit and a non-volatile memory control unit, the method including:
when the rising edge of the clock signal and the added signal are simultaneously effective, the counting unit increases 1 on the basis of the initial value to obtain the current counting value, and the counting value is input into the remapping unit;
the remapping unit carries out high-low bit conversion on the counting value to obtain a remapped counting value;
the non-volatile memory control unit writes the remapped count value to non-volatile memory.
Optionally, when the rising edge of the clock signal and the increment signal are simultaneously valid, the counter increments by 1 on the basis of an initial value to obtain a current count value, and inputs the count value to the remapping unit, and the method further includes:
when the rising edge of the clock signal and the load signal are simultaneously valid, the counting unit loads data from the remapping unit as initial values.
Optionally, the count value is a 32-bit value.
Optionally, the remapping unit performs high-low bit swapping on the count value to obtain a remapped count value, where the remapped count value includes:
the remapping unit keeps the 16 th bit and the 17 th bit of the count value unchanged, and exchanges the value of the nth bit with the value of the mth bit to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
In addition, to achieve the above object, the present invention further provides an enhanced flash, including:
the counting unit is used for increasing 1 on the basis of an initial value when the rising edge of the clock signal and the increasing signal are simultaneously effective to obtain a current counting value, and inputting the counting value into the remapping unit;
the remapping unit is used for carrying out high-low bit conversion on the counting value to obtain a remapped counting value;
a non-volatile memory control unit for writing the remapped count value to a non-volatile memory.
Optionally, the counting unit is configured to:
when the rising edge of the clock signal and the load signal are simultaneously active, data is loaded from the remapping unit as an initial value.
Optionally, the counting unit is a 32-bit counter, and the count value is a 32-bit value.
Optionally, the remapping unit is configured to:
the 16 th bit and the 17 th bit of the count value are kept unchanged, and the value of the nth bit and the value of the mth bit are exchanged to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
When the rising edge of the clock signal and the added signal are simultaneously effective, the counting unit increases 1 on the basis of the initial value to obtain the current counting value, and the counting value is input into the remapping unit; the remapping unit carries out high-low bit conversion on the counting value to obtain a remapped counting value; the non-volatile memory control unit writes the remapped count value to non-volatile memory. The invention realizes the relative equalization of the PEcycles of the counters in the nonvolatile memory, thereby reducing the size of the nonvolatile memory and reducing the chip area.
Drawings
FIG. 1 is a flowchart illustrating an enhanced flash counting method according to an embodiment of the present invention;
fig. 2 is a functional block diagram of an enhanced flash according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
Since the prior art uses the non-volatile memory to directly correspond to four sets of 32-bit RPMCs, because each set of RPMC is 32 bits, assuming that the product is guaranteed to be updated 5 times in 10 years and 1 minute, the required PE cycle is 10x365x24x60x5 ═ 26,280,000, while the PE cycle of the conventional non-volatile memory is only 100,000 times, and one set of 32-bit RPMC is 8,410bits of non-volatile memory, the current design method needs too many non-volatile memories. Resulting in a larger size of the non-volatile memory required in existing enhanced FLASH, resulting in a larger chip area. In order to solve this problem, the embodiment of the present invention implements relative balancing of PE cycles of the counters stored in the nonvolatile memory through a mapping mechanism, so as to reduce the size of the nonvolatile memory, and thus reduce the chip area.
Referring to fig. 1, fig. 1 is a flowchart illustrating an enhanced flash counting method according to an embodiment of the present invention. In one embodiment, a counting method of an enhanced flash is applied to the enhanced flash, wherein the enhanced flash comprises a counting unit, a remapping unit and a nonvolatile memory control unit, and the method comprises the following steps:
step S10, when the rising edge of the clock signal and the added signal are both valid, the counting unit adds 1 on the basis of the initial value to obtain the current count value, and inputs the count value into the remapping unit;
in this embodiment, the counting unit is a counter for receiving the clock signal CLK, the LOAD signal and the INC signal. When the rising edge of the clock signal CLK and the INC signal are simultaneously active, the initial value in the current counter is incremented by 1 to obtain a new value (i.e., count value) and the new value is sent to the remapping unit.
In an embodiment, before step S10, the method further includes:
when the rising edge of the clock signal and the load signal are simultaneously valid, the counting unit loads data from the remapping unit as initial values.
The counting unit is a counter for receiving the clock signal CLK, the LOAD signal and the INC signal, and when the rising edge of the clock signal CLK and the LOAD signal are simultaneously active, data is loaded from the remapping unit as an initial value of the counting unit.
Step S20, the remapping unit performs high-low bit swapping on the count value to obtain a remapped count value;
in this embodiment, the remapping unit performs high-low permutation on the input count value, that is, permutes the value on the high order with the value on the low order, to obtain the remapped count value.
In one embodiment, the count unit is a 32-bit counter, and the count value of the input remap unit is a 32-bit value.
On the basis that the count value is a 32-bit value, step S20 includes:
the remapping unit keeps the 16 th bit and the 17 th bit of the count value unchanged, and exchanges the value of the nth bit with the value of the mth bit to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
In this embodiment, when the count value is a 32-bit value, the remapping unit keeps the 16 th bit and the 17 th bit of the count value unchanged, and exchanges the value of the nth bit with the value of the mth bit to obtain the remapped count value, where N is 1, 2, 3, … …, 15, and N + M is 33. That is, the value at the 1 st bit of the count value is exchanged with the value at the 32 nd bit, the value at the 2 nd bit of the count value is exchanged with the value at the 31 st bit, the value at the 3 rd bit of the count value is exchanged with the value at the 30 th bit, the value at the 4 th bit of the count value is exchanged with the value at the 29 th bit, the value at the 5 th bit of the count value is exchanged with the value at the 28 th bit, the value at the 6 th bit of the count value is exchanged with the value at the 27 th bit, the value at the 7 th bit of the count value is exchanged with the value at the 26 th bit, the value at the 8 th bit of the count value is exchanged with the value at the 25 th bit, the value at the 9 th bit of the count value is exchanged with the value at the 24 th bit, the value at the 10 th bit of the count value is exchanged with the value at the 23 th bit, the value at the 11 th bit of the count value is exchanged with the value at the 22 nd bit, the value at the 12 th bit of the count, the value at the 13 th bit of the count value is exchanged with the value at the 20 th bit, the value at the 14 th bit of the count value is exchanged with the value at the 19 th bit, the value at the 15 th bit of the count value is exchanged with the value at the 18 th bit, and the remapped count value is obtained by the exchange processing. By the remapping process proposed in this embodiment, the PE cycles of the upper bits and the lower bits are relatively equalized. The above-described high-low bit swapping process may be performed when the 16 th bit of the count value is equal to 0. That is, when the count value is a 32-bit value and the 16 th bit of the count value is 0, the remapping unit keeps the 16 th bit and the 17 th bit of the count value unchanged, and exchanges the value of the nth bit with the value of the mth bit to obtain a remapped count value, where N is 1, 2, 3, … …, 15, and N + M is 33.
As shown in Table 1, Table 1 is an indication of the number of PE cycles required for each bit in a 4-bit counter in the prior art without using remapping.
TABLE 1
As can be seen from table 1, instead of using the remapping process proposed in this embodiment, the maximum PE cycle value of 16 is required in all the bits of the counter.
Referring to table 2, table 2 is an exemplary table of the number of cycles required for each bit in the remapping process for a 4-bit counter.
TABLE 2
As can be seen from table 2, if the remapping process proposed in this embodiment is used, the maximum PE cycle value of 8 is required in all the bits of the counter. As is clear from comparison with table 1, the maximum required cycle of all bits of the counter is reduced by half, and therefore, the size of the required nonvolatile memory can be reduced by half, thereby reducing the chip area.
Referring to table 3, table 3 shows the number of PE cycles required for each bit when a 32-bit counter does not adopt the remapping process and the Bits of the corresponding non-volatile memory (nvm memory) in the prior art.
TABLE 3
As shown in Table 3, when a 32-bit counter in the prior art does not employ remapping, the Bits of the required non-volatile memory is 64K.
Referring to table 4, table 4 shows the number of cycles required for each bit in the remapping process and the Bits of the corresponding non-volatile memory (nvm memory) for a 32-bit counter.
TABLE 4
As shown in table 4, when a 32-bit counter is remapped, Bits of the required nonvolatile memory is 32K. Therefore, by the remapping process proposed by this embodiment, the size of the required nonvolatile memory can be reduced by half, thereby reducing the area of the chip.
In step S30, the nonvolatile memory control unit writes the remapped count value to the nonvolatile memory.
In this embodiment, after obtaining the remapped count value based on step S20, the nonvolatile memory control unit writes the remapped count value into the nonvolatile memory.
In this embodiment, when the rising edge of the clock signal and the added signal are simultaneously valid, the counting unit adds 1 on the basis of the initial value to obtain the current count value, and inputs the count value into the remapping unit; the remapping unit carries out high-low bit conversion on the counting value to obtain a remapped counting value; the non-volatile memory control unit writes the remapped count value to non-volatile memory. By the embodiment, the relative balance of the PE cycles of the counter in the nonvolatile memory is realized, so that the size of the nonvolatile memory is reduced, and the chip area is reduced.
Referring to fig. 2, fig. 2 is a functional block diagram of an enhanced flash according to an embodiment of the present invention. In one embodiment, an enhanced flash includes:
a counting unit 10, configured to increase 1 based on an initial value when a rising edge of a clock signal and an increase signal are simultaneously valid, to obtain a current count value, and input the count value to the remapping unit;
a remapping unit 20, configured to perform high-low bit swapping on the count value to obtain a remapped count value;
a non-volatile memory control unit 30 for writing the remapped count value to a non-volatile memory.
Further, in an embodiment, the counting unit 10 is configured to:
when the rising edge of the clock signal and the load signal are simultaneously active, data is loaded from the remapping unit as an initial value.
Further, in an embodiment, the counting unit 10 is a 32-bit counter, and the count value is a 32-bit value.
Further, in an embodiment, the remapping unit 20 is configured to:
the 16 th bit and the 17 th bit of the count value are kept unchanged, and the value of the nth bit and the value of the mth bit are exchanged to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
The specific embodiment of the enhanced flash of the present invention is basically the same as the embodiments of the counting method of the enhanced flash described above, and details are not described herein.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some or all of the components in accordance with embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (8)
1. A counting method of an enhanced flash, the method is applied to the enhanced flash, the enhanced flash comprises a counting unit, a remapping unit and a nonvolatile memory control unit, and the method comprises the following steps:
when the rising edge of the clock signal and the added signal are simultaneously effective, the counting unit increases 1 on the basis of the initial value to obtain the current counting value, and the counting value is input into the remapping unit;
the remapping unit carries out high-low bit conversion on the counting value to obtain a remapped counting value;
the non-volatile memory control unit writes the remapped count value to non-volatile memory.
2. The method as claimed in claim 1, wherein the counter increments by 1 based on an initial value when the rising edge of the clock signal and the increment signal are simultaneously active, obtains a current count value, and inputs the count value to the remapping unit, further comprising:
when the rising edge of the clock signal and the load signal are simultaneously valid, the counting unit loads data from the remapping unit as initial values.
3. The method of claim 1, wherein the count value is a 32-bit value.
4. The method of claim 3, wherein the remapping unit permutes the count value high and low to obtain a remapped count value comprising:
the remapping unit keeps the 16 th bit and the 17 th bit of the count value unchanged, and exchanges the value of the nth bit with the value of the mth bit to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
5. An enhanced flash, comprising:
the counting unit is used for increasing 1 on the basis of an initial value when the rising edge of the clock signal and the increasing signal are simultaneously effective to obtain a current counting value, and inputting the counting value into the remapping unit;
the remapping unit is used for carrying out high-low bit conversion on the counting value to obtain a remapped counting value;
a non-volatile memory control unit for writing the remapped count value to a non-volatile memory.
6. The enhanced flash of claim 5, wherein said counting unit is to:
when the rising edge of the clock signal and the load signal are simultaneously active, data is loaded from the remapping unit as an initial value.
7. The enhanced flash of claim 5 wherein said count unit is a 32-bit counter and said count value is a 32-bit value.
8. The enhanced flash of claim 7, wherein said remapping unit is for:
the 16 th bit and the 17 th bit of the count value are kept unchanged, and the value of the nth bit and the value of the mth bit are exchanged to obtain a remapped count value, wherein N is 1, 2, 3, … …, 15, and N + M is 33.
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